1 files changed, 10 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 979228594599..932a061f28d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2044,9 +2044,11 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                                 reg = I915_READ(trans_dp_ctl);
                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
-                                         TRANS_DP_SYNC_MASK);
+                                         TRANS_DP_SYNC_MASK |
+                                         TRANS_DP_BPC_MASK);
                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
                                         TRANS_DP_ENH_FRAMING);
+                                reg |= TRANS_DP_8BPC;
 
                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
@@ -5674,6 +5676,13 @@ void intel_init_clock_gating(struct drm_device *dev)
                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 
                 /*
+                 * On Ibex Peak and Cougar Point, we need to disable clock
+                 * gating for the panel power sequencer or it will fail to
+                 * start up when no ports are active.
+                 */
+                I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+
+                /*
                  * According to the spec the following bits should be set in
                  * order to enable memory self-refresh
                  * The bit 22/21 of 0x42004