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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1832
1 files changed, 1176 insertions, 656 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 099f420de57a..c7502b6b1600 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -28,11 +28,12 @@
28#include <linux/input.h> 28#include <linux/input.h>
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/slab.h>
31#include "drmP.h" 32#include "drmP.h"
32#include "intel_drv.h" 33#include "intel_drv.h"
33#include "i915_drm.h" 34#include "i915_drm.h"
34#include "i915_drv.h" 35#include "i915_drv.h"
35#include "intel_dp.h" 36#include "drm_dp_helper.h"
36 37
37#include "drm_crtc_helper.h" 38#include "drm_crtc_helper.h"
38 39
@@ -70,8 +71,6 @@ struct intel_limit {
70 intel_p2_t p2; 71 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 72 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *); 73 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75}; 74};
76 75
77#define I8XX_DOT_MIN 25000 76#define I8XX_DOT_MIN 25000
@@ -102,32 +101,32 @@ struct intel_limit {
102#define I9XX_DOT_MAX 400000 101#define I9XX_DOT_MAX 400000
103#define I9XX_VCO_MIN 1400000 102#define I9XX_VCO_MIN 1400000
104#define I9XX_VCO_MAX 2800000 103#define I9XX_VCO_MAX 2800000
105#define IGD_VCO_MIN 1700000 104#define PINEVIEW_VCO_MIN 1700000
106#define IGD_VCO_MAX 3500000 105#define PINEVIEW_VCO_MAX 3500000
107#define I9XX_N_MIN 1 106#define I9XX_N_MIN 1
108#define I9XX_N_MAX 6 107#define I9XX_N_MAX 6
109/* IGD's Ncounter is a ring counter */ 108/* Pineview's Ncounter is a ring counter */
110#define IGD_N_MIN 3 109#define PINEVIEW_N_MIN 3
111#define IGD_N_MAX 6 110#define PINEVIEW_N_MAX 6
112#define I9XX_M_MIN 70 111#define I9XX_M_MIN 70
113#define I9XX_M_MAX 120 112#define I9XX_M_MAX 120
114#define IGD_M_MIN 2 113#define PINEVIEW_M_MIN 2
115#define IGD_M_MAX 256 114#define PINEVIEW_M_MAX 256
116#define I9XX_M1_MIN 10 115#define I9XX_M1_MIN 10
117#define I9XX_M1_MAX 22 116#define I9XX_M1_MAX 22
118#define I9XX_M2_MIN 5 117#define I9XX_M2_MIN 5
119#define I9XX_M2_MAX 9 118#define I9XX_M2_MAX 9
120/* IGD M1 is reserved, and must be 0 */ 119/* Pineview M1 is reserved, and must be 0 */
121#define IGD_M1_MIN 0 120#define PINEVIEW_M1_MIN 0
122#define IGD_M1_MAX 0 121#define PINEVIEW_M1_MAX 0
123#define IGD_M2_MIN 0 122#define PINEVIEW_M2_MIN 0
124#define IGD_M2_MAX 254 123#define PINEVIEW_M2_MAX 254
125#define I9XX_P_SDVO_DAC_MIN 5 124#define I9XX_P_SDVO_DAC_MIN 5
126#define I9XX_P_SDVO_DAC_MAX 80 125#define I9XX_P_SDVO_DAC_MAX 80
127#define I9XX_P_LVDS_MIN 7 126#define I9XX_P_LVDS_MIN 7
128#define I9XX_P_LVDS_MAX 98 127#define I9XX_P_LVDS_MAX 98
129#define IGD_P_LVDS_MIN 7 128#define PINEVIEW_P_LVDS_MIN 7
130#define IGD_P_LVDS_MAX 112 129#define PINEVIEW_P_LVDS_MAX 112
131#define I9XX_P1_MIN 1 130#define I9XX_P1_MIN 1
132#define I9XX_P1_MAX 8 131#define I9XX_P1_MAX 8
133#define I9XX_P2_SDVO_DAC_SLOW 10 132#define I9XX_P2_SDVO_DAC_SLOW 10
@@ -234,53 +233,108 @@ struct intel_limit {
234#define G4X_P2_DISPLAY_PORT_FAST 10 233#define G4X_P2_DISPLAY_PORT_FAST 10
235#define G4X_P2_DISPLAY_PORT_LIMIT 0 234#define G4X_P2_DISPLAY_PORT_LIMIT 0
236 235
237/* IGDNG */ 236/* Ironlake / Sandybridge */
238/* as we calculate clock using (register_value + 2) for 237/* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2). 238 N/M1/M2, so here the range value for them is (actual_value-2).
240 */ 239 */
241#define IGDNG_DOT_MIN 25000 240#define IRONLAKE_DOT_MIN 25000
242#define IGDNG_DOT_MAX 350000 241#define IRONLAKE_DOT_MAX 350000
243#define IGDNG_VCO_MIN 1760000 242#define IRONLAKE_VCO_MIN 1760000
244#define IGDNG_VCO_MAX 3510000 243#define IRONLAKE_VCO_MAX 3510000
245#define IGDNG_N_MIN 1 244#define IRONLAKE_M1_MIN 12
246#define IGDNG_N_MAX 5 245#define IRONLAKE_M1_MAX 22
247#define IGDNG_M_MIN 79 246#define IRONLAKE_M2_MIN 5
248#define IGDNG_M_MAX 118 247#define IRONLAKE_M2_MAX 9
249#define IGDNG_M1_MIN 12 248#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
250#define IGDNG_M1_MAX 23 249
251#define IGDNG_M2_MIN 5 250/* We have parameter ranges for different type of outputs. */
252#define IGDNG_M2_MAX 9 251
253#define IGDNG_P_SDVO_DAC_MIN 5 252/* DAC & HDMI Refclk 120Mhz */
254#define IGDNG_P_SDVO_DAC_MAX 80 253#define IRONLAKE_DAC_N_MIN 1
255#define IGDNG_P_LVDS_MIN 28 254#define IRONLAKE_DAC_N_MAX 5
256#define IGDNG_P_LVDS_MAX 112 255#define IRONLAKE_DAC_M_MIN 79
257#define IGDNG_P1_MIN 1 256#define IRONLAKE_DAC_M_MAX 127
258#define IGDNG_P1_MAX 8 257#define IRONLAKE_DAC_P_MIN 5
259#define IGDNG_P2_SDVO_DAC_SLOW 10 258#define IRONLAKE_DAC_P_MAX 80
260#define IGDNG_P2_SDVO_DAC_FAST 5 259#define IRONLAKE_DAC_P1_MIN 1
261#define IGDNG_P2_LVDS_SLOW 14 /* single channel */ 260#define IRONLAKE_DAC_P1_MAX 8
262#define IGDNG_P2_LVDS_FAST 7 /* double channel */ 261#define IRONLAKE_DAC_P2_SLOW 10
263#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ 262#define IRONLAKE_DAC_P2_FAST 5
263
264/* LVDS single-channel 120Mhz refclk */
265#define IRONLAKE_LVDS_S_N_MIN 1
266#define IRONLAKE_LVDS_S_N_MAX 3
267#define IRONLAKE_LVDS_S_M_MIN 79
268#define IRONLAKE_LVDS_S_M_MAX 118
269#define IRONLAKE_LVDS_S_P_MIN 28
270#define IRONLAKE_LVDS_S_P_MAX 112
271#define IRONLAKE_LVDS_S_P1_MIN 2
272#define IRONLAKE_LVDS_S_P1_MAX 8
273#define IRONLAKE_LVDS_S_P2_SLOW 14
274#define IRONLAKE_LVDS_S_P2_FAST 14
275
276/* LVDS dual-channel 120Mhz refclk */
277#define IRONLAKE_LVDS_D_N_MIN 1
278#define IRONLAKE_LVDS_D_N_MAX 3
279#define IRONLAKE_LVDS_D_M_MIN 79
280#define IRONLAKE_LVDS_D_M_MAX 127
281#define IRONLAKE_LVDS_D_P_MIN 14
282#define IRONLAKE_LVDS_D_P_MAX 56
283#define IRONLAKE_LVDS_D_P1_MIN 2
284#define IRONLAKE_LVDS_D_P1_MAX 8
285#define IRONLAKE_LVDS_D_P2_SLOW 7
286#define IRONLAKE_LVDS_D_P2_FAST 7
287
288/* LVDS single-channel 100Mhz refclk */
289#define IRONLAKE_LVDS_S_SSC_N_MIN 1
290#define IRONLAKE_LVDS_S_SSC_N_MAX 2
291#define IRONLAKE_LVDS_S_SSC_M_MIN 79
292#define IRONLAKE_LVDS_S_SSC_M_MAX 126
293#define IRONLAKE_LVDS_S_SSC_P_MIN 28
294#define IRONLAKE_LVDS_S_SSC_P_MAX 112
295#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299
300/* LVDS dual-channel 100Mhz refclk */
301#define IRONLAKE_LVDS_D_SSC_N_MIN 1
302#define IRONLAKE_LVDS_D_SSC_N_MAX 3
303#define IRONLAKE_LVDS_D_SSC_M_MIN 79
304#define IRONLAKE_LVDS_D_SSC_M_MAX 126
305#define IRONLAKE_LVDS_D_SSC_P_MIN 14
306#define IRONLAKE_LVDS_D_SSC_P_MAX 42
307#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
311
312/* DisplayPort */
313#define IRONLAKE_DP_N_MIN 1
314#define IRONLAKE_DP_N_MAX 2
315#define IRONLAKE_DP_M_MIN 81
316#define IRONLAKE_DP_M_MAX 90
317#define IRONLAKE_DP_P_MIN 10
318#define IRONLAKE_DP_P_MAX 20
319#define IRONLAKE_DP_P2_FAST 10
320#define IRONLAKE_DP_P2_SLOW 10
321#define IRONLAKE_DP_P2_LIMIT 0
322#define IRONLAKE_DP_P1_MIN 1
323#define IRONLAKE_DP_P1_MAX 2
264 324
265static bool 325static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 326intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock); 327 int target, int refclk, intel_clock_t *best_clock);
268static bool 328static bool
269intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271static bool
272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 329intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock); 330 int target, int refclk, intel_clock_t *best_clock);
274static bool
275intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277 331
278static bool 332static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 333intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock); 334 int target, int refclk, intel_clock_t *best_clock);
281static bool 335static bool
282intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc, 336intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock); 337 int target, int refclk, intel_clock_t *best_clock);
284 338
285static const intel_limit_t intel_limits_i8xx_dvo = { 339static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 340 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
@@ -294,7 +348,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 348 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, 349 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL, 350 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
298}; 351};
299 352
300static const intel_limit_t intel_limits_i8xx_lvds = { 353static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -309,7 +362,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 362 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, 363 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL, 364 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
313}; 365};
314 366
315static const intel_limit_t intel_limits_i9xx_sdvo = { 367static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -324,7 +376,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 376 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 377 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL, 378 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
328}; 379};
329 380
330static const intel_limit_t intel_limits_i9xx_lvds = { 381static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -342,7 +393,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 393 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, 394 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL, 395 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
346}; 396};
347 397
348 /* below parameter and function is for G4X Chipset Family*/ 398 /* below parameter and function is for G4X Chipset Family*/
@@ -360,7 +410,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
360 .p2_fast = G4X_P2_SDVO_FAST 410 .p2_fast = G4X_P2_SDVO_FAST
361 }, 411 },
362 .find_pll = intel_g4x_find_best_PLL, 412 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
364}; 413};
365 414
366static const intel_limit_t intel_limits_g4x_hdmi = { 415static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -377,7 +426,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
377 .p2_fast = G4X_P2_HDMI_DAC_FAST 426 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 }, 427 },
379 .find_pll = intel_g4x_find_best_PLL, 428 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
381}; 429};
382 430
383static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 431static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -402,7 +450,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST 450 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 }, 451 },
404 .find_pll = intel_g4x_find_best_PLL, 452 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
406}; 453};
407 454
408static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 455static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -427,7 +474,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST 474 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 }, 475 },
429 .find_pll = intel_g4x_find_best_PLL, 476 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
431}; 477};
432 478
433static const intel_limit_t intel_limits_g4x_display_port = { 479static const intel_limit_t intel_limits_g4x_display_port = {
@@ -453,74 +499,162 @@ static const intel_limit_t intel_limits_g4x_display_port = {
453 .find_pll = intel_find_pll_g4x_dp, 499 .find_pll = intel_find_pll_g4x_dp,
454}; 500};
455 501
456static const intel_limit_t intel_limits_igd_sdvo = { 502static const intel_limit_t intel_limits_pineview_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 503 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 504 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, 505 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, 506 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, 507 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, 508 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, 509 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 510 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 511 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 512 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL, 513 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
469}; 514};
470 515
471static const intel_limit_t intel_limits_igd_lvds = { 516static const intel_limit_t intel_limits_pineview_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 517 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 518 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, 519 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, 520 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, 521 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, 522 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, 523 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 524 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */ 525 /* Pineview only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 526 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 527 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL, 528 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
485}; 529};
486 530
487static const intel_limit_t intel_limits_igdng_sdvo = { 531static const intel_limit_t intel_limits_ironlake_dac = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, 532 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, 533 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, 534 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, 535 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, 536 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, 537 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, 538 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, 539 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, 540 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, 541 .p2_slow = IRONLAKE_DAC_P2_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, 542 .p2_fast = IRONLAKE_DAC_P2_FAST },
499 .find_pll = intel_igdng_find_best_PLL, 543 .find_pll = intel_g4x_find_best_PLL,
544};
545
546static const intel_limit_t intel_limits_ironlake_single_lvds = {
547 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
548 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
549 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
550 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
551 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
552 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
553 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
554 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
555 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558 .find_pll = intel_g4x_find_best_PLL,
559};
560
561static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
563 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
564 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
565 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
566 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
567 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
568 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
569 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
570 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573 .find_pll = intel_g4x_find_best_PLL,
574};
575
576static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
578 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
579 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
582 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
583 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588 .find_pll = intel_g4x_find_best_PLL,
500}; 589};
501 590
502static const intel_limit_t intel_limits_igdng_lvds = { 591static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, 592 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, 593 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, 594 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, 595 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, 596 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, 597 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, 598 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, 599 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, 600 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW, 601 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST }, 602 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
514 .find_pll = intel_igdng_find_best_PLL, 603 .find_pll = intel_g4x_find_best_PLL,
515}; 604};
516 605
517static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) 606static const intel_limit_t intel_limits_ironlake_display_port = {
607 .dot = { .min = IRONLAKE_DOT_MIN,
608 .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN,
610 .max = IRONLAKE_VCO_MAX},
611 .n = { .min = IRONLAKE_DP_N_MIN,
612 .max = IRONLAKE_DP_N_MAX },
613 .m = { .min = IRONLAKE_DP_M_MIN,
614 .max = IRONLAKE_DP_M_MAX },
615 .m1 = { .min = IRONLAKE_M1_MIN,
616 .max = IRONLAKE_M1_MAX },
617 .m2 = { .min = IRONLAKE_M2_MIN,
618 .max = IRONLAKE_M2_MAX },
619 .p = { .min = IRONLAKE_DP_P_MIN,
620 .max = IRONLAKE_DP_P_MAX },
621 .p1 = { .min = IRONLAKE_DP_P1_MIN,
622 .max = IRONLAKE_DP_P1_MAX},
623 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624 .p2_slow = IRONLAKE_DP_P2_SLOW,
625 .p2_fast = IRONLAKE_DP_P2_FAST },
626 .find_pll = intel_find_pll_ironlake_dp,
627};
628
629static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
518{ 630{
631 struct drm_device *dev = crtc->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
519 const intel_limit_t *limit; 633 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 634 int refclk = 120;
521 limit = &intel_limits_igdng_lvds; 635
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638 refclk = 100;
639
640 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641 LVDS_CLKB_POWER_UP) {
642 /* LVDS dual channel */
643 if (refclk == 100)
644 limit = &intel_limits_ironlake_dual_lvds_100m;
645 else
646 limit = &intel_limits_ironlake_dual_lvds;
647 } else {
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_single_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_single_lvds;
652 }
653 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654 HAS_eDP)
655 limit = &intel_limits_ironlake_display_port;
522 else 656 else
523 limit = &intel_limits_igdng_sdvo; 657 limit = &intel_limits_ironlake_dac;
524 658
525 return limit; 659 return limit;
526} 660}
@@ -557,20 +691,20 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
557 struct drm_device *dev = crtc->dev; 691 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit; 692 const intel_limit_t *limit;
559 693
560 if (IS_IGDNG(dev)) 694 if (HAS_PCH_SPLIT(dev))
561 limit = intel_igdng_limit(crtc); 695 limit = intel_ironlake_limit(crtc);
562 else if (IS_G4X(dev)) { 696 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc); 697 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) { 698 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 699 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds; 700 limit = &intel_limits_i9xx_lvds;
567 else 701 else
568 limit = &intel_limits_i9xx_sdvo; 702 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) { 703 } else if (IS_PINEVIEW(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds; 705 limit = &intel_limits_pineview_lvds;
572 else 706 else
573 limit = &intel_limits_igd_sdvo; 707 limit = &intel_limits_pineview_sdvo;
574 } else { 708 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds; 710 limit = &intel_limits_i8xx_lvds;
@@ -580,8 +714,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
580 return limit; 714 return limit;
581} 715}
582 716
583/* m1 is reserved as 0 in IGD, n is a ring counter */ 717/* m1 is reserved as 0 in Pineview, n is a ring counter */
584static void igd_clock(int refclk, intel_clock_t *clock) 718static void pineview_clock(int refclk, intel_clock_t *clock)
585{ 719{
586 clock->m = clock->m2 + 2; 720 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2; 721 clock->p = clock->p1 * clock->p2;
@@ -591,8 +725,8 @@ static void igd_clock(int refclk, intel_clock_t *clock)
591 725
592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 726static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593{ 727{
594 if (IS_IGD(dev)) { 728 if (IS_PINEVIEW(dev)) {
595 igd_clock(refclk, clock); 729 pineview_clock(refclk, clock);
596 return; 730 return;
597 } 731 }
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 732 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
@@ -613,16 +747,16 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 747 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder && 748 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) { 749 l_entry->encoder->crtc == crtc) {
616 struct intel_output *intel_output = to_intel_output(l_entry); 750 struct intel_encoder *intel_encoder = to_intel_encoder(l_entry);
617 if (intel_output->type == type) 751 if (intel_encoder->type == type)
618 return true; 752 return true;
619 } 753 }
620 } 754 }
621 return false; 755 return false;
622} 756}
623 757
624struct drm_connector * 758static struct drm_connector *
625intel_pipe_get_output (struct drm_crtc *crtc) 759intel_pipe_get_connector (struct drm_crtc *crtc)
626{ 760{
627 struct drm_device *dev = crtc->dev; 761 struct drm_device *dev = crtc->dev;
628 struct drm_mode_config *mode_config = &dev->mode_config; 762 struct drm_mode_config *mode_config = &dev->mode_config;
@@ -657,7 +791,7 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
657 INTELPllInvalid ("m2 out of range\n"); 791 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 792 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n"); 793 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev)) 794 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
661 INTELPllInvalid ("m1 <= m2\n"); 795 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m) 796 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n"); 797 INTELPllInvalid ("m out of range\n");
@@ -706,16 +840,17 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
706 840
707 memset (best_clock, 0, sizeof (*best_clock)); 841 memset (best_clock, 0, sizeof (*best_clock));
708 842
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 843 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 844 clock.m1++) {
711 clock.m1++) { 845 for (clock.m2 = limit->m2.min;
712 for (clock.m2 = limit->m2.min; 846 clock.m2 <= limit->m2.max; clock.m2++) {
713 clock.m2 <= limit->m2.max; clock.m2++) { 847 /* m1 is always 0 in Pineview */
714 /* m1 is always 0 in IGD */ 848 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 849 break;
716 break; 850 for (clock.n = limit->n.min;
717 for (clock.n = limit->n.min; 851 clock.n <= limit->n.max; clock.n++) {
718 clock.n <= limit->n.max; clock.n++) { 852 for (clock.p1 = limit->p1.min;
853 clock.p1 <= limit->p1.max; clock.p1++) {
719 int this_err; 854 int this_err;
720 855
721 intel_clock(dev, refclk, &clock); 856 intel_clock(dev, refclk, &clock);
@@ -736,46 +871,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
736 return (err != target); 871 return (err != target);
737} 872}
738 873
739
740static bool
741intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *best_clock)
743
744{
745 struct drm_device *dev = crtc->dev;
746 intel_clock_t clock;
747 int err = target;
748 bool found = false;
749
750 memcpy(&clock, best_clock, sizeof(intel_clock_t));
751
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754 /* m1 is always 0 in IGD */
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
756 break;
757 for (clock.n = limit->n.min; clock.n <= limit->n.max;
758 clock.n++) {
759 int this_err;
760
761 intel_clock(dev, refclk, &clock);
762
763 if (!intel_PLL_is_valid(crtc, &clock))
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 found = true;
771 }
772 }
773 }
774 }
775
776 return found;
777}
778
779static bool 874static bool
780intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 875intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
781 int target, int refclk, intel_clock_t *best_clock) 876 int target, int refclk, intel_clock_t *best_clock)
@@ -790,7 +885,13 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
790 found = false; 885 found = false;
791 886
792 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 887 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
793 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 888 int lvds_reg;
889
890 if (HAS_PCH_SPLIT(dev))
891 lvds_reg = PCH_LVDS;
892 else
893 lvds_reg = LVDS;
894 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
794 LVDS_CLKB_POWER_UP) 895 LVDS_CLKB_POWER_UP)
795 clock.p2 = limit->p2.p2_fast; 896 clock.p2 = limit->p2.p2_fast;
796 else 897 else
@@ -833,11 +934,16 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
833} 934}
834 935
835static bool 936static bool
836intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 937intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock) 938 int target, int refclk, intel_clock_t *best_clock)
838{ 939{
839 struct drm_device *dev = crtc->dev; 940 struct drm_device *dev = crtc->dev;
840 intel_clock_t clock; 941 intel_clock_t clock;
942
943 /* return directly when it is eDP */
944 if (HAS_eDP)
945 return true;
946
841 if (target < 200000) { 947 if (target < 200000) {
842 clock.n = 1; 948 clock.n = 1;
843 clock.p1 = 2; 949 clock.p1 = 2;
@@ -856,68 +962,6 @@ intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
856 return true; 962 return true;
857} 963}
858 964
859static bool
860intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862{
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int err_most = 47;
867 int err_min = 10000;
868
869 /* eDP has only 2 clock choice, no n/m/p setting */
870 if (HAS_eDP)
871 return true;
872
873 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
874 return intel_find_pll_igdng_dp(limit, crtc, target,
875 refclk, best_clock);
876
877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
878 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
879 LVDS_CLKB_POWER_UP)
880 clock.p2 = limit->p2.p2_fast;
881 else
882 clock.p2 = limit->p2.p2_slow;
883 } else {
884 if (target < limit->p2.dot_limit)
885 clock.p2 = limit->p2.p2_slow;
886 else
887 clock.p2 = limit->p2.p2_fast;
888 }
889
890 memset(best_clock, 0, sizeof(*best_clock));
891 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
892 /* based on hardware requriment prefer smaller n to precision */
893 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
894 /* based on hardware requirment prefere larger m1,m2 */
895 for (clock.m1 = limit->m1.max;
896 clock.m1 >= limit->m1.min; clock.m1--) {
897 for (clock.m2 = limit->m2.max;
898 clock.m2 >= limit->m2.min; clock.m2--) {
899 int this_err;
900
901 intel_clock(dev, refclk, &clock);
902 if (!intel_PLL_is_valid(crtc, &clock))
903 continue;
904 this_err = abs((10000 - (target*10000/clock.dot)));
905 if (this_err < err_most) {
906 *best_clock = clock;
907 /* found on first matching */
908 goto out;
909 } else if (this_err < err_min) {
910 *best_clock = clock;
911 err_min = this_err;
912 }
913 }
914 }
915 }
916 }
917out:
918 return true;
919}
920
921/* DisplayPort has only two frequencies, 162MHz and 270MHz */ 965/* DisplayPort has only two frequencies, 162MHz and 270MHz */
922static bool 966static bool
923intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 967intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -949,7 +993,7 @@ void
949intel_wait_for_vblank(struct drm_device *dev) 993intel_wait_for_vblank(struct drm_device *dev)
950{ 994{
951 /* Wait for 20ms, i.e. one cycle at 50hz. */ 995 /* Wait for 20ms, i.e. one cycle at 50hz. */
952 mdelay(20); 996 msleep(20);
953} 997}
954 998
955/* Parameters have changed, update FBC info */ 999/* Parameters have changed, update FBC info */
@@ -959,7 +1003,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
959 struct drm_i915_private *dev_priv = dev->dev_private; 1003 struct drm_i915_private *dev_priv = dev->dev_private;
960 struct drm_framebuffer *fb = crtc->fb; 1004 struct drm_framebuffer *fb = crtc->fb;
961 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1005 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
962 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private; 1006 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
964 int plane, i; 1008 int plane, i;
965 u32 fbc_ctl, fbc_ctl2; 1009 u32 fbc_ctl, fbc_ctl2;
@@ -988,13 +1032,15 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
988 1032
989 /* enable it... */ 1033 /* enable it... */
990 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 1034 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1035 if (IS_I945GM(dev))
1036 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
991 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 1037 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
992 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 1038 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
993 if (obj_priv->tiling_mode != I915_TILING_NONE) 1039 if (obj_priv->tiling_mode != I915_TILING_NONE)
994 fbc_ctl |= dev_priv->cfb_fence; 1040 fbc_ctl |= dev_priv->cfb_fence;
995 I915_WRITE(FBC_CONTROL, fbc_ctl); 1041 I915_WRITE(FBC_CONTROL, fbc_ctl);
996 1042
997 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ", 1043 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
998 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); 1044 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
999} 1045}
1000 1046
@@ -1017,7 +1063,7 @@ void i8xx_disable_fbc(struct drm_device *dev)
1017 1063
1018 intel_wait_for_vblank(dev); 1064 intel_wait_for_vblank(dev);
1019 1065
1020 DRM_DEBUG("disabled FBC\n"); 1066 DRM_DEBUG_KMS("disabled FBC\n");
1021} 1067}
1022 1068
1023static bool i8xx_fbc_enabled(struct drm_crtc *crtc) 1069static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
@@ -1034,7 +1080,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1034 struct drm_i915_private *dev_priv = dev->dev_private; 1080 struct drm_i915_private *dev_priv = dev->dev_private;
1035 struct drm_framebuffer *fb = crtc->fb; 1081 struct drm_framebuffer *fb = crtc->fb;
1036 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1082 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private; 1083 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : 1085 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1040 DPFC_CTL_PLANEB); 1086 DPFC_CTL_PLANEB);
@@ -1062,7 +1108,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 /* enable it... */ 1108 /* enable it... */
1063 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 1109 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1064 1110
1065 DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane); 1111 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1066} 1112}
1067 1113
1068void g4x_disable_fbc(struct drm_device *dev) 1114void g4x_disable_fbc(struct drm_device *dev)
@@ -1076,7 +1122,7 @@ void g4x_disable_fbc(struct drm_device *dev)
1076 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1122 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1077 intel_wait_for_vblank(dev); 1123 intel_wait_for_vblank(dev);
1078 1124
1079 DRM_DEBUG("disabled FBC\n"); 1125 DRM_DEBUG_KMS("disabled FBC\n");
1080} 1126}
1081 1127
1082static bool g4x_fbc_enabled(struct drm_crtc *crtc) 1128static bool g4x_fbc_enabled(struct drm_crtc *crtc)
@@ -1130,7 +1176,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1130 return; 1176 return;
1131 1177
1132 intel_fb = to_intel_framebuffer(fb); 1178 intel_fb = to_intel_framebuffer(fb);
1133 obj_priv = intel_fb->obj->driver_private; 1179 obj_priv = to_intel_bo(intel_fb->obj);
1134 1180
1135 /* 1181 /*
1136 * If FBC is already on, we just have to verify that we can 1182 * If FBC is already on, we just have to verify that we can
@@ -1141,25 +1187,32 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1141 * - going to an unsupported config (interlace, pixel multiply, etc.) 1187 * - going to an unsupported config (interlace, pixel multiply, etc.)
1142 */ 1188 */
1143 if (intel_fb->obj->size > dev_priv->cfb_size) { 1189 if (intel_fb->obj->size > dev_priv->cfb_size) {
1144 DRM_DEBUG("framebuffer too large, disabling compression\n"); 1190 DRM_DEBUG_KMS("framebuffer too large, disabling "
1191 "compression\n");
1192 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1145 goto out_disable; 1193 goto out_disable;
1146 } 1194 }
1147 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 1195 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1148 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 1196 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1149 DRM_DEBUG("mode incompatible with compression, disabling\n"); 1197 DRM_DEBUG_KMS("mode incompatible with compression, "
1198 "disabling\n");
1199 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1150 goto out_disable; 1200 goto out_disable;
1151 } 1201 }
1152 if ((mode->hdisplay > 2048) || 1202 if ((mode->hdisplay > 2048) ||
1153 (mode->vdisplay > 1536)) { 1203 (mode->vdisplay > 1536)) {
1154 DRM_DEBUG("mode too large for compression, disabling\n"); 1204 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1205 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1155 goto out_disable; 1206 goto out_disable;
1156 } 1207 }
1157 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { 1208 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1158 DRM_DEBUG("plane not 0, disabling compression\n"); 1209 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1210 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1159 goto out_disable; 1211 goto out_disable;
1160 } 1212 }
1161 if (obj_priv->tiling_mode != I915_TILING_X) { 1213 if (obj_priv->tiling_mode != I915_TILING_X) {
1162 DRM_DEBUG("framebuffer not tiled, disabling compression\n"); 1214 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1215 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1163 goto out_disable; 1216 goto out_disable;
1164 } 1217 }
1165 1218
@@ -1181,13 +1234,57 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1181 return; 1234 return;
1182 1235
1183out_disable: 1236out_disable:
1184 DRM_DEBUG("unsupported config, disabling FBC\n"); 1237 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1185 /* Multiple disables should be harmless */ 1238 /* Multiple disables should be harmless */
1186 if (dev_priv->display.fbc_enabled(crtc)) 1239 if (dev_priv->display.fbc_enabled(crtc))
1187 dev_priv->display.disable_fbc(dev); 1240 dev_priv->display.disable_fbc(dev);
1188} 1241}
1189 1242
1190static int 1243static int
1244intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1245{
1246 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1247 u32 alignment;
1248 int ret;
1249
1250 switch (obj_priv->tiling_mode) {
1251 case I915_TILING_NONE:
1252 alignment = 64 * 1024;
1253 break;
1254 case I915_TILING_X:
1255 /* pin() will align the object as required by fence */
1256 alignment = 0;
1257 break;
1258 case I915_TILING_Y:
1259 /* FIXME: Is this true? */
1260 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1261 return -EINVAL;
1262 default:
1263 BUG();
1264 }
1265
1266 ret = i915_gem_object_pin(obj, alignment);
1267 if (ret != 0)
1268 return ret;
1269
1270 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1271 * fence, whereas 965+ only requires a fence if using
1272 * framebuffer compression. For simplicity, we always install
1273 * a fence as the cost is not that onerous.
1274 */
1275 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1276 obj_priv->tiling_mode != I915_TILING_NONE) {
1277 ret = i915_gem_object_get_fence_reg(obj);
1278 if (ret != 0) {
1279 i915_gem_object_unpin(obj);
1280 return ret;
1281 }
1282 }
1283
1284 return 0;
1285}
1286
1287static int
1191intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 1288intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1192 struct drm_framebuffer *old_fb) 1289 struct drm_framebuffer *old_fb)
1193{ 1290{
@@ -1206,12 +1303,12 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1206 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE; 1303 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1207 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF); 1304 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1208 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; 1305 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1209 u32 dspcntr, alignment; 1306 u32 dspcntr;
1210 int ret; 1307 int ret;
1211 1308
1212 /* no fb bound */ 1309 /* no fb bound */
1213 if (!crtc->fb) { 1310 if (!crtc->fb) {
1214 DRM_DEBUG("No FB bound\n"); 1311 DRM_DEBUG_KMS("No FB bound\n");
1215 return 0; 1312 return 0;
1216 } 1313 }
1217 1314
@@ -1226,52 +1323,22 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1226 1323
1227 intel_fb = to_intel_framebuffer(crtc->fb); 1324 intel_fb = to_intel_framebuffer(crtc->fb);
1228 obj = intel_fb->obj; 1325 obj = intel_fb->obj;
1229 obj_priv = obj->driver_private; 1326 obj_priv = to_intel_bo(obj);
1230
1231 switch (obj_priv->tiling_mode) {
1232 case I915_TILING_NONE:
1233 alignment = 64 * 1024;
1234 break;
1235 case I915_TILING_X:
1236 /* pin() will align the object as required by fence */
1237 alignment = 0;
1238 break;
1239 case I915_TILING_Y:
1240 /* FIXME: Is this true? */
1241 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1242 return -EINVAL;
1243 default:
1244 BUG();
1245 }
1246 1327
1247 mutex_lock(&dev->struct_mutex); 1328 mutex_lock(&dev->struct_mutex);
1248 ret = i915_gem_object_pin(obj, alignment); 1329 ret = intel_pin_and_fence_fb_obj(dev, obj);
1249 if (ret != 0) { 1330 if (ret != 0) {
1250 mutex_unlock(&dev->struct_mutex); 1331 mutex_unlock(&dev->struct_mutex);
1251 return ret; 1332 return ret;
1252 } 1333 }
1253 1334
1254 ret = i915_gem_object_set_to_gtt_domain(obj, 1); 1335 ret = i915_gem_object_set_to_display_plane(obj);
1255 if (ret != 0) { 1336 if (ret != 0) {
1256 i915_gem_object_unpin(obj); 1337 i915_gem_object_unpin(obj);
1257 mutex_unlock(&dev->struct_mutex); 1338 mutex_unlock(&dev->struct_mutex);
1258 return ret; 1339 return ret;
1259 } 1340 }
1260 1341
1261 /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1262 * whereas 965+ only requires a fence if using framebuffer compression.
1263 * For simplicity, we always install a fence as the cost is not that onerous.
1264 */
1265 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266 obj_priv->tiling_mode != I915_TILING_NONE) {
1267 ret = i915_gem_object_get_fence_reg(obj);
1268 if (ret != 0) {
1269 i915_gem_object_unpin(obj);
1270 mutex_unlock(&dev->struct_mutex);
1271 return ret;
1272 }
1273 }
1274
1275 dspcntr = I915_READ(dspcntr_reg); 1342 dspcntr = I915_READ(dspcntr_reg);
1276 /* Mask out pixel format bits in case we change it */ 1343 /* Mask out pixel format bits in case we change it */
1277 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1344 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
@@ -1287,7 +1354,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1287 break; 1354 break;
1288 case 24: 1355 case 24:
1289 case 32: 1356 case 32:
1290 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 1357 if (crtc->fb->depth == 30)
1358 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1359 else
1360 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291 break; 1361 break;
1292 default: 1362 default:
1293 DRM_ERROR("Unknown color depth\n"); 1363 DRM_ERROR("Unknown color depth\n");
@@ -1302,7 +1372,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1302 dspcntr &= ~DISPPLANE_TILED; 1372 dspcntr &= ~DISPPLANE_TILED;
1303 } 1373 }
1304 1374
1305 if (IS_IGDNG(dev)) 1375 if (HAS_PCH_SPLIT(dev))
1306 /* must disable */ 1376 /* must disable */
1307 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1377 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308 1378
@@ -1311,7 +1381,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1311 Start = obj_priv->gtt_offset; 1381 Start = obj_priv->gtt_offset;
1312 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); 1382 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313 1383
1314 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1384 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1315 I915_WRITE(dspstride, crtc->fb->pitch); 1385 I915_WRITE(dspstride, crtc->fb->pitch);
1316 if (IS_I965G(dev)) { 1386 if (IS_I965G(dev)) {
1317 I915_WRITE(dspbase, Offset); 1387 I915_WRITE(dspbase, Offset);
@@ -1331,7 +1401,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1331 1401
1332 if (old_fb) { 1402 if (old_fb) {
1333 intel_fb = to_intel_framebuffer(old_fb); 1403 intel_fb = to_intel_framebuffer(old_fb);
1334 obj_priv = intel_fb->obj->driver_private; 1404 obj_priv = to_intel_bo(intel_fb->obj);
1335 i915_gem_object_unpin(intel_fb->obj); 1405 i915_gem_object_unpin(intel_fb->obj);
1336 } 1406 }
1337 intel_increase_pllclock(crtc, true); 1407 intel_increase_pllclock(crtc, true);
@@ -1363,7 +1433,7 @@ static void i915_disable_vga (struct drm_device *dev)
1363 u8 sr1; 1433 u8 sr1;
1364 u32 vga_reg; 1434 u32 vga_reg;
1365 1435
1366 if (IS_IGDNG(dev)) 1436 if (HAS_PCH_SPLIT(dev))
1367 vga_reg = CPU_VGACNTRL; 1437 vga_reg = CPU_VGACNTRL;
1368 else 1438 else
1369 vga_reg = VGACNTRL; 1439 vga_reg = VGACNTRL;
@@ -1379,19 +1449,19 @@ static void i915_disable_vga (struct drm_device *dev)
1379 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 1449 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380} 1450}
1381 1451
1382static void igdng_disable_pll_edp (struct drm_crtc *crtc) 1452static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1383{ 1453{
1384 struct drm_device *dev = crtc->dev; 1454 struct drm_device *dev = crtc->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private; 1455 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 dpa_ctl; 1456 u32 dpa_ctl;
1387 1457
1388 DRM_DEBUG("\n"); 1458 DRM_DEBUG_KMS("\n");
1389 dpa_ctl = I915_READ(DP_A); 1459 dpa_ctl = I915_READ(DP_A);
1390 dpa_ctl &= ~DP_PLL_ENABLE; 1460 dpa_ctl &= ~DP_PLL_ENABLE;
1391 I915_WRITE(DP_A, dpa_ctl); 1461 I915_WRITE(DP_A, dpa_ctl);
1392} 1462}
1393 1463
1394static void igdng_enable_pll_edp (struct drm_crtc *crtc) 1464static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1395{ 1465{
1396 struct drm_device *dev = crtc->dev; 1466 struct drm_device *dev = crtc->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private; 1467 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1404,13 +1474,13 @@ static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1404} 1474}
1405 1475
1406 1476
1407static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock) 1477static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1408{ 1478{
1409 struct drm_device *dev = crtc->dev; 1479 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private; 1480 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl; 1481 u32 dpa_ctl;
1412 1482
1413 DRM_DEBUG("eDP PLL enable for clock %d\n", clock); 1483 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1414 dpa_ctl = I915_READ(DP_A); 1484 dpa_ctl = I915_READ(DP_A);
1415 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1485 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416 1486
@@ -1440,7 +1510,7 @@ static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1440 udelay(500); 1510 udelay(500);
1441} 1511}
1442 1512
1443static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) 1513static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1444{ 1514{
1445 struct drm_device *dev = crtc->dev; 1515 struct drm_device *dev = crtc->dev;
1446 struct drm_i915_private *dev_priv = dev->dev_private; 1516 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1473,6 +1543,10 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1473 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1543 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1474 u32 temp; 1544 u32 temp;
1475 int tries = 5, j, n; 1545 int tries = 5, j, n;
1546 u32 pipe_bpc;
1547
1548 temp = I915_READ(pipeconf_reg);
1549 pipe_bpc = temp & PIPE_BPC_MASK;
1476 1550
1477 /* XXX: When our outputs are all unaware of DPMS modes other than off 1551 /* XXX: When our outputs are all unaware of DPMS modes other than off
1478 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 1552 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1481,10 +1555,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1481 case DRM_MODE_DPMS_ON: 1555 case DRM_MODE_DPMS_ON:
1482 case DRM_MODE_DPMS_STANDBY: 1556 case DRM_MODE_DPMS_STANDBY:
1483 case DRM_MODE_DPMS_SUSPEND: 1557 case DRM_MODE_DPMS_SUSPEND:
1484 DRM_DEBUG("crtc %d dpms on\n", pipe); 1558 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1559
1560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1561 temp = I915_READ(PCH_LVDS);
1562 if ((temp & LVDS_PORT_EN) == 0) {
1563 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1564 POSTING_READ(PCH_LVDS);
1565 }
1566 }
1567
1485 if (HAS_eDP) { 1568 if (HAS_eDP) {
1486 /* enable eDP PLL */ 1569 /* enable eDP PLL */
1487 igdng_enable_pll_edp(crtc); 1570 ironlake_enable_pll_edp(crtc);
1488 } else { 1571 } else {
1489 /* enable PCH DPLL */ 1572 /* enable PCH DPLL */
1490 temp = I915_READ(pch_dpll_reg); 1573 temp = I915_READ(pch_dpll_reg);
@@ -1495,13 +1578,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1495 1578
1496 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1579 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1497 temp = I915_READ(fdi_rx_reg); 1580 temp = I915_READ(fdi_rx_reg);
1581 /*
1582 * make the BPC in FDI Rx be consistent with that in
1583 * pipeconf reg.
1584 */
1585 temp &= ~(0x7 << 16);
1586 temp |= (pipe_bpc << 11);
1498 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1587 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1499 FDI_SEL_PCDCLK | 1588 FDI_SEL_PCDCLK |
1500 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ 1589 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1501 I915_READ(fdi_rx_reg); 1590 I915_READ(fdi_rx_reg);
1502 udelay(200); 1591 udelay(200);
1503 1592
1504 /* Enable CPU FDI TX PLL, always on for IGDNG */ 1593 /* Enable CPU FDI TX PLL, always on for Ironlake */
1505 temp = I915_READ(fdi_tx_reg); 1594 temp = I915_READ(fdi_tx_reg);
1506 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1595 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1507 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); 1596 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
@@ -1568,12 +1657,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1568 udelay(150); 1657 udelay(150);
1569 1658
1570 temp = I915_READ(fdi_rx_iir_reg); 1659 temp = I915_READ(fdi_rx_iir_reg);
1571 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1572 1661
1573 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1662 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1574 for (j = 0; j < tries; j++) { 1663 for (j = 0; j < tries; j++) {
1575 temp = I915_READ(fdi_rx_iir_reg); 1664 temp = I915_READ(fdi_rx_iir_reg);
1576 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1666 temp);
1577 if (temp & FDI_RX_BIT_LOCK) 1667 if (temp & FDI_RX_BIT_LOCK)
1578 break; 1668 break;
1579 udelay(200); 1669 udelay(200);
@@ -1582,11 +1672,11 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1582 I915_WRITE(fdi_rx_iir_reg, 1672 I915_WRITE(fdi_rx_iir_reg,
1583 temp | FDI_RX_BIT_LOCK); 1673 temp | FDI_RX_BIT_LOCK);
1584 else 1674 else
1585 DRM_DEBUG("train 1 fail\n"); 1675 DRM_DEBUG_KMS("train 1 fail\n");
1586 } else { 1676 } else {
1587 I915_WRITE(fdi_rx_iir_reg, 1677 I915_WRITE(fdi_rx_iir_reg,
1588 temp | FDI_RX_BIT_LOCK); 1678 temp | FDI_RX_BIT_LOCK);
1589 DRM_DEBUG("train 1 ok 2!\n"); 1679 DRM_DEBUG_KMS("train 1 ok 2!\n");
1590 } 1680 }
1591 temp = I915_READ(fdi_tx_reg); 1681 temp = I915_READ(fdi_tx_reg);
1592 temp &= ~FDI_LINK_TRAIN_NONE; 1682 temp &= ~FDI_LINK_TRAIN_NONE;
@@ -1601,12 +1691,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1601 udelay(150); 1691 udelay(150);
1602 1692
1603 temp = I915_READ(fdi_rx_iir_reg); 1693 temp = I915_READ(fdi_rx_iir_reg);
1604 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1605 1695
1606 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1696 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1607 for (j = 0; j < tries; j++) { 1697 for (j = 0; j < tries; j++) {
1608 temp = I915_READ(fdi_rx_iir_reg); 1698 temp = I915_READ(fdi_rx_iir_reg);
1609 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1700 temp);
1610 if (temp & FDI_RX_SYMBOL_LOCK) 1701 if (temp & FDI_RX_SYMBOL_LOCK)
1611 break; 1702 break;
1612 udelay(200); 1703 udelay(200);
@@ -1614,15 +1705,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1614 if (j != tries) { 1705 if (j != tries) {
1615 I915_WRITE(fdi_rx_iir_reg, 1706 I915_WRITE(fdi_rx_iir_reg,
1616 temp | FDI_RX_SYMBOL_LOCK); 1707 temp | FDI_RX_SYMBOL_LOCK);
1617 DRM_DEBUG("train 2 ok 1!\n"); 1708 DRM_DEBUG_KMS("train 2 ok 1!\n");
1618 } else 1709 } else
1619 DRM_DEBUG("train 2 fail\n"); 1710 DRM_DEBUG_KMS("train 2 fail\n");
1620 } else { 1711 } else {
1621 I915_WRITE(fdi_rx_iir_reg, 1712 I915_WRITE(fdi_rx_iir_reg,
1622 temp | FDI_RX_SYMBOL_LOCK); 1713 temp | FDI_RX_SYMBOL_LOCK);
1623 DRM_DEBUG("train 2 ok 2!\n"); 1714 DRM_DEBUG_KMS("train 2 ok 2!\n");
1624 } 1715 }
1625 DRM_DEBUG("train done\n"); 1716 DRM_DEBUG_KMS("train done\n");
1626 1717
1627 /* set transcoder timing */ 1718 /* set transcoder timing */
1628 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1719 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1635,6 +1726,12 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1635 1726
1636 /* enable PCH transcoder */ 1727 /* enable PCH transcoder */
1637 temp = I915_READ(transconf_reg); 1728 temp = I915_READ(transconf_reg);
1729 /*
1730 * make the BPC in transcoder be consistent with
1731 * that in pipeconf reg.
1732 */
1733 temp &= ~PIPE_BPC_MASK;
1734 temp |= pipe_bpc;
1638 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 1735 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1639 I915_READ(transconf_reg); 1736 I915_READ(transconf_reg);
1640 1737
@@ -1664,10 +1761,9 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1664 1761
1665 break; 1762 break;
1666 case DRM_MODE_DPMS_OFF: 1763 case DRM_MODE_DPMS_OFF:
1667 DRM_DEBUG("crtc %d dpms off\n", pipe); 1764 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1668
1669 i915_disable_vga(dev);
1670 1765
1766 drm_vblank_off(dev, pipe);
1671 /* Disable display plane */ 1767 /* Disable display plane */
1672 temp = I915_READ(dspcntr_reg); 1768 temp = I915_READ(dspcntr_reg);
1673 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 1769 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -1677,6 +1773,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1677 I915_READ(dspbase_reg); 1773 I915_READ(dspbase_reg);
1678 } 1774 }
1679 1775
1776 i915_disable_vga(dev);
1777
1680 /* disable cpu pipe, disable after all planes disabled */ 1778 /* disable cpu pipe, disable after all planes disabled */
1681 temp = I915_READ(pipeconf_reg); 1779 temp = I915_READ(pipeconf_reg);
1682 if ((temp & PIPEACONF_ENABLE) != 0) { 1780 if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -1690,16 +1788,23 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1690 udelay(500); 1788 udelay(500);
1691 continue; 1789 continue;
1692 } else { 1790 } else {
1693 DRM_DEBUG("pipe %d off delay\n", pipe); 1791 DRM_DEBUG_KMS("pipe %d off delay\n",
1792 pipe);
1694 break; 1793 break;
1695 } 1794 }
1696 } 1795 }
1697 } else 1796 } else
1698 DRM_DEBUG("crtc %d is disabled\n", pipe); 1797 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1699 1798
1700 if (HAS_eDP) { 1799 udelay(100);
1701 igdng_disable_pll_edp(crtc); 1800
1801 /* Disable PF */
1802 temp = I915_READ(pf_ctl_reg);
1803 if ((temp & PF_ENABLE) != 0) {
1804 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1805 I915_READ(pf_ctl_reg);
1702 } 1806 }
1807 I915_WRITE(pf_win_size, 0);
1703 1808
1704 /* disable CPU FDI tx and PCH FDI rx */ 1809 /* disable CPU FDI tx and PCH FDI rx */
1705 temp = I915_READ(fdi_tx_reg); 1810 temp = I915_READ(fdi_tx_reg);
@@ -1707,6 +1812,9 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1707 I915_READ(fdi_tx_reg); 1812 I915_READ(fdi_tx_reg);
1708 1813
1709 temp = I915_READ(fdi_rx_reg); 1814 temp = I915_READ(fdi_rx_reg);
1815 /* BPC in FDI rx is consistent with that in pipeconf */
1816 temp &= ~(0x07 << 16);
1817 temp |= (pipe_bpc << 11);
1710 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); 1818 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1711 I915_READ(fdi_rx_reg); 1819 I915_READ(fdi_rx_reg);
1712 1820
@@ -1725,6 +1833,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1725 1833
1726 udelay(100); 1834 udelay(100);
1727 1835
1836 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1837 temp = I915_READ(PCH_LVDS);
1838 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1839 I915_READ(PCH_LVDS);
1840 udelay(100);
1841 }
1842
1728 /* disable PCH transcoder */ 1843 /* disable PCH transcoder */
1729 temp = I915_READ(transconf_reg); 1844 temp = I915_READ(transconf_reg);
1730 if ((temp & TRANS_ENABLE) != 0) { 1845 if ((temp & TRANS_ENABLE) != 0) {
@@ -1738,11 +1853,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1738 udelay(500); 1853 udelay(500);
1739 continue; 1854 continue;
1740 } else { 1855 } else {
1741 DRM_DEBUG("transcoder %d off delay\n", pipe); 1856 DRM_DEBUG_KMS("transcoder %d off "
1857 "delay\n", pipe);
1742 break; 1858 break;
1743 } 1859 }
1744 } 1860 }
1745 } 1861 }
1862 temp = I915_READ(transconf_reg);
1863 /* BPC in transcoder is consistent with that in pipeconf */
1864 temp &= ~PIPE_BPC_MASK;
1865 temp |= pipe_bpc;
1866 I915_WRITE(transconf_reg, temp);
1867 I915_READ(transconf_reg);
1868 udelay(100);
1746 1869
1747 /* disable PCH DPLL */ 1870 /* disable PCH DPLL */
1748 temp = I915_READ(pch_dpll_reg); 1871 temp = I915_READ(pch_dpll_reg);
@@ -1751,14 +1874,20 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1751 I915_READ(pch_dpll_reg); 1874 I915_READ(pch_dpll_reg);
1752 } 1875 }
1753 1876
1754 temp = I915_READ(fdi_rx_reg); 1877 if (HAS_eDP) {
1755 if ((temp & FDI_RX_PLL_ENABLE) != 0) { 1878 ironlake_disable_pll_edp(crtc);
1756 temp &= ~FDI_SEL_PCDCLK;
1757 temp &= ~FDI_RX_PLL_ENABLE;
1758 I915_WRITE(fdi_rx_reg, temp);
1759 I915_READ(fdi_rx_reg);
1760 } 1879 }
1761 1880
1881 temp = I915_READ(fdi_rx_reg);
1882 temp &= ~FDI_SEL_PCDCLK;
1883 I915_WRITE(fdi_rx_reg, temp);
1884 I915_READ(fdi_rx_reg);
1885
1886 temp = I915_READ(fdi_rx_reg);
1887 temp &= ~FDI_RX_PLL_ENABLE;
1888 I915_WRITE(fdi_rx_reg, temp);
1889 I915_READ(fdi_rx_reg);
1890
1762 /* Disable CPU FDI TX PLL */ 1891 /* Disable CPU FDI TX PLL */
1763 temp = I915_READ(fdi_tx_reg); 1892 temp = I915_READ(fdi_tx_reg);
1764 if ((temp & FDI_TX_PLL_ENABLE) != 0) { 1893 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
@@ -1767,20 +1896,43 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1767 udelay(100); 1896 udelay(100);
1768 } 1897 }
1769 1898
1770 /* Disable PF */
1771 temp = I915_READ(pf_ctl_reg);
1772 if ((temp & PF_ENABLE) != 0) {
1773 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1774 I915_READ(pf_ctl_reg);
1775 }
1776 I915_WRITE(pf_win_size, 0);
1777
1778 /* Wait for the clocks to turn off. */ 1899 /* Wait for the clocks to turn off. */
1779 udelay(150); 1900 udelay(100);
1780 break; 1901 break;
1781 } 1902 }
1782} 1903}
1783 1904
1905static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1906{
1907 struct intel_overlay *overlay;
1908 int ret;
1909
1910 if (!enable && intel_crtc->overlay) {
1911 overlay = intel_crtc->overlay;
1912 mutex_lock(&overlay->dev->struct_mutex);
1913 for (;;) {
1914 ret = intel_overlay_switch_off(overlay);
1915 if (ret == 0)
1916 break;
1917
1918 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1919 if (ret != 0) {
1920 /* overlay doesn't react anymore. Usually
1921 * results in a black screen and an unkillable
1922 * X server. */
1923 BUG();
1924 overlay->hw_wedged = HW_WEDGED;
1925 break;
1926 }
1927 }
1928 mutex_unlock(&overlay->dev->struct_mutex);
1929 }
1930 /* Let userspace switch the overlay on again. In most cases userspace
1931 * has to recompute where to put it anyway. */
1932
1933 return;
1934}
1935
1784static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 1936static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1785{ 1937{
1786 struct drm_device *dev = crtc->dev; 1938 struct drm_device *dev = crtc->dev;
@@ -1839,12 +1991,14 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1839 intel_update_fbc(crtc, &crtc->mode); 1991 intel_update_fbc(crtc, &crtc->mode);
1840 1992
1841 /* Give the overlay scaler a chance to enable if it's on this pipe */ 1993 /* Give the overlay scaler a chance to enable if it's on this pipe */
1842 //intel_crtc_dpms_video(crtc, true); TODO 1994 intel_crtc_dpms_overlay(intel_crtc, true);
1843 break; 1995 break;
1844 case DRM_MODE_DPMS_OFF: 1996 case DRM_MODE_DPMS_OFF:
1845 intel_update_watermarks(dev); 1997 intel_update_watermarks(dev);
1998
1846 /* Give the overlay scaler a chance to disable if it's on this pipe */ 1999 /* Give the overlay scaler a chance to disable if it's on this pipe */
1847 //intel_crtc_dpms_video(crtc, FALSE); TODO 2000 intel_crtc_dpms_overlay(intel_crtc, false);
2001 drm_vblank_off(dev, pipe);
1848 2002
1849 if (dev_priv->cfb_plane == plane && 2003 if (dev_priv->cfb_plane == plane &&
1850 dev_priv->display.disable_fbc) 2004 dev_priv->display.disable_fbc)
@@ -1963,7 +2117,7 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1963 struct drm_display_mode *adjusted_mode) 2117 struct drm_display_mode *adjusted_mode)
1964{ 2118{
1965 struct drm_device *dev = crtc->dev; 2119 struct drm_device *dev = crtc->dev;
1966 if (IS_IGDNG(dev)) { 2120 if (HAS_PCH_SPLIT(dev)) {
1967 /* FDI link clock is fixed at 2.7G */ 2121 /* FDI link clock is fixed at 2.7G */
1968 if (mode->clock * 3 > 27000 * 4) 2122 if (mode->clock * 3 > 27000 * 4)
1969 return MODE_CLOCK_HIGH; 2123 return MODE_CLOCK_HIGH;
@@ -2039,7 +2193,7 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
2039 * Return the pipe currently connected to the panel fitter, 2193 * Return the pipe currently connected to the panel fitter,
2040 * or -1 if the panel fitter is not present or not in use 2194 * or -1 if the panel fitter is not present or not in use
2041 */ 2195 */
2042static int intel_panel_fitter_pipe (struct drm_device *dev) 2196int intel_panel_fitter_pipe (struct drm_device *dev)
2043{ 2197{
2044 struct drm_i915_private *dev_priv = dev->dev_private; 2198 struct drm_i915_private *dev_priv = dev->dev_private;
2045 u32 pfit_control; 2199 u32 pfit_control;
@@ -2083,9 +2237,8 @@ fdi_reduce_ratio(u32 *num, u32 *den)
2083#define LINK_N 0x80000 2237#define LINK_N 0x80000
2084 2238
2085static void 2239static void
2086igdng_compute_m_n(int bits_per_pixel, int nlanes, 2240ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2087 int pixel_clock, int link_clock, 2241 int link_clock, struct fdi_m_n *m_n)
2088 struct fdi_m_n *m_n)
2089{ 2242{
2090 u64 temp; 2243 u64 temp;
2091 2244
@@ -2113,34 +2266,34 @@ struct intel_watermark_params {
2113 unsigned long cacheline_size; 2266 unsigned long cacheline_size;
2114}; 2267};
2115 2268
2116/* IGD has different values for various configs */ 2269/* Pineview has different values for various configs */
2117static struct intel_watermark_params igd_display_wm = { 2270static struct intel_watermark_params pineview_display_wm = {
2118 IGD_DISPLAY_FIFO, 2271 PINEVIEW_DISPLAY_FIFO,
2119 IGD_MAX_WM, 2272 PINEVIEW_MAX_WM,
2120 IGD_DFT_WM, 2273 PINEVIEW_DFT_WM,
2121 IGD_GUARD_WM, 2274 PINEVIEW_GUARD_WM,
2122 IGD_FIFO_LINE_SIZE 2275 PINEVIEW_FIFO_LINE_SIZE
2123}; 2276};
2124static struct intel_watermark_params igd_display_hplloff_wm = { 2277static struct intel_watermark_params pineview_display_hplloff_wm = {
2125 IGD_DISPLAY_FIFO, 2278 PINEVIEW_DISPLAY_FIFO,
2126 IGD_MAX_WM, 2279 PINEVIEW_MAX_WM,
2127 IGD_DFT_HPLLOFF_WM, 2280 PINEVIEW_DFT_HPLLOFF_WM,
2128 IGD_GUARD_WM, 2281 PINEVIEW_GUARD_WM,
2129 IGD_FIFO_LINE_SIZE 2282 PINEVIEW_FIFO_LINE_SIZE
2130}; 2283};
2131static struct intel_watermark_params igd_cursor_wm = { 2284static struct intel_watermark_params pineview_cursor_wm = {
2132 IGD_CURSOR_FIFO, 2285 PINEVIEW_CURSOR_FIFO,
2133 IGD_CURSOR_MAX_WM, 2286 PINEVIEW_CURSOR_MAX_WM,
2134 IGD_CURSOR_DFT_WM, 2287 PINEVIEW_CURSOR_DFT_WM,
2135 IGD_CURSOR_GUARD_WM, 2288 PINEVIEW_CURSOR_GUARD_WM,
2136 IGD_FIFO_LINE_SIZE, 2289 PINEVIEW_FIFO_LINE_SIZE,
2137}; 2290};
2138static struct intel_watermark_params igd_cursor_hplloff_wm = { 2291static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2139 IGD_CURSOR_FIFO, 2292 PINEVIEW_CURSOR_FIFO,
2140 IGD_CURSOR_MAX_WM, 2293 PINEVIEW_CURSOR_MAX_WM,
2141 IGD_CURSOR_DFT_WM, 2294 PINEVIEW_CURSOR_DFT_WM,
2142 IGD_CURSOR_GUARD_WM, 2295 PINEVIEW_CURSOR_GUARD_WM,
2143 IGD_FIFO_LINE_SIZE 2296 PINEVIEW_FIFO_LINE_SIZE
2144}; 2297};
2145static struct intel_watermark_params g4x_wm_info = { 2298static struct intel_watermark_params g4x_wm_info = {
2146 G4X_FIFO_SIZE, 2299 G4X_FIFO_SIZE,
@@ -2213,11 +2366,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2213 1000; 2366 1000;
2214 entries_required /= wm->cacheline_size; 2367 entries_required /= wm->cacheline_size;
2215 2368
2216 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required); 2369 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2217 2370
2218 wm_size = wm->fifo_size - (entries_required + wm->guard_size); 2371 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2219 2372
2220 DRM_DEBUG("FIFO watermark level: %d\n", wm_size); 2373 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2221 2374
2222 /* Don't promote wm_size to unsigned... */ 2375 /* Don't promote wm_size to unsigned... */
2223 if (wm_size > (long)wm->max_wm) 2376 if (wm_size > (long)wm->max_wm)
@@ -2279,50 +2432,50 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2279 return latency; 2432 return latency;
2280 } 2433 }
2281 2434
2282 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); 2435 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2283 2436
2284 return NULL; 2437 return NULL;
2285} 2438}
2286 2439
2287static void igd_disable_cxsr(struct drm_device *dev) 2440static void pineview_disable_cxsr(struct drm_device *dev)
2288{ 2441{
2289 struct drm_i915_private *dev_priv = dev->dev_private; 2442 struct drm_i915_private *dev_priv = dev->dev_private;
2290 u32 reg; 2443 u32 reg;
2291 2444
2292 /* deactivate cxsr */ 2445 /* deactivate cxsr */
2293 reg = I915_READ(DSPFW3); 2446 reg = I915_READ(DSPFW3);
2294 reg &= ~(IGD_SELF_REFRESH_EN); 2447 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2295 I915_WRITE(DSPFW3, reg); 2448 I915_WRITE(DSPFW3, reg);
2296 DRM_INFO("Big FIFO is disabled\n"); 2449 DRM_INFO("Big FIFO is disabled\n");
2297} 2450}
2298 2451
2299static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, 2452static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2300 int pixel_size) 2453 int pixel_size)
2301{ 2454{
2302 struct drm_i915_private *dev_priv = dev->dev_private; 2455 struct drm_i915_private *dev_priv = dev->dev_private;
2303 u32 reg; 2456 u32 reg;
2304 unsigned long wm; 2457 unsigned long wm;
2305 struct cxsr_latency *latency; 2458 struct cxsr_latency *latency;
2306 2459
2307 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, 2460 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2308 dev_priv->mem_freq); 2461 dev_priv->mem_freq);
2309 if (!latency) { 2462 if (!latency) {
2310 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); 2463 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2311 igd_disable_cxsr(dev); 2464 pineview_disable_cxsr(dev);
2312 return; 2465 return;
2313 } 2466 }
2314 2467
2315 /* Display SR */ 2468 /* Display SR */
2316 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size, 2469 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2317 latency->display_sr); 2470 latency->display_sr);
2318 reg = I915_READ(DSPFW1); 2471 reg = I915_READ(DSPFW1);
2319 reg &= 0x7fffff; 2472 reg &= 0x7fffff;
2320 reg |= wm << 23; 2473 reg |= wm << 23;
2321 I915_WRITE(DSPFW1, reg); 2474 I915_WRITE(DSPFW1, reg);
2322 DRM_DEBUG("DSPFW1 register is %x\n", reg); 2475 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2323 2476
2324 /* cursor SR */ 2477 /* cursor SR */
2325 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, 2478 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2326 latency->cursor_sr); 2479 latency->cursor_sr);
2327 reg = I915_READ(DSPFW3); 2480 reg = I915_READ(DSPFW3);
2328 reg &= ~(0x3f << 24); 2481 reg &= ~(0x3f << 24);
@@ -2330,7 +2483,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2330 I915_WRITE(DSPFW3, reg); 2483 I915_WRITE(DSPFW3, reg);
2331 2484
2332 /* Display HPLL off SR */ 2485 /* Display HPLL off SR */
2333 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm, 2486 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2334 latency->display_hpll_disable, I915_FIFO_LINE_SIZE); 2487 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2335 reg = I915_READ(DSPFW3); 2488 reg = I915_READ(DSPFW3);
2336 reg &= 0xfffffe00; 2489 reg &= 0xfffffe00;
@@ -2338,17 +2491,17 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2338 I915_WRITE(DSPFW3, reg); 2491 I915_WRITE(DSPFW3, reg);
2339 2492
2340 /* cursor HPLL off SR */ 2493 /* cursor HPLL off SR */
2341 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size, 2494 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2342 latency->cursor_hpll_disable); 2495 latency->cursor_hpll_disable);
2343 reg = I915_READ(DSPFW3); 2496 reg = I915_READ(DSPFW3);
2344 reg &= ~(0x3f << 16); 2497 reg &= ~(0x3f << 16);
2345 reg |= (wm & 0x3f) << 16; 2498 reg |= (wm & 0x3f) << 16;
2346 I915_WRITE(DSPFW3, reg); 2499 I915_WRITE(DSPFW3, reg);
2347 DRM_DEBUG("DSPFW3 register is %x\n", reg); 2500 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2348 2501
2349 /* activate cxsr */ 2502 /* activate cxsr */
2350 reg = I915_READ(DSPFW3); 2503 reg = I915_READ(DSPFW3);
2351 reg |= IGD_SELF_REFRESH_EN; 2504 reg |= PINEVIEW_SELF_REFRESH_EN;
2352 I915_WRITE(DSPFW3, reg); 2505 I915_WRITE(DSPFW3, reg);
2353 2506
2354 DRM_INFO("Big FIFO is enabled\n"); 2507 DRM_INFO("Big FIFO is enabled\n");
@@ -2370,7 +2523,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2370 * A value of 5us seems to be a good balance; safe for very low end 2523 * A value of 5us seems to be a good balance; safe for very low end
2371 * platforms but not overly aggressive on lower latency configs. 2524 * platforms but not overly aggressive on lower latency configs.
2372 */ 2525 */
2373const static int latency_ns = 5000; 2526static const int latency_ns = 5000;
2374 2527
2375static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 2528static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2376{ 2529{
@@ -2384,8 +2537,8 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2384 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - 2537 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2385 (dsparb & 0x7f); 2538 (dsparb & 0x7f);
2386 2539
2387 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2540 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2388 size); 2541 plane ? "B" : "A", size);
2389 2542
2390 return size; 2543 return size;
2391} 2544}
@@ -2403,8 +2556,8 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2403 (dsparb & 0x1ff); 2556 (dsparb & 0x1ff);
2404 size >>= 1; /* Convert to cachelines */ 2557 size >>= 1; /* Convert to cachelines */
2405 2558
2406 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2559 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2407 size); 2560 plane ? "B" : "A", size);
2408 2561
2409 return size; 2562 return size;
2410} 2563}
@@ -2418,7 +2571,8 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
2418 size = dsparb & 0x7f; 2571 size = dsparb & 0x7f;
2419 size >>= 2; /* Convert to cachelines */ 2572 size >>= 2; /* Convert to cachelines */
2420 2573
2421 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2574 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2575 plane ? "B" : "A",
2422 size); 2576 size);
2423 2577
2424 return size; 2578 return size;
@@ -2433,8 +2587,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
2433 size = dsparb & 0x7f; 2587 size = dsparb & 0x7f;
2434 size >>= 1; /* Convert to cachelines */ 2588 size >>= 1; /* Convert to cachelines */
2435 2589
2436 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2590 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2437 size); 2591 plane ? "B" : "A", size);
2438 2592
2439 return size; 2593 return size;
2440} 2594}
@@ -2480,7 +2634,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2480 /* Calc sr entries for one plane configs */ 2634 /* Calc sr entries for one plane configs */
2481 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2635 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2482 /* self-refresh has much higher latency */ 2636 /* self-refresh has much higher latency */
2483 const static int sr_latency_ns = 12000; 2637 static const int sr_latency_ns = 12000;
2484 2638
2485 sr_clock = planea_clock ? planea_clock : planeb_clock; 2639 sr_clock = planea_clock ? planea_clock : planeb_clock;
2486 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2640 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2491,6 +2645,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2491 sr_entries = roundup(sr_entries / cacheline_size, 1); 2645 sr_entries = roundup(sr_entries / cacheline_size, 1);
2492 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 2646 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2493 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2647 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2648 } else {
2649 /* Turn off self refresh if both pipes are enabled */
2650 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2651 & ~FW_BLC_SELF_EN);
2494 } 2652 }
2495 2653
2496 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", 2654 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
@@ -2509,15 +2667,43 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2509 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 2667 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2510} 2668}
2511 2669
2512static void i965_update_wm(struct drm_device *dev, int unused, int unused2, 2670static void i965_update_wm(struct drm_device *dev, int planea_clock,
2513 int unused3, int unused4) 2671 int planeb_clock, int sr_hdisplay, int pixel_size)
2514{ 2672{
2515 struct drm_i915_private *dev_priv = dev->dev_private; 2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 unsigned long line_time_us;
2675 int sr_clock, sr_entries, srwm = 1;
2676
2677 /* Calc sr entries for one plane configs */
2678 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2679 /* self-refresh has much higher latency */
2680 static const int sr_latency_ns = 12000;
2516 2681
2517 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n"); 2682 sr_clock = planea_clock ? planea_clock : planeb_clock;
2683 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2684
2685 /* Use ns/us then divide to preserve precision */
2686 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2687 pixel_size * sr_hdisplay) / 1000;
2688 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2689 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2690 srwm = I945_FIFO_SIZE - sr_entries;
2691 if (srwm < 0)
2692 srwm = 1;
2693 srwm &= 0x3f;
2694 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2695 } else {
2696 /* Turn off self refresh if both pipes are enabled */
2697 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2698 & ~FW_BLC_SELF_EN);
2699 }
2700
2701 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2702 srwm);
2518 2703
2519 /* 965 has limitations... */ 2704 /* 965 has limitations... */
2520 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0)); 2705 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2706 (8 << 0));
2521 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 2707 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2522} 2708}
2523 2709
@@ -2553,7 +2739,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2553 pixel_size, latency_ns); 2739 pixel_size, latency_ns);
2554 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, 2740 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2555 pixel_size, latency_ns); 2741 pixel_size, latency_ns);
2556 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 2742 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2557 2743
2558 /* 2744 /*
2559 * Overlay gets an aggressive default since video jitter is bad. 2745 * Overlay gets an aggressive default since video jitter is bad.
@@ -2564,7 +2750,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2564 if (HAS_FW_BLC(dev) && sr_hdisplay && 2750 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2565 (!planea_clock || !planeb_clock)) { 2751 (!planea_clock || !planeb_clock)) {
2566 /* self-refresh has much higher latency */ 2752 /* self-refresh has much higher latency */
2567 const static int sr_latency_ns = 6000; 2753 static const int sr_latency_ns = 6000;
2568 2754
2569 sr_clock = planea_clock ? planea_clock : planeb_clock; 2755 sr_clock = planea_clock ? planea_clock : planeb_clock;
2570 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2756 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2573,14 +2759,29 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2573 sr_entries = (((sr_latency_ns / line_time_us) + 1) * 2759 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2574 pixel_size * sr_hdisplay) / 1000; 2760 pixel_size * sr_hdisplay) / 1000;
2575 sr_entries = roundup(sr_entries / cacheline_size, 1); 2761 sr_entries = roundup(sr_entries / cacheline_size, 1);
2576 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 2762 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2577 srwm = total_size - sr_entries; 2763 srwm = total_size - sr_entries;
2578 if (srwm < 0) 2764 if (srwm < 0)
2579 srwm = 1; 2765 srwm = 1;
2580 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); 2766
2767 if (IS_I945G(dev) || IS_I945GM(dev))
2768 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2769 else if (IS_I915GM(dev)) {
2770 /* 915M has a smaller SRWM field */
2771 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2772 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2773 }
2774 } else {
2775 /* Turn off self refresh if both pipes are enabled */
2776 if (IS_I945G(dev) || IS_I945GM(dev)) {
2777 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2778 & ~FW_BLC_SELF_EN);
2779 } else if (IS_I915GM(dev)) {
2780 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2781 }
2581 } 2782 }
2582 2783
2583 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2784 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2584 planea_wm, planeb_wm, cwm, srwm); 2785 planea_wm, planeb_wm, cwm, srwm);
2585 2786
2586 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 2787 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
@@ -2607,7 +2808,7 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2607 pixel_size, latency_ns); 2808 pixel_size, latency_ns);
2608 fwater_lo |= (3<<8) | planea_wm; 2809 fwater_lo |= (3<<8) | planea_wm;
2609 2810
2610 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm); 2811 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2611 2812
2612 I915_WRITE(FW_BLC, fwater_lo); 2813 I915_WRITE(FW_BLC, fwater_lo);
2613} 2814}
@@ -2661,11 +2862,11 @@ static void intel_update_watermarks(struct drm_device *dev)
2661 if (crtc->enabled) { 2862 if (crtc->enabled) {
2662 enabled++; 2863 enabled++;
2663 if (intel_crtc->plane == 0) { 2864 if (intel_crtc->plane == 0) {
2664 DRM_DEBUG("plane A (pipe %d) clock: %d\n", 2865 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2665 intel_crtc->pipe, crtc->mode.clock); 2866 intel_crtc->pipe, crtc->mode.clock);
2666 planea_clock = crtc->mode.clock; 2867 planea_clock = crtc->mode.clock;
2667 } else { 2868 } else {
2668 DRM_DEBUG("plane B (pipe %d) clock: %d\n", 2869 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2669 intel_crtc->pipe, crtc->mode.clock); 2870 intel_crtc->pipe, crtc->mode.clock);
2670 planeb_clock = crtc->mode.clock; 2871 planeb_clock = crtc->mode.clock;
2671 } 2872 }
@@ -2682,10 +2883,10 @@ static void intel_update_watermarks(struct drm_device *dev)
2682 return; 2883 return;
2683 2884
2684 /* Single plane configs can enable self refresh */ 2885 /* Single plane configs can enable self refresh */
2685 if (enabled == 1 && IS_IGD(dev)) 2886 if (enabled == 1 && IS_PINEVIEW(dev))
2686 igd_enable_cxsr(dev, sr_clock, pixel_size); 2887 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2687 else if (IS_IGD(dev)) 2888 else if (IS_PINEVIEW(dev))
2688 igd_disable_cxsr(dev); 2889 pineview_disable_cxsr(dev);
2689 2890
2690 dev_priv->display.update_wm(dev, planea_clock, planeb_clock, 2891 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2691 sr_hdisplay, pixel_size); 2892 sr_hdisplay, pixel_size);
@@ -2716,7 +2917,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2716 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; 2917 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2717 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; 2918 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2718 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 2919 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2719 int refclk, num_outputs = 0; 2920 int refclk, num_connectors = 0;
2720 intel_clock_t clock, reduced_clock; 2921 intel_clock_t clock, reduced_clock;
2721 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 2922 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2722 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 2923 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
@@ -2742,19 +2943,19 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2742 drm_vblank_pre_modeset(dev, pipe); 2943 drm_vblank_pre_modeset(dev, pipe);
2743 2944
2744 list_for_each_entry(connector, &mode_config->connector_list, head) { 2945 list_for_each_entry(connector, &mode_config->connector_list, head) {
2745 struct intel_output *intel_output = to_intel_output(connector); 2946 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2746 2947
2747 if (!connector->encoder || connector->encoder->crtc != crtc) 2948 if (!connector->encoder || connector->encoder->crtc != crtc)
2748 continue; 2949 continue;
2749 2950
2750 switch (intel_output->type) { 2951 switch (intel_encoder->type) {
2751 case INTEL_OUTPUT_LVDS: 2952 case INTEL_OUTPUT_LVDS:
2752 is_lvds = true; 2953 is_lvds = true;
2753 break; 2954 break;
2754 case INTEL_OUTPUT_SDVO: 2955 case INTEL_OUTPUT_SDVO:
2755 case INTEL_OUTPUT_HDMI: 2956 case INTEL_OUTPUT_HDMI:
2756 is_sdvo = true; 2957 is_sdvo = true;
2757 if (intel_output->needs_tv_clock) 2958 if (intel_encoder->needs_tv_clock)
2758 is_tv = true; 2959 is_tv = true;
2759 break; 2960 break;
2760 case INTEL_OUTPUT_DVO: 2961 case INTEL_OUTPUT_DVO:
@@ -2774,15 +2975,16 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2774 break; 2975 break;
2775 } 2976 }
2776 2977
2777 num_outputs++; 2978 num_connectors++;
2778 } 2979 }
2779 2980
2780 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { 2981 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
2781 refclk = dev_priv->lvds_ssc_freq * 1000; 2982 refclk = dev_priv->lvds_ssc_freq * 1000;
2782 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); 2983 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2984 refclk / 1000);
2783 } else if (IS_I9XX(dev)) { 2985 } else if (IS_I9XX(dev)) {
2784 refclk = 96000; 2986 refclk = 96000;
2785 if (IS_IGDNG(dev)) 2987 if (HAS_PCH_SPLIT(dev))
2786 refclk = 120000; /* 120Mhz refclk */ 2988 refclk = 120000; /* 120Mhz refclk */
2787 } else { 2989 } else {
2788 refclk = 48000; 2990 refclk = 48000;
@@ -2802,14 +3004,23 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2802 return -EINVAL; 3004 return -EINVAL;
2803 } 3005 }
2804 3006
2805 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { 3007 if (is_lvds && dev_priv->lvds_downclock_avail) {
2806 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); 3008 has_reduced_clock = limit->find_pll(limit, crtc,
2807 has_reduced_clock = limit->find_reduced_pll(limit, crtc, 3009 dev_priv->lvds_downclock,
2808 (adjusted_mode->clock*3/4),
2809 refclk, 3010 refclk,
2810 &reduced_clock); 3011 &reduced_clock);
3012 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3013 /*
3014 * If the different P is found, it means that we can't
3015 * switch the display clock by using the FP0/FP1.
3016 * In such case we will disable the LVDS downclock
3017 * feature.
3018 */
3019 DRM_DEBUG_KMS("Different P is found for "
3020 "LVDS clock/downclock\n");
3021 has_reduced_clock = 0;
3022 }
2811 } 3023 }
2812
2813 /* SDVO TV has fixed PLL values depend on its clock range, 3024 /* SDVO TV has fixed PLL values depend on its clock range,
2814 this mirrors vbios setting. */ 3025 this mirrors vbios setting. */
2815 if (is_sdvo && is_tv) { 3026 if (is_sdvo && is_tv) {
@@ -2831,15 +3042,15 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2831 } 3042 }
2832 3043
2833 /* FDI link */ 3044 /* FDI link */
2834 if (IS_IGDNG(dev)) { 3045 if (HAS_PCH_SPLIT(dev)) {
2835 int lane, link_bw, bpp; 3046 int lane, link_bw, bpp;
2836 /* eDP doesn't require FDI link, so just set DP M/N 3047 /* eDP doesn't require FDI link, so just set DP M/N
2837 according to current link config */ 3048 according to current link config */
2838 if (is_edp) { 3049 if (is_edp) {
2839 struct drm_connector *edp; 3050 struct drm_connector *edp;
2840 target_clock = mode->clock; 3051 target_clock = mode->clock;
2841 edp = intel_pipe_get_output(crtc); 3052 edp = intel_pipe_get_connector(crtc);
2842 intel_edp_link_config(to_intel_output(edp), 3053 intel_edp_link_config(to_intel_encoder(edp),
2843 &lane, &link_bw); 3054 &lane, &link_bw);
2844 } else { 3055 } else {
2845 /* DP over FDI requires target mode clock 3056 /* DP over FDI requires target mode clock
@@ -2854,6 +3065,33 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2854 3065
2855 /* determine panel color depth */ 3066 /* determine panel color depth */
2856 temp = I915_READ(pipeconf_reg); 3067 temp = I915_READ(pipeconf_reg);
3068 temp &= ~PIPE_BPC_MASK;
3069 if (is_lvds) {
3070 int lvds_reg = I915_READ(PCH_LVDS);
3071 /* the BPC will be 6 if it is 18-bit LVDS panel */
3072 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3073 temp |= PIPE_8BPC;
3074 else
3075 temp |= PIPE_6BPC;
3076 } else if (is_edp) {
3077 switch (dev_priv->edp_bpp/3) {
3078 case 8:
3079 temp |= PIPE_8BPC;
3080 break;
3081 case 10:
3082 temp |= PIPE_10BPC;
3083 break;
3084 case 6:
3085 temp |= PIPE_6BPC;
3086 break;
3087 case 12:
3088 temp |= PIPE_12BPC;
3089 break;
3090 }
3091 } else
3092 temp |= PIPE_8BPC;
3093 I915_WRITE(pipeconf_reg, temp);
3094 I915_READ(pipeconf_reg);
2857 3095
2858 switch (temp & PIPE_BPC_MASK) { 3096 switch (temp & PIPE_BPC_MASK) {
2859 case PIPE_8BPC: 3097 case PIPE_8BPC:
@@ -2873,8 +3111,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2873 bpp = 24; 3111 bpp = 24;
2874 } 3112 }
2875 3113
2876 igdng_compute_m_n(bpp, lane, target_clock, 3114 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
2877 link_bw, &m_n);
2878 } 3115 }
2879 3116
2880 /* Ironlake: try to setup display ref clock before DPLL 3117 /* Ironlake: try to setup display ref clock before DPLL
@@ -2882,7 +3119,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2882 * PCH B stepping, previous chipset stepping should be 3119 * PCH B stepping, previous chipset stepping should be
2883 * ignoring this setting. 3120 * ignoring this setting.
2884 */ 3121 */
2885 if (IS_IGDNG(dev)) { 3122 if (HAS_PCH_SPLIT(dev)) {
2886 temp = I915_READ(PCH_DREF_CONTROL); 3123 temp = I915_READ(PCH_DREF_CONTROL);
2887 /* Always enable nonspread source */ 3124 /* Always enable nonspread source */
2888 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 3125 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
@@ -2917,7 +3154,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2917 } 3154 }
2918 } 3155 }
2919 3156
2920 if (IS_IGD(dev)) { 3157 if (IS_PINEVIEW(dev)) {
2921 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 3158 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2922 if (has_reduced_clock) 3159 if (has_reduced_clock)
2923 fp2 = (1 << reduced_clock.n) << 16 | 3160 fp2 = (1 << reduced_clock.n) << 16 |
@@ -2929,7 +3166,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2929 reduced_clock.m2; 3166 reduced_clock.m2;
2930 } 3167 }
2931 3168
2932 if (!IS_IGDNG(dev)) 3169 if (!HAS_PCH_SPLIT(dev))
2933 dpll = DPLL_VGA_MODE_DIS; 3170 dpll = DPLL_VGA_MODE_DIS;
2934 3171
2935 if (IS_I9XX(dev)) { 3172 if (IS_I9XX(dev)) {
@@ -2942,19 +3179,19 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2942 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 3179 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2943 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 3180 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2944 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 3181 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2945 else if (IS_IGDNG(dev)) 3182 else if (HAS_PCH_SPLIT(dev))
2946 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 3183 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2947 } 3184 }
2948 if (is_dp) 3185 if (is_dp)
2949 dpll |= DPLL_DVO_HIGH_SPEED; 3186 dpll |= DPLL_DVO_HIGH_SPEED;
2950 3187
2951 /* compute bitmask from p1 value */ 3188 /* compute bitmask from p1 value */
2952 if (IS_IGD(dev)) 3189 if (IS_PINEVIEW(dev))
2953 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; 3190 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2954 else { 3191 else {
2955 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3192 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2956 /* also FPA1 */ 3193 /* also FPA1 */
2957 if (IS_IGDNG(dev)) 3194 if (HAS_PCH_SPLIT(dev))
2958 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3195 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2959 if (IS_G4X(dev) && has_reduced_clock) 3196 if (IS_G4X(dev) && has_reduced_clock)
2960 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3197 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
@@ -2973,7 +3210,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2973 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 3210 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2974 break; 3211 break;
2975 } 3212 }
2976 if (IS_I965G(dev) && !IS_IGDNG(dev)) 3213 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
2977 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 3214 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2978 } else { 3215 } else {
2979 if (is_lvds) { 3216 if (is_lvds) {
@@ -2994,7 +3231,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2994 /* XXX: just matching BIOS for now */ 3231 /* XXX: just matching BIOS for now */
2995 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2996 dpll |= 3; 3233 dpll |= 3;
2997 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) 3234 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
2998 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3235 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2999 else 3236 else
3000 dpll |= PLL_REF_INPUT_DREFCLK; 3237 dpll |= PLL_REF_INPUT_DREFCLK;
@@ -3005,9 +3242,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3005 /* Set up the display plane register */ 3242 /* Set up the display plane register */
3006 dspcntr = DISPPLANE_GAMMA_ENABLE; 3243 dspcntr = DISPPLANE_GAMMA_ENABLE;
3007 3244
3008 /* IGDNG's plane is forced to pipe, bit 24 is to 3245 /* Ironlake's plane is forced to pipe, bit 24 is to
3009 enable color space conversion */ 3246 enable color space conversion */
3010 if (!IS_IGDNG(dev)) { 3247 if (!HAS_PCH_SPLIT(dev)) {
3011 if (pipe == 0) 3248 if (pipe == 0)
3012 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 3249 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3013 else 3250 else
@@ -3034,20 +3271,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3034 3271
3035 3272
3036 /* Disable the panel fitter if it was on our pipe */ 3273 /* Disable the panel fitter if it was on our pipe */
3037 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) 3274 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3038 I915_WRITE(PFIT_CONTROL, 0); 3275 I915_WRITE(PFIT_CONTROL, 0);
3039 3276
3040 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3277 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3041 drm_mode_debug_printmodeline(mode); 3278 drm_mode_debug_printmodeline(mode);
3042 3279
3043 /* assign to IGDNG registers */ 3280 /* assign to Ironlake registers */
3044 if (IS_IGDNG(dev)) { 3281 if (HAS_PCH_SPLIT(dev)) {
3045 fp_reg = pch_fp_reg; 3282 fp_reg = pch_fp_reg;
3046 dpll_reg = pch_dpll_reg; 3283 dpll_reg = pch_dpll_reg;
3047 } 3284 }
3048 3285
3049 if (is_edp) { 3286 if (is_edp) {
3050 igdng_disable_pll_edp(crtc); 3287 ironlake_disable_pll_edp(crtc);
3051 } else if ((dpll & DPLL_VCO_ENABLE)) { 3288 } else if ((dpll & DPLL_VCO_ENABLE)) {
3052 I915_WRITE(fp_reg, fp); 3289 I915_WRITE(fp_reg, fp);
3053 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3290 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
@@ -3062,7 +3299,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3062 if (is_lvds) { 3299 if (is_lvds) {
3063 u32 lvds; 3300 u32 lvds;
3064 3301
3065 if (IS_IGDNG(dev)) 3302 if (HAS_PCH_SPLIT(dev))
3066 lvds_reg = PCH_LVDS; 3303 lvds_reg = PCH_LVDS;
3067 3304
3068 lvds = I915_READ(lvds_reg); 3305 lvds = I915_READ(lvds_reg);
@@ -3081,7 +3318,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3081 * appropriately here, but we need to look more thoroughly into how 3318 * appropriately here, but we need to look more thoroughly into how
3082 * panels behave in the two modes. 3319 * panels behave in the two modes.
3083 */ 3320 */
3084 3321 /* set the dithering flag */
3322 if (IS_I965G(dev)) {
3323 if (dev_priv->lvds_dither) {
3324 if (HAS_PCH_SPLIT(dev))
3325 pipeconf |= PIPE_ENABLE_DITHER;
3326 else
3327 lvds |= LVDS_ENABLE_DITHER;
3328 } else {
3329 if (HAS_PCH_SPLIT(dev))
3330 pipeconf &= ~PIPE_ENABLE_DITHER;
3331 else
3332 lvds &= ~LVDS_ENABLE_DITHER;
3333 }
3334 }
3085 I915_WRITE(lvds_reg, lvds); 3335 I915_WRITE(lvds_reg, lvds);
3086 I915_READ(lvds_reg); 3336 I915_READ(lvds_reg);
3087 } 3337 }
@@ -3095,7 +3345,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3095 /* Wait for the clocks to stabilize. */ 3345 /* Wait for the clocks to stabilize. */
3096 udelay(150); 3346 udelay(150);
3097 3347
3098 if (IS_I965G(dev) && !IS_IGDNG(dev)) { 3348 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3099 if (is_sdvo) { 3349 if (is_sdvo) {
3100 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 3350 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3101 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | 3351 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
@@ -3115,14 +3365,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3115 I915_WRITE(fp_reg + 4, fp2); 3365 I915_WRITE(fp_reg + 4, fp2);
3116 intel_crtc->lowfreq_avail = true; 3366 intel_crtc->lowfreq_avail = true;
3117 if (HAS_PIPE_CXSR(dev)) { 3367 if (HAS_PIPE_CXSR(dev)) {
3118 DRM_DEBUG("enabling CxSR downclocking\n"); 3368 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3119 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 3369 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3120 } 3370 }
3121 } else { 3371 } else {
3122 I915_WRITE(fp_reg + 4, fp); 3372 I915_WRITE(fp_reg + 4, fp);
3123 intel_crtc->lowfreq_avail = false; 3373 intel_crtc->lowfreq_avail = false;
3124 if (HAS_PIPE_CXSR(dev)) { 3374 if (HAS_PIPE_CXSR(dev)) {
3125 DRM_DEBUG("disabling CxSR downclocking\n"); 3375 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3126 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 3376 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3127 } 3377 }
3128 } 3378 }
@@ -3142,21 +3392,21 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3142 /* pipesrc and dspsize control the size that is scaled from, which should 3392 /* pipesrc and dspsize control the size that is scaled from, which should
3143 * always be the user's requested size. 3393 * always be the user's requested size.
3144 */ 3394 */
3145 if (!IS_IGDNG(dev)) { 3395 if (!HAS_PCH_SPLIT(dev)) {
3146 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | 3396 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3147 (mode->hdisplay - 1)); 3397 (mode->hdisplay - 1));
3148 I915_WRITE(dsppos_reg, 0); 3398 I915_WRITE(dsppos_reg, 0);
3149 } 3399 }
3150 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 3400 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3151 3401
3152 if (IS_IGDNG(dev)) { 3402 if (HAS_PCH_SPLIT(dev)) {
3153 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); 3403 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3154 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); 3404 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3155 I915_WRITE(link_m1_reg, m_n.link_m); 3405 I915_WRITE(link_m1_reg, m_n.link_m);
3156 I915_WRITE(link_n1_reg, m_n.link_n); 3406 I915_WRITE(link_n1_reg, m_n.link_n);
3157 3407
3158 if (is_edp) { 3408 if (is_edp) {
3159 igdng_set_pll_edp(crtc, adjusted_mode->clock); 3409 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3160 } else { 3410 } else {
3161 /* enable FDI RX PLL too */ 3411 /* enable FDI RX PLL too */
3162 temp = I915_READ(fdi_rx_reg); 3412 temp = I915_READ(fdi_rx_reg);
@@ -3170,7 +3420,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3170 3420
3171 intel_wait_for_vblank(dev); 3421 intel_wait_for_vblank(dev);
3172 3422
3173 if (IS_IGDNG(dev)) { 3423 if (IS_IRONLAKE(dev)) {
3174 /* enable address swizzle for tiling buffer */ 3424 /* enable address swizzle for tiling buffer */
3175 temp = I915_READ(DISP_ARB_CTL); 3425 temp = I915_READ(DISP_ARB_CTL);
3176 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); 3426 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
@@ -3204,8 +3454,8 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
3204 if (!crtc->enabled) 3454 if (!crtc->enabled)
3205 return; 3455 return;
3206 3456
3207 /* use legacy palette for IGDNG */ 3457 /* use legacy palette for Ironlake */
3208 if (IS_IGDNG(dev)) 3458 if (HAS_PCH_SPLIT(dev))
3209 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : 3459 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3210 LGC_PALETTE_B; 3460 LGC_PALETTE_B;
3211 3461
@@ -3234,11 +3484,11 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3234 size_t addr; 3484 size_t addr;
3235 int ret; 3485 int ret;
3236 3486
3237 DRM_DEBUG("\n"); 3487 DRM_DEBUG_KMS("\n");
3238 3488
3239 /* if we want to turn off the cursor ignore width and height */ 3489 /* if we want to turn off the cursor ignore width and height */
3240 if (!handle) { 3490 if (!handle) {
3241 DRM_DEBUG("cursor off\n"); 3491 DRM_DEBUG_KMS("cursor off\n");
3242 if (IS_MOBILE(dev) || IS_I9XX(dev)) { 3492 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3243 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 3493 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3244 temp |= CURSOR_MODE_DISABLE; 3494 temp |= CURSOR_MODE_DISABLE;
@@ -3261,7 +3511,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3261 if (!bo) 3511 if (!bo)
3262 return -ENOENT; 3512 return -ENOENT;
3263 3513
3264 obj_priv = bo->driver_private; 3514 obj_priv = to_intel_bo(bo);
3265 3515
3266 if (bo->size < width * height * 4) { 3516 if (bo->size < width * height * 4) {
3267 DRM_ERROR("buffer is to small\n"); 3517 DRM_ERROR("buffer is to small\n");
@@ -3271,7 +3521,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3271 3521
3272 /* we only need to pin inside GTT if cursor is non-phy */ 3522 /* we only need to pin inside GTT if cursor is non-phy */
3273 mutex_lock(&dev->struct_mutex); 3523 mutex_lock(&dev->struct_mutex);
3274 if (!dev_priv->cursor_needs_physical) { 3524 if (!dev_priv->info->cursor_needs_physical) {
3275 ret = i915_gem_object_pin(bo, PAGE_SIZE); 3525 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3276 if (ret) { 3526 if (ret) {
3277 DRM_ERROR("failed to pin cursor bo\n"); 3527 DRM_ERROR("failed to pin cursor bo\n");
@@ -3306,7 +3556,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3306 I915_WRITE(base, addr); 3556 I915_WRITE(base, addr);
3307 3557
3308 if (intel_crtc->cursor_bo) { 3558 if (intel_crtc->cursor_bo) {
3309 if (dev_priv->cursor_needs_physical) { 3559 if (dev_priv->info->cursor_needs_physical) {
3310 if (intel_crtc->cursor_bo != bo) 3560 if (intel_crtc->cursor_bo != bo)
3311 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 3561 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3312 } else 3562 } else
@@ -3320,11 +3570,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3320 intel_crtc->cursor_bo = bo; 3570 intel_crtc->cursor_bo = bo;
3321 3571
3322 return 0; 3572 return 0;
3323fail:
3324 mutex_lock(&dev->struct_mutex);
3325fail_locked: 3573fail_locked:
3326 drm_gem_object_unreference(bo);
3327 mutex_unlock(&dev->struct_mutex); 3574 mutex_unlock(&dev->struct_mutex);
3575fail:
3576 drm_gem_object_unreference_unlocked(bo);
3328 return ret; 3577 return ret;
3329} 3578}
3330 3579
@@ -3406,9 +3655,9 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3406 * detection. 3655 * detection.
3407 * 3656 *
3408 * It will be up to the load-detect code to adjust the pipe as appropriate for 3657 * It will be up to the load-detect code to adjust the pipe as appropriate for
3409 * its requirements. The pipe will be connected to no other outputs. 3658 * its requirements. The pipe will be connected to no other encoders.
3410 * 3659 *
3411 * Currently this code will only succeed if there is a pipe with no outputs 3660 * Currently this code will only succeed if there is a pipe with no encoders
3412 * configured for it. In the future, it could choose to temporarily disable 3661 * configured for it. In the future, it could choose to temporarily disable
3413 * some outputs to free up a pipe for its use. 3662 * some outputs to free up a pipe for its use.
3414 * 3663 *
@@ -3421,14 +3670,14 @@ static struct drm_display_mode load_detect_mode = {
3421 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 3670 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3422}; 3671};
3423 3672
3424struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, 3673struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3425 struct drm_display_mode *mode, 3674 struct drm_display_mode *mode,
3426 int *dpms_mode) 3675 int *dpms_mode)
3427{ 3676{
3428 struct intel_crtc *intel_crtc; 3677 struct intel_crtc *intel_crtc;
3429 struct drm_crtc *possible_crtc; 3678 struct drm_crtc *possible_crtc;
3430 struct drm_crtc *supported_crtc =NULL; 3679 struct drm_crtc *supported_crtc =NULL;
3431 struct drm_encoder *encoder = &intel_output->enc; 3680 struct drm_encoder *encoder = &intel_encoder->enc;
3432 struct drm_crtc *crtc = NULL; 3681 struct drm_crtc *crtc = NULL;
3433 struct drm_device *dev = encoder->dev; 3682 struct drm_device *dev = encoder->dev;
3434 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3683 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
@@ -3480,8 +3729,8 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3480 } 3729 }
3481 3730
3482 encoder->crtc = crtc; 3731 encoder->crtc = crtc;
3483 intel_output->base.encoder = encoder; 3732 intel_encoder->base.encoder = encoder;
3484 intel_output->load_detect_temp = true; 3733 intel_encoder->load_detect_temp = true;
3485 3734
3486 intel_crtc = to_intel_crtc(crtc); 3735 intel_crtc = to_intel_crtc(crtc);
3487 *dpms_mode = intel_crtc->dpms_mode; 3736 *dpms_mode = intel_crtc->dpms_mode;
@@ -3506,23 +3755,23 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3506 return crtc; 3755 return crtc;
3507} 3756}
3508 3757
3509void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) 3758void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpms_mode)
3510{ 3759{
3511 struct drm_encoder *encoder = &intel_output->enc; 3760 struct drm_encoder *encoder = &intel_encoder->enc;
3512 struct drm_device *dev = encoder->dev; 3761 struct drm_device *dev = encoder->dev;
3513 struct drm_crtc *crtc = encoder->crtc; 3762 struct drm_crtc *crtc = encoder->crtc;
3514 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3763 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3515 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 3764 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3516 3765
3517 if (intel_output->load_detect_temp) { 3766 if (intel_encoder->load_detect_temp) {
3518 encoder->crtc = NULL; 3767 encoder->crtc = NULL;
3519 intel_output->base.encoder = NULL; 3768 intel_encoder->base.encoder = NULL;
3520 intel_output->load_detect_temp = false; 3769 intel_encoder->load_detect_temp = false;
3521 crtc->enabled = drm_helper_crtc_in_use(crtc); 3770 crtc->enabled = drm_helper_crtc_in_use(crtc);
3522 drm_helper_disable_unused_functions(dev); 3771 drm_helper_disable_unused_functions(dev);
3523 } 3772 }
3524 3773
3525 /* Switch crtc and output back off if necessary */ 3774 /* Switch crtc and encoder back off if necessary */
3526 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { 3775 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3527 if (encoder->crtc == crtc) 3776 if (encoder->crtc == crtc)
3528 encoder_funcs->dpms(encoder, dpms_mode); 3777 encoder_funcs->dpms(encoder, dpms_mode);
@@ -3546,18 +3795,18 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3546 fp = I915_READ((pipe == 0) ? FPA1 : FPB1); 3795 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3547 3796
3548 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3797 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3549 if (IS_IGD(dev)) { 3798 if (IS_PINEVIEW(dev)) {
3550 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3799 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3551 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; 3800 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3552 } else { 3801 } else {
3553 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3802 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3554 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3803 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3555 } 3804 }
3556 3805
3557 if (IS_I9XX(dev)) { 3806 if (IS_I9XX(dev)) {
3558 if (IS_IGD(dev)) 3807 if (IS_PINEVIEW(dev))
3559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> 3808 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3560 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); 3809 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3561 else 3810 else
3562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3811 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3563 DPLL_FPA01_P1_POST_DIV_SHIFT); 3812 DPLL_FPA01_P1_POST_DIV_SHIFT);
@@ -3572,7 +3821,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3572 7 : 14; 3821 7 : 14;
3573 break; 3822 break;
3574 default: 3823 default:
3575 DRM_DEBUG("Unknown DPLL mode %08x in programmed " 3824 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3576 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3825 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3577 return 0; 3826 return 0;
3578 } 3827 }
@@ -3658,132 +3907,13 @@ static void intel_gpu_idle_timer(unsigned long arg)
3658 struct drm_device *dev = (struct drm_device *)arg; 3907 struct drm_device *dev = (struct drm_device *)arg;
3659 drm_i915_private_t *dev_priv = dev->dev_private; 3908 drm_i915_private_t *dev_priv = dev->dev_private;
3660 3909
3661 DRM_DEBUG("idle timer fired, downclocking\n"); 3910 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3662 3911
3663 dev_priv->busy = false; 3912 dev_priv->busy = false;
3664 3913
3665 queue_work(dev_priv->wq, &dev_priv->idle_work); 3914 queue_work(dev_priv->wq, &dev_priv->idle_work);
3666} 3915}
3667 3916
3668void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3669{
3670 drm_i915_private_t *dev_priv = dev->dev_private;
3671
3672 if (IS_IGDNG(dev))
3673 return;
3674
3675 if (!dev_priv->render_reclock_avail) {
3676 DRM_DEBUG("not reclocking render clock\n");
3677 return;
3678 }
3679
3680 /* Restore render clock frequency to original value */
3681 if (IS_G4X(dev) || IS_I9XX(dev))
3682 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3683 else if (IS_I85X(dev))
3684 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3685 DRM_DEBUG("increasing render clock frequency\n");
3686
3687 /* Schedule downclock */
3688 if (schedule)
3689 mod_timer(&dev_priv->idle_timer, jiffies +
3690 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3691}
3692
3693void intel_decrease_renderclock(struct drm_device *dev)
3694{
3695 drm_i915_private_t *dev_priv = dev->dev_private;
3696
3697 if (IS_IGDNG(dev))
3698 return;
3699
3700 if (!dev_priv->render_reclock_avail) {
3701 DRM_DEBUG("not reclocking render clock\n");
3702 return;
3703 }
3704
3705 if (IS_G4X(dev)) {
3706 u16 gcfgc;
3707
3708 /* Adjust render clock... */
3709 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3710
3711 /* Down to minimum... */
3712 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3713 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3714
3715 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3716 } else if (IS_I965G(dev)) {
3717 u16 gcfgc;
3718
3719 /* Adjust render clock... */
3720 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3721
3722 /* Down to minimum... */
3723 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3724 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3725
3726 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3727 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3728 u16 gcfgc;
3729
3730 /* Adjust render clock... */
3731 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3732
3733 /* Down to minimum... */
3734 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3735 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3736
3737 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3738 } else if (IS_I915G(dev)) {
3739 u16 gcfgc;
3740
3741 /* Adjust render clock... */
3742 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3743
3744 /* Down to minimum... */
3745 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3746 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3747
3748 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3749 } else if (IS_I85X(dev)) {
3750 u16 hpllcc;
3751
3752 /* Adjust render clock... */
3753 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3754
3755 /* Up to maximum... */
3756 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3757 hpllcc |= GC_CLOCK_133_200;
3758
3759 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3760 }
3761 DRM_DEBUG("decreasing render clock frequency\n");
3762}
3763
3764/* Note that no increase function is needed for this - increase_renderclock()
3765 * will also rewrite these bits
3766 */
3767void intel_decrease_displayclock(struct drm_device *dev)
3768{
3769 if (IS_IGDNG(dev))
3770 return;
3771
3772 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3773 IS_I915GM(dev)) {
3774 u16 gcfgc;
3775
3776 /* Adjust render clock... */
3777 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3778
3779 /* Down to minimum... */
3780 gcfgc &= ~0xf0;
3781 gcfgc |= 0x80;
3782
3783 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3784 }
3785}
3786
3787#define CRTC_IDLE_TIMEOUT 1000 /* ms */ 3917#define CRTC_IDLE_TIMEOUT 1000 /* ms */
3788 3918
3789static void intel_crtc_idle_timer(unsigned long arg) 3919static void intel_crtc_idle_timer(unsigned long arg)
@@ -3792,7 +3922,7 @@ static void intel_crtc_idle_timer(unsigned long arg)
3792 struct drm_crtc *crtc = &intel_crtc->base; 3922 struct drm_crtc *crtc = &intel_crtc->base;
3793 drm_i915_private_t *dev_priv = crtc->dev->dev_private; 3923 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3794 3924
3795 DRM_DEBUG("idle timer fired, downclocking\n"); 3925 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3796 3926
3797 intel_crtc->busy = false; 3927 intel_crtc->busy = false;
3798 3928
@@ -3808,14 +3938,14 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3808 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 3938 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3809 int dpll = I915_READ(dpll_reg); 3939 int dpll = I915_READ(dpll_reg);
3810 3940
3811 if (IS_IGDNG(dev)) 3941 if (HAS_PCH_SPLIT(dev))
3812 return; 3942 return;
3813 3943
3814 if (!dev_priv->lvds_downclock_avail) 3944 if (!dev_priv->lvds_downclock_avail)
3815 return; 3945 return;
3816 3946
3817 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 3947 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3818 DRM_DEBUG("upclocking LVDS\n"); 3948 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3819 3949
3820 /* Unlock panel regs */ 3950 /* Unlock panel regs */
3821 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3951 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3826,7 +3956,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3826 intel_wait_for_vblank(dev); 3956 intel_wait_for_vblank(dev);
3827 dpll = I915_READ(dpll_reg); 3957 dpll = I915_READ(dpll_reg);
3828 if (dpll & DISPLAY_RATE_SELECT_FPA1) 3958 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3829 DRM_DEBUG("failed to upclock LVDS!\n"); 3959 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3830 3960
3831 /* ...and lock them again */ 3961 /* ...and lock them again */
3832 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3962 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -3847,7 +3977,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3847 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 3977 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3848 int dpll = I915_READ(dpll_reg); 3978 int dpll = I915_READ(dpll_reg);
3849 3979
3850 if (IS_IGDNG(dev)) 3980 if (HAS_PCH_SPLIT(dev))
3851 return; 3981 return;
3852 3982
3853 if (!dev_priv->lvds_downclock_avail) 3983 if (!dev_priv->lvds_downclock_avail)
@@ -3858,7 +3988,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3858 * the manual case. 3988 * the manual case.
3859 */ 3989 */
3860 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 3990 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3861 DRM_DEBUG("downclocking LVDS\n"); 3991 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3862 3992
3863 /* Unlock panel regs */ 3993 /* Unlock panel regs */
3864 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3994 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3869,7 +3999,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3869 intel_wait_for_vblank(dev); 3999 intel_wait_for_vblank(dev);
3870 dpll = I915_READ(dpll_reg); 4000 dpll = I915_READ(dpll_reg);
3871 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 4001 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3872 DRM_DEBUG("failed to downclock LVDS!\n"); 4002 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3873 4003
3874 /* ...and lock them again */ 4004 /* ...and lock them again */
3875 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 4005 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -3897,10 +4027,9 @@ static void intel_idle_update(struct work_struct *work)
3897 4027
3898 mutex_lock(&dev->struct_mutex); 4028 mutex_lock(&dev->struct_mutex);
3899 4029
3900 /* GPU isn't processing, downclock it. */ 4030 if (IS_I945G(dev) || IS_I945GM(dev)) {
3901 if (!dev_priv->busy) { 4031 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
3902 intel_decrease_renderclock(dev); 4032 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3903 intel_decrease_displayclock(dev);
3904 } 4033 }
3905 4034
3906 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4035 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -3936,8 +4065,19 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3936 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4065 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3937 return; 4066 return;
3938 4067
3939 dev_priv->busy = true; 4068 if (!dev_priv->busy) {
3940 intel_increase_renderclock(dev, true); 4069 if (IS_I945G(dev) || IS_I945GM(dev)) {
4070 u32 fw_blc_self;
4071
4072 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4073 fw_blc_self = I915_READ(FW_BLC_SELF);
4074 fw_blc_self &= ~FW_BLC_SELF_EN;
4075 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4076 }
4077 dev_priv->busy = true;
4078 } else
4079 mod_timer(&dev_priv->idle_timer, jiffies +
4080 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3941 4081
3942 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3943 if (!crtc->fb) 4083 if (!crtc->fb)
@@ -3947,6 +4087,14 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3947 intel_fb = to_intel_framebuffer(crtc->fb); 4087 intel_fb = to_intel_framebuffer(crtc->fb);
3948 if (intel_fb->obj == obj) { 4088 if (intel_fb->obj == obj) {
3949 if (!intel_crtc->busy) { 4089 if (!intel_crtc->busy) {
4090 if (IS_I945G(dev) || IS_I945GM(dev)) {
4091 u32 fw_blc_self;
4092
4093 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4094 fw_blc_self = I915_READ(FW_BLC_SELF);
4095 fw_blc_self &= ~FW_BLC_SELF_EN;
4096 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4097 }
3950 /* Non-busy -> busy, upclock */ 4098 /* Non-busy -> busy, upclock */
3951 intel_increase_pllclock(crtc, true); 4099 intel_increase_pllclock(crtc, true);
3952 intel_crtc->busy = true; 4100 intel_crtc->busy = true;
@@ -3967,6 +4115,180 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
3967 kfree(intel_crtc); 4115 kfree(intel_crtc);
3968} 4116}
3969 4117
4118struct intel_unpin_work {
4119 struct work_struct work;
4120 struct drm_device *dev;
4121 struct drm_gem_object *old_fb_obj;
4122 struct drm_gem_object *pending_flip_obj;
4123 struct drm_pending_vblank_event *event;
4124 int pending;
4125};
4126
4127static void intel_unpin_work_fn(struct work_struct *__work)
4128{
4129 struct intel_unpin_work *work =
4130 container_of(__work, struct intel_unpin_work, work);
4131
4132 mutex_lock(&work->dev->struct_mutex);
4133 i915_gem_object_unpin(work->old_fb_obj);
4134 drm_gem_object_unreference(work->pending_flip_obj);
4135 drm_gem_object_unreference(work->old_fb_obj);
4136 mutex_unlock(&work->dev->struct_mutex);
4137 kfree(work);
4138}
4139
4140void intel_finish_page_flip(struct drm_device *dev, int pipe)
4141{
4142 drm_i915_private_t *dev_priv = dev->dev_private;
4143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145 struct intel_unpin_work *work;
4146 struct drm_i915_gem_object *obj_priv;
4147 struct drm_pending_vblank_event *e;
4148 struct timeval now;
4149 unsigned long flags;
4150
4151 /* Ignore early vblank irqs */
4152 if (intel_crtc == NULL)
4153 return;
4154
4155 spin_lock_irqsave(&dev->event_lock, flags);
4156 work = intel_crtc->unpin_work;
4157 if (work == NULL || !work->pending) {
4158 if (work && !work->pending) {
4159 obj_priv = to_intel_bo(work->pending_flip_obj);
4160 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4161 obj_priv,
4162 atomic_read(&obj_priv->pending_flip));
4163 }
4164 spin_unlock_irqrestore(&dev->event_lock, flags);
4165 return;
4166 }
4167
4168 intel_crtc->unpin_work = NULL;
4169 drm_vblank_put(dev, intel_crtc->pipe);
4170
4171 if (work->event) {
4172 e = work->event;
4173 do_gettimeofday(&now);
4174 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4175 e->event.tv_sec = now.tv_sec;
4176 e->event.tv_usec = now.tv_usec;
4177 list_add_tail(&e->base.link,
4178 &e->base.file_priv->event_list);
4179 wake_up_interruptible(&e->base.file_priv->event_wait);
4180 }
4181
4182 spin_unlock_irqrestore(&dev->event_lock, flags);
4183
4184 obj_priv = to_intel_bo(work->pending_flip_obj);
4185
4186 /* Initial scanout buffer will have a 0 pending flip count */
4187 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4188 atomic_dec_and_test(&obj_priv->pending_flip))
4189 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4190 schedule_work(&work->work);
4191}
4192
4193void intel_prepare_page_flip(struct drm_device *dev, int plane)
4194{
4195 drm_i915_private_t *dev_priv = dev->dev_private;
4196 struct intel_crtc *intel_crtc =
4197 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4198 unsigned long flags;
4199
4200 spin_lock_irqsave(&dev->event_lock, flags);
4201 if (intel_crtc->unpin_work) {
4202 intel_crtc->unpin_work->pending = 1;
4203 } else {
4204 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4205 }
4206 spin_unlock_irqrestore(&dev->event_lock, flags);
4207}
4208
4209static int intel_crtc_page_flip(struct drm_crtc *crtc,
4210 struct drm_framebuffer *fb,
4211 struct drm_pending_vblank_event *event)
4212{
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_framebuffer *intel_fb;
4216 struct drm_i915_gem_object *obj_priv;
4217 struct drm_gem_object *obj;
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219 struct intel_unpin_work *work;
4220 unsigned long flags;
4221 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4222 int ret, pipesrc;
4223 RING_LOCALS;
4224
4225 work = kzalloc(sizeof *work, GFP_KERNEL);
4226 if (work == NULL)
4227 return -ENOMEM;
4228
4229 mutex_lock(&dev->struct_mutex);
4230
4231 work->event = event;
4232 work->dev = crtc->dev;
4233 intel_fb = to_intel_framebuffer(crtc->fb);
4234 work->old_fb_obj = intel_fb->obj;
4235 INIT_WORK(&work->work, intel_unpin_work_fn);
4236
4237 /* We borrow the event spin lock for protecting unpin_work */
4238 spin_lock_irqsave(&dev->event_lock, flags);
4239 if (intel_crtc->unpin_work) {
4240 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4241 spin_unlock_irqrestore(&dev->event_lock, flags);
4242 kfree(work);
4243 mutex_unlock(&dev->struct_mutex);
4244 return -EBUSY;
4245 }
4246 intel_crtc->unpin_work = work;
4247 spin_unlock_irqrestore(&dev->event_lock, flags);
4248
4249 intel_fb = to_intel_framebuffer(fb);
4250 obj = intel_fb->obj;
4251
4252 ret = intel_pin_and_fence_fb_obj(dev, obj);
4253 if (ret != 0) {
4254 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4255 to_intel_bo(obj));
4256 kfree(work);
4257 intel_crtc->unpin_work = NULL;
4258 mutex_unlock(&dev->struct_mutex);
4259 return ret;
4260 }
4261
4262 /* Reference the objects for the scheduled work. */
4263 drm_gem_object_reference(work->old_fb_obj);
4264 drm_gem_object_reference(obj);
4265
4266 crtc->fb = fb;
4267 i915_gem_object_flush_write_domain(obj);
4268 drm_vblank_get(dev, intel_crtc->pipe);
4269 obj_priv = to_intel_bo(obj);
4270 atomic_inc(&obj_priv->pending_flip);
4271 work->pending_flip_obj = obj;
4272
4273 BEGIN_LP_RING(4);
4274 OUT_RING(MI_DISPLAY_FLIP |
4275 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4276 OUT_RING(fb->pitch);
4277 if (IS_I965G(dev)) {
4278 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4279 pipesrc = I915_READ(pipesrc_reg);
4280 OUT_RING(pipesrc & 0x0fff0fff);
4281 } else {
4282 OUT_RING(obj_priv->gtt_offset);
4283 OUT_RING(MI_NOOP);
4284 }
4285 ADVANCE_LP_RING();
4286
4287 mutex_unlock(&dev->struct_mutex);
4288
4289 return 0;
4290}
4291
3970static const struct drm_crtc_helper_funcs intel_helper_funcs = { 4292static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3971 .dpms = intel_crtc_dpms, 4293 .dpms = intel_crtc_dpms,
3972 .mode_fixup = intel_crtc_mode_fixup, 4294 .mode_fixup = intel_crtc_mode_fixup,
@@ -3983,11 +4305,13 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
3983 .gamma_set = intel_crtc_gamma_set, 4305 .gamma_set = intel_crtc_gamma_set,
3984 .set_config = drm_crtc_helper_set_config, 4306 .set_config = drm_crtc_helper_set_config,
3985 .destroy = intel_crtc_destroy, 4307 .destroy = intel_crtc_destroy,
4308 .page_flip = intel_crtc_page_flip,
3986}; 4309};
3987 4310
3988 4311
3989static void intel_crtc_init(struct drm_device *dev, int pipe) 4312static void intel_crtc_init(struct drm_device *dev, int pipe)
3990{ 4313{
4314 drm_i915_private_t *dev_priv = dev->dev_private;
3991 struct intel_crtc *intel_crtc; 4315 struct intel_crtc *intel_crtc;
3992 int i; 4316 int i;
3993 4317
@@ -4010,10 +4334,15 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
4010 intel_crtc->pipe = pipe; 4334 intel_crtc->pipe = pipe;
4011 intel_crtc->plane = pipe; 4335 intel_crtc->plane = pipe;
4012 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) { 4336 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4013 DRM_DEBUG("swapping pipes & planes for FBC\n"); 4337 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4014 intel_crtc->plane = ((pipe == 0) ? 1 : 0); 4338 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4015 } 4339 }
4016 4340
4341 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4342 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4343 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4344 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4345
4017 intel_crtc->cursor_addr = 0; 4346 intel_crtc->cursor_addr = 0;
4018 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 4347 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4019 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 4348 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
@@ -4070,8 +4399,8 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
4070 int entry = 0; 4399 int entry = 0;
4071 4400
4072 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4073 struct intel_output *intel_output = to_intel_output(connector); 4402 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4074 if (type_mask & intel_output->clone_mask) 4403 if (type_mask & intel_encoder->clone_mask)
4075 index_mask |= (1 << entry); 4404 index_mask |= (1 << entry);
4076 entry++; 4405 entry++;
4077 } 4406 }
@@ -4090,7 +4419,7 @@ static void intel_setup_outputs(struct drm_device *dev)
4090 if (IS_MOBILE(dev) && !IS_I830(dev)) 4419 if (IS_MOBILE(dev) && !IS_I830(dev))
4091 intel_lvds_init(dev); 4420 intel_lvds_init(dev);
4092 4421
4093 if (IS_IGDNG(dev)) { 4422 if (HAS_PCH_SPLIT(dev)) {
4094 int found; 4423 int found;
4095 4424
4096 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) 4425 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
@@ -4118,46 +4447,60 @@ static void intel_setup_outputs(struct drm_device *dev)
4118 if (I915_READ(PCH_DP_D) & DP_DETECTED) 4447 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4119 intel_dp_init(dev, PCH_DP_D); 4448 intel_dp_init(dev, PCH_DP_D);
4120 4449
4121 } else if (IS_I9XX(dev)) { 4450 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4122 bool found = false; 4451 bool found = false;
4123 4452
4124 if (I915_READ(SDVOB) & SDVO_DETECTED) { 4453 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4454 DRM_DEBUG_KMS("probing SDVOB\n");
4125 found = intel_sdvo_init(dev, SDVOB); 4455 found = intel_sdvo_init(dev, SDVOB);
4126 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 4456 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4457 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4127 intel_hdmi_init(dev, SDVOB); 4458 intel_hdmi_init(dev, SDVOB);
4459 }
4128 4460
4129 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 4461 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4462 DRM_DEBUG_KMS("probing DP_B\n");
4130 intel_dp_init(dev, DP_B); 4463 intel_dp_init(dev, DP_B);
4464 }
4131 } 4465 }
4132 4466
4133 /* Before G4X SDVOC doesn't have its own detect register */ 4467 /* Before G4X SDVOC doesn't have its own detect register */
4134 4468
4135 if (I915_READ(SDVOB) & SDVO_DETECTED) 4469 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4470 DRM_DEBUG_KMS("probing SDVOC\n");
4136 found = intel_sdvo_init(dev, SDVOC); 4471 found = intel_sdvo_init(dev, SDVOC);
4472 }
4137 4473
4138 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 4474 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4139 4475
4140 if (SUPPORTS_INTEGRATED_HDMI(dev)) 4476 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4477 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4141 intel_hdmi_init(dev, SDVOC); 4478 intel_hdmi_init(dev, SDVOC);
4142 if (SUPPORTS_INTEGRATED_DP(dev)) 4479 }
4480 if (SUPPORTS_INTEGRATED_DP(dev)) {
4481 DRM_DEBUG_KMS("probing DP_C\n");
4143 intel_dp_init(dev, DP_C); 4482 intel_dp_init(dev, DP_C);
4483 }
4144 } 4484 }
4145 4485
4146 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 4486 if (SUPPORTS_INTEGRATED_DP(dev) &&
4487 (I915_READ(DP_D) & DP_DETECTED)) {
4488 DRM_DEBUG_KMS("probing DP_D\n");
4147 intel_dp_init(dev, DP_D); 4489 intel_dp_init(dev, DP_D);
4148 } else 4490 }
4491 } else if (IS_GEN2(dev))
4149 intel_dvo_init(dev); 4492 intel_dvo_init(dev);
4150 4493
4151 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) 4494 if (SUPPORTS_TV(dev))
4152 intel_tv_init(dev); 4495 intel_tv_init(dev);
4153 4496
4154 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4155 struct intel_output *intel_output = to_intel_output(connector); 4498 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4156 struct drm_encoder *encoder = &intel_output->enc; 4499 struct drm_encoder *encoder = &intel_encoder->enc;
4157 4500
4158 encoder->possible_crtcs = intel_output->crtc_mask; 4501 encoder->possible_crtcs = intel_encoder->crtc_mask;
4159 encoder->possible_clones = intel_connector_clones(dev, 4502 encoder->possible_clones = intel_connector_clones(dev,
4160 intel_output->clone_mask); 4503 intel_encoder->clone_mask);
4161 } 4504 }
4162} 4505}
4163 4506
@@ -4170,9 +4513,7 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4170 intelfb_remove(dev, fb); 4513 intelfb_remove(dev, fb);
4171 4514
4172 drm_framebuffer_cleanup(fb); 4515 drm_framebuffer_cleanup(fb);
4173 mutex_lock(&dev->struct_mutex); 4516 drm_gem_object_unreference_unlocked(intel_fb->obj);
4174 drm_gem_object_unreference(intel_fb->obj);
4175 mutex_unlock(&dev->struct_mutex);
4176 4517
4177 kfree(intel_fb); 4518 kfree(intel_fb);
4178} 4519}
@@ -4235,9 +4576,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
4235 4576
4236 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); 4577 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4237 if (ret) { 4578 if (ret) {
4238 mutex_lock(&dev->struct_mutex); 4579 drm_gem_object_unreference_unlocked(obj);
4239 drm_gem_object_unreference(obj);
4240 mutex_unlock(&dev->struct_mutex);
4241 return NULL; 4580 return NULL;
4242 } 4581 }
4243 4582
@@ -4249,6 +4588,127 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
4249 .fb_changed = intelfb_probe, 4588 .fb_changed = intelfb_probe,
4250}; 4589};
4251 4590
4591static struct drm_gem_object *
4592intel_alloc_power_context(struct drm_device *dev)
4593{
4594 struct drm_gem_object *pwrctx;
4595 int ret;
4596
4597 pwrctx = drm_gem_object_alloc(dev, 4096);
4598 if (!pwrctx) {
4599 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4600 return NULL;
4601 }
4602
4603 mutex_lock(&dev->struct_mutex);
4604 ret = i915_gem_object_pin(pwrctx, 4096);
4605 if (ret) {
4606 DRM_ERROR("failed to pin power context: %d\n", ret);
4607 goto err_unref;
4608 }
4609
4610 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4611 if (ret) {
4612 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4613 goto err_unpin;
4614 }
4615 mutex_unlock(&dev->struct_mutex);
4616
4617 return pwrctx;
4618
4619err_unpin:
4620 i915_gem_object_unpin(pwrctx);
4621err_unref:
4622 drm_gem_object_unreference(pwrctx);
4623 mutex_unlock(&dev->struct_mutex);
4624 return NULL;
4625}
4626
4627void ironlake_enable_drps(struct drm_device *dev)
4628{
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4631 u8 fmax, fmin, fstart, vstart;
4632 int i = 0;
4633
4634 /* 100ms RC evaluation intervals */
4635 I915_WRITE(RCUPEI, 100000);
4636 I915_WRITE(RCDNEI, 100000);
4637
4638 /* Set max/min thresholds to 90ms and 80ms respectively */
4639 I915_WRITE(RCBMAXAVG, 90000);
4640 I915_WRITE(RCBMINAVG, 80000);
4641
4642 I915_WRITE(MEMIHYST, 1);
4643
4644 /* Set up min, max, and cur for interrupt handling */
4645 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4646 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4647 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4648 MEMMODE_FSTART_SHIFT;
4649 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4650 PXVFREQ_PX_SHIFT;
4651
4652 dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4653 dev_priv->min_delay = fmin;
4654 dev_priv->cur_delay = fstart;
4655
4656 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4657
4658 /*
4659 * Interrupts will be enabled in ironlake_irq_postinstall
4660 */
4661
4662 I915_WRITE(VIDSTART, vstart);
4663 POSTING_READ(VIDSTART);
4664
4665 rgvmodectl |= MEMMODE_SWMODE_EN;
4666 I915_WRITE(MEMMODECTL, rgvmodectl);
4667
4668 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4669 if (i++ > 100) {
4670 DRM_ERROR("stuck trying to change perf mode\n");
4671 break;
4672 }
4673 msleep(1);
4674 }
4675 msleep(1);
4676
4677 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4678 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4679 I915_WRITE(MEMSWCTL, rgvswctl);
4680 POSTING_READ(MEMSWCTL);
4681
4682 rgvswctl |= MEMCTL_CMD_STS;
4683 I915_WRITE(MEMSWCTL, rgvswctl);
4684}
4685
4686void ironlake_disable_drps(struct drm_device *dev)
4687{
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4689 u32 rgvswctl;
4690 u8 fstart;
4691
4692 /* Ack interrupts, disable EFC interrupt */
4693 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4694 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4695 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4696 I915_WRITE(DEIIR, DE_PCU_EVENT);
4697 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4698
4699 /* Go back to the starting frequency */
4700 fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4701 MEMMODE_FSTART_SHIFT;
4702 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4703 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4704 I915_WRITE(MEMSWCTL, rgvswctl);
4705 msleep(1);
4706 rgvswctl |= MEMCTL_CMD_STS;
4707 I915_WRITE(MEMSWCTL, rgvswctl);
4708 msleep(1);
4709
4710}
4711
4252void intel_init_clock_gating(struct drm_device *dev) 4712void intel_init_clock_gating(struct drm_device *dev)
4253{ 4713{
4254 struct drm_i915_private *dev_priv = dev->dev_private; 4714 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4257,7 +4717,21 @@ void intel_init_clock_gating(struct drm_device *dev)
4257 * Disable clock gating reported to work incorrectly according to the 4717 * Disable clock gating reported to work incorrectly according to the
4258 * specs, but enable as much else as we can. 4718 * specs, but enable as much else as we can.
4259 */ 4719 */
4260 if (IS_IGDNG(dev)) { 4720 if (HAS_PCH_SPLIT(dev)) {
4721 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
4722
4723 if (IS_IRONLAKE(dev)) {
4724 /* Required for FBC */
4725 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
4726 /* Required for CxSR */
4727 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
4728
4729 I915_WRITE(PCH_3DCGDIS0,
4730 MARIUNIT_CLOCK_GATE_DISABLE |
4731 SVSMUNIT_CLOCK_GATE_DISABLE);
4732 }
4733
4734 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
4261 return; 4735 return;
4262 } else if (IS_G4X(dev)) { 4736 } else if (IS_G4X(dev)) {
4263 uint32_t dspclk_gate; 4737 uint32_t dspclk_gate;
@@ -4291,11 +4765,37 @@ void intel_init_clock_gating(struct drm_device *dev)
4291 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4765 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4292 DSTATE_DOT_CLOCK_GATING; 4766 DSTATE_DOT_CLOCK_GATING;
4293 I915_WRITE(D_STATE, dstate); 4767 I915_WRITE(D_STATE, dstate);
4294 } else if (IS_I855(dev) || IS_I865G(dev)) { 4768 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4295 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4769 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4296 } else if (IS_I830(dev)) { 4770 } else if (IS_I830(dev)) {
4297 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4771 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4298 } 4772 }
4773
4774 /*
4775 * GPU can automatically power down the render unit if given a page
4776 * to save state.
4777 */
4778 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4779 struct drm_i915_gem_object *obj_priv = NULL;
4780
4781 if (dev_priv->pwrctx) {
4782 obj_priv = to_intel_bo(dev_priv->pwrctx);
4783 } else {
4784 struct drm_gem_object *pwrctx;
4785
4786 pwrctx = intel_alloc_power_context(dev);
4787 if (pwrctx) {
4788 dev_priv->pwrctx = pwrctx;
4789 obj_priv = to_intel_bo(pwrctx);
4790 }
4791 }
4792
4793 if (obj_priv) {
4794 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4795 I915_WRITE(MCHBAR_RENDER_STANDBY,
4796 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4797 }
4798 }
4299} 4799}
4300 4800
4301/* Set up chip specific display functions */ 4801/* Set up chip specific display functions */
@@ -4304,8 +4804,8 @@ static void intel_init_display(struct drm_device *dev)
4304 struct drm_i915_private *dev_priv = dev->dev_private; 4804 struct drm_i915_private *dev_priv = dev->dev_private;
4305 4805
4306 /* We always want a DPMS function */ 4806 /* We always want a DPMS function */
4307 if (IS_IGDNG(dev)) 4807 if (HAS_PCH_SPLIT(dev))
4308 dev_priv->display.dpms = igdng_crtc_dpms; 4808 dev_priv->display.dpms = ironlake_crtc_dpms;
4309 else 4809 else
4310 dev_priv->display.dpms = i9xx_crtc_dpms; 4810 dev_priv->display.dpms = i9xx_crtc_dpms;
4311 4811
@@ -4315,7 +4815,7 @@ static void intel_init_display(struct drm_device *dev)
4315 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 4815 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4316 dev_priv->display.enable_fbc = g4x_enable_fbc; 4816 dev_priv->display.enable_fbc = g4x_enable_fbc;
4317 dev_priv->display.disable_fbc = g4x_disable_fbc; 4817 dev_priv->display.disable_fbc = g4x_disable_fbc;
4318 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) { 4818 } else if (IS_I965GM(dev)) {
4319 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 4819 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4320 dev_priv->display.enable_fbc = i8xx_enable_fbc; 4820 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4321 dev_priv->display.disable_fbc = i8xx_disable_fbc; 4821 dev_priv->display.disable_fbc = i8xx_disable_fbc;
@@ -4324,13 +4824,13 @@ static void intel_init_display(struct drm_device *dev)
4324 } 4824 }
4325 4825
4326 /* Returns the core display clock speed */ 4826 /* Returns the core display clock speed */
4327 if (IS_I945G(dev)) 4827 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4328 dev_priv->display.get_display_clock_speed = 4828 dev_priv->display.get_display_clock_speed =
4329 i945_get_display_clock_speed; 4829 i945_get_display_clock_speed;
4330 else if (IS_I915G(dev)) 4830 else if (IS_I915G(dev))
4331 dev_priv->display.get_display_clock_speed = 4831 dev_priv->display.get_display_clock_speed =
4332 i915_get_display_clock_speed; 4832 i915_get_display_clock_speed;
4333 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) 4833 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4334 dev_priv->display.get_display_clock_speed = 4834 dev_priv->display.get_display_clock_speed =
4335 i9xx_misc_get_display_clock_speed; 4835 i9xx_misc_get_display_clock_speed;
4336 else if (IS_I915GM(dev)) 4836 else if (IS_I915GM(dev))
@@ -4339,7 +4839,7 @@ static void intel_init_display(struct drm_device *dev)
4339 else if (IS_I865G(dev)) 4839 else if (IS_I865G(dev))
4340 dev_priv->display.get_display_clock_speed = 4840 dev_priv->display.get_display_clock_speed =
4341 i865_get_display_clock_speed; 4841 i865_get_display_clock_speed;
4342 else if (IS_I855(dev)) 4842 else if (IS_I85X(dev))
4343 dev_priv->display.get_display_clock_speed = 4843 dev_priv->display.get_display_clock_speed =
4344 i855_get_display_clock_speed; 4844 i855_get_display_clock_speed;
4345 else /* 852, 830 */ 4845 else /* 852, 830 */
@@ -4347,23 +4847,24 @@ static void intel_init_display(struct drm_device *dev)
4347 i830_get_display_clock_speed; 4847 i830_get_display_clock_speed;
4348 4848
4349 /* For FIFO watermark updates */ 4849 /* For FIFO watermark updates */
4350 if (IS_IGDNG(dev)) 4850 if (HAS_PCH_SPLIT(dev))
4351 dev_priv->display.update_wm = NULL; 4851 dev_priv->display.update_wm = NULL;
4352 else if (IS_G4X(dev)) 4852 else if (IS_G4X(dev))
4353 dev_priv->display.update_wm = g4x_update_wm; 4853 dev_priv->display.update_wm = g4x_update_wm;
4354 else if (IS_I965G(dev)) 4854 else if (IS_I965G(dev))
4355 dev_priv->display.update_wm = i965_update_wm; 4855 dev_priv->display.update_wm = i965_update_wm;
4356 else if (IS_I9XX(dev) || IS_MOBILE(dev)) { 4856 else if (IS_I9XX(dev)) {
4357 dev_priv->display.update_wm = i9xx_update_wm; 4857 dev_priv->display.update_wm = i9xx_update_wm;
4358 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 4858 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4859 } else if (IS_I85X(dev)) {
4860 dev_priv->display.update_wm = i9xx_update_wm;
4861 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4359 } else { 4862 } else {
4360 if (IS_I85X(dev)) 4863 dev_priv->display.update_wm = i830_update_wm;
4361 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 4864 if (IS_845G(dev))
4362 else if (IS_845G(dev))
4363 dev_priv->display.get_fifo_size = i845_get_fifo_size; 4865 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4364 else 4866 else
4365 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4867 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4366 dev_priv->display.update_wm = i830_update_wm;
4367 } 4868 }
4368} 4869}
4369 4870
@@ -4403,14 +4904,9 @@ void intel_modeset_init(struct drm_device *dev)
4403 num_pipe = 2; 4904 num_pipe = 2;
4404 else 4905 else
4405 num_pipe = 1; 4906 num_pipe = 1;
4406 DRM_DEBUG("%d display pipe%s available.\n", 4907 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4407 num_pipe, num_pipe > 1 ? "s" : ""); 4908 num_pipe, num_pipe > 1 ? "s" : "");
4408 4909
4409 if (IS_I85X(dev))
4410 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4411 else if (IS_I9XX(dev) || IS_G4X(dev))
4412 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4413
4414 for (i = 0; i < num_pipe; i++) { 4910 for (i = 0; i < num_pipe; i++) {
4415 intel_crtc_init(dev, i); 4911 intel_crtc_init(dev, i);
4416 } 4912 }
@@ -4419,9 +4915,21 @@ void intel_modeset_init(struct drm_device *dev)
4419 4915
4420 intel_init_clock_gating(dev); 4916 intel_init_clock_gating(dev);
4421 4917
4918 if (IS_IRONLAKE_M(dev))
4919 ironlake_enable_drps(dev);
4920
4422 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 4921 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4423 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 4922 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4424 (unsigned long)dev); 4923 (unsigned long)dev);
4924
4925 intel_setup_overlay(dev);
4926
4927 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4928 dev_priv->fsb_freq,
4929 dev_priv->mem_freq))
4930 DRM_INFO("failed to find known CxSR latency "
4931 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4932 dev_priv->fsb_freq, dev_priv->mem_freq);
4425} 4933}
4426 4934
4427void intel_modeset_cleanup(struct drm_device *dev) 4935void intel_modeset_cleanup(struct drm_device *dev)
@@ -4442,14 +4950,26 @@ void intel_modeset_cleanup(struct drm_device *dev)
4442 del_timer_sync(&intel_crtc->idle_timer); 4950 del_timer_sync(&intel_crtc->idle_timer);
4443 } 4951 }
4444 4952
4445 intel_increase_renderclock(dev, false);
4446 del_timer_sync(&dev_priv->idle_timer); 4953 del_timer_sync(&dev_priv->idle_timer);
4447 4954
4448 mutex_unlock(&dev->struct_mutex);
4449
4450 if (dev_priv->display.disable_fbc) 4955 if (dev_priv->display.disable_fbc)
4451 dev_priv->display.disable_fbc(dev); 4956 dev_priv->display.disable_fbc(dev);
4452 4957
4958 if (dev_priv->pwrctx) {
4959 struct drm_i915_gem_object *obj_priv;
4960
4961 obj_priv = to_intel_bo(dev_priv->pwrctx);
4962 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4963 I915_READ(PWRCTXA);
4964 i915_gem_object_unpin(dev_priv->pwrctx);
4965 drm_gem_object_unreference(dev_priv->pwrctx);
4966 }
4967
4968 if (IS_IRONLAKE_M(dev))
4969 ironlake_disable_drps(dev);
4970
4971 mutex_unlock(&dev->struct_mutex);
4972
4453 drm_mode_config_cleanup(dev); 4973 drm_mode_config_cleanup(dev);
4454} 4974}
4455 4975
@@ -4459,9 +4979,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
4459*/ 4979*/
4460struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 4980struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4461{ 4981{
4462 struct intel_output *intel_output = to_intel_output(connector); 4982 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4463 4983
4464 return &intel_output->enc; 4984 return &intel_encoder->enc;
4465} 4985}
4466 4986
4467/* 4987/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-13 06:53:56 -0400