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path: root/drivers/gpu/drm/i915/intel_crt.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c48
1 files changed, 26 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9293878ec7eb..32a3693905ec 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -88,7 +88,7 @@ static void intel_disable_crt(struct intel_encoder *encoder)
88 u32 temp; 88 u32 temp;
89 89
90 temp = I915_READ(crt->adpa_reg); 90 temp = I915_READ(crt->adpa_reg);
91 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 91 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
92 temp &= ~ADPA_DAC_ENABLE; 92 temp &= ~ADPA_DAC_ENABLE;
93 I915_WRITE(crt->adpa_reg, temp); 93 I915_WRITE(crt->adpa_reg, temp);
94} 94}
@@ -267,27 +267,27 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
267 267
268 crt->force_hotplug_required = 0; 268 crt->force_hotplug_required = 0;
269 269
270 save_adpa = adpa = I915_READ(PCH_ADPA); 270 save_adpa = adpa = I915_READ(crt->adpa_reg);
271 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 271 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
272 272
273 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 273 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
274 if (turn_off_dac) 274 if (turn_off_dac)
275 adpa &= ~ADPA_DAC_ENABLE; 275 adpa &= ~ADPA_DAC_ENABLE;
276 276
277 I915_WRITE(PCH_ADPA, adpa); 277 I915_WRITE(crt->adpa_reg, adpa);
278 278
279 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 279 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
280 1000)) 280 1000))
281 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 281 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
282 282
283 if (turn_off_dac) { 283 if (turn_off_dac) {
284 I915_WRITE(PCH_ADPA, save_adpa); 284 I915_WRITE(crt->adpa_reg, save_adpa);
285 POSTING_READ(PCH_ADPA); 285 POSTING_READ(crt->adpa_reg);
286 } 286 }
287 } 287 }
288 288
289 /* Check the status to see if both blue and green are on now */ 289 /* Check the status to see if both blue and green are on now */
290 adpa = I915_READ(PCH_ADPA); 290 adpa = I915_READ(crt->adpa_reg);
291 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 291 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
292 ret = true; 292 ret = true;
293 else 293 else
@@ -300,26 +300,27 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
300static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 300static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
301{ 301{
302 struct drm_device *dev = connector->dev; 302 struct drm_device *dev = connector->dev;
303 struct intel_crt *crt = intel_attached_crt(connector);
303 struct drm_i915_private *dev_priv = dev->dev_private; 304 struct drm_i915_private *dev_priv = dev->dev_private;
304 u32 adpa; 305 u32 adpa;
305 bool ret; 306 bool ret;
306 u32 save_adpa; 307 u32 save_adpa;
307 308
308 save_adpa = adpa = I915_READ(ADPA); 309 save_adpa = adpa = I915_READ(crt->adpa_reg);
309 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 310 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
310 311
311 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 312 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
312 313
313 I915_WRITE(ADPA, adpa); 314 I915_WRITE(crt->adpa_reg, adpa);
314 315
315 if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 316 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
316 1000)) { 317 1000)) {
317 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 318 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
318 I915_WRITE(ADPA, save_adpa); 319 I915_WRITE(crt->adpa_reg, save_adpa);
319 } 320 }
320 321
321 /* Check the status to see if both blue and green are on now */ 322 /* Check the status to see if both blue and green are on now */
322 adpa = I915_READ(ADPA); 323 adpa = I915_READ(crt->adpa_reg);
323 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 324 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
324 ret = true; 325 ret = true;
325 else 326 else
@@ -665,11 +666,11 @@ static void intel_crt_reset(struct drm_connector *connector)
665 if (HAS_PCH_SPLIT(dev)) { 666 if (HAS_PCH_SPLIT(dev)) {
666 u32 adpa; 667 u32 adpa;
667 668
668 adpa = I915_READ(PCH_ADPA); 669 adpa = I915_READ(crt->adpa_reg);
669 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 670 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
670 adpa |= ADPA_HOTPLUG_BITS; 671 adpa |= ADPA_HOTPLUG_BITS;
671 I915_WRITE(PCH_ADPA, adpa); 672 I915_WRITE(crt->adpa_reg, adpa);
672 POSTING_READ(PCH_ADPA); 673 POSTING_READ(crt->adpa_reg);
673 674
674 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); 675 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
675 crt->force_hotplug_required = 1; 676 crt->force_hotplug_required = 1;
@@ -684,7 +685,6 @@ static void intel_crt_reset(struct drm_connector *connector)
684static const struct drm_encoder_helper_funcs crt_encoder_funcs = { 685static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
685 .mode_fixup = intel_crt_mode_fixup, 686 .mode_fixup = intel_crt_mode_fixup,
686 .mode_set = intel_crt_mode_set, 687 .mode_set = intel_crt_mode_set,
687 .disable = intel_encoder_noop,
688}; 688};
689 689
690static const struct drm_connector_funcs intel_crt_connector_funcs = { 690static const struct drm_connector_funcs intel_crt_connector_funcs = {
@@ -776,7 +776,7 @@ void intel_crt_init(struct drm_device *dev)
776 776
777 crt->base.disable = intel_disable_crt; 777 crt->base.disable = intel_disable_crt;
778 crt->base.enable = intel_enable_crt; 778 crt->base.enable = intel_enable_crt;
779 if (IS_HASWELL(dev)) 779 if (HAS_DDI(dev))
780 crt->base.get_hw_state = intel_ddi_get_hw_state; 780 crt->base.get_hw_state = intel_ddi_get_hw_state;
781 else 781 else
782 crt->base.get_hw_state = intel_crt_get_hw_state; 782 crt->base.get_hw_state = intel_crt_get_hw_state;
@@ -800,10 +800,14 @@ void intel_crt_init(struct drm_device *dev)
800 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; 800 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
801 801
802 /* 802 /*
803 * TODO: find a proper way to discover whether we need to set the 803 * TODO: find a proper way to discover whether we need to set the the
804 * polarity reversal bit or not, instead of relying on the BIOS. 804 * polarity and link reversal bits or not, instead of relying on the
805 * BIOS.
805 */ 806 */
806 if (HAS_PCH_LPT(dev)) 807 if (HAS_PCH_LPT(dev)) {
807 dev_priv->fdi_rx_polarity_reversed = 808 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
808 !!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT); 809 FDI_RX_LINK_REVERSAL_OVERRIDE;
810
811 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
812 }
809} 813}