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path: root/drivers/gpu/drm/i915/i915_suspend.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c592
1 files changed, 305 insertions, 287 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 31f08581e93a..5257cfc34c35 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,11 +34,10 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 35 u32 dpll_reg;
36 36
37 if (HAS_PCH_SPLIT(dev)) { 37 if (HAS_PCH_SPLIT(dev))
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 38 dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;
39 } else { 39 else
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; 40 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
41 }
42 41
43 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); 42 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
44} 43}
@@ -46,7 +45,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
46static void i915_save_palette(struct drm_device *dev, enum pipe pipe) 45static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
47{ 46{
48 struct drm_i915_private *dev_priv = dev->dev_private; 47 struct drm_i915_private *dev_priv = dev->dev_private;
49 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 48 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
50 u32 *array; 49 u32 *array;
51 int i; 50 int i;
52 51
@@ -54,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
54 return; 53 return;
55 54
56 if (HAS_PCH_SPLIT(dev)) 55 if (HAS_PCH_SPLIT(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 56 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
58 57
59 if (pipe == PIPE_A) 58 if (pipe == PIPE_A)
60 array = dev_priv->save_palette_a; 59 array = dev_priv->save_palette_a;
@@ -68,7 +67,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
68static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) 67static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
69{ 68{
70 struct drm_i915_private *dev_priv = dev->dev_private; 69 struct drm_i915_private *dev_priv = dev->dev_private;
71 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 70 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
72 u32 *array; 71 u32 *array;
73 int i; 72 int i;
74 73
@@ -76,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76 return; 75 return;
77 76
78 if (HAS_PCH_SPLIT(dev)) 77 if (HAS_PCH_SPLIT(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 78 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
80 79
81 if (pipe == PIPE_A) 80 if (pipe == PIPE_A)
82 array = dev_priv->save_palette_a; 81 array = dev_priv->save_palette_a;
@@ -235,128 +234,161 @@ static void i915_restore_vga(struct drm_device *dev)
235static void i915_save_modeset_reg(struct drm_device *dev) 234static void i915_save_modeset_reg(struct drm_device *dev)
236{ 235{
237 struct drm_i915_private *dev_priv = dev->dev_private; 236 struct drm_i915_private *dev_priv = dev->dev_private;
237 int i;
238 238
239 if (drm_core_check_feature(dev, DRIVER_MODESET)) 239 if (drm_core_check_feature(dev, DRIVER_MODESET))
240 return; 240 return;
241 241
242 /* Cursor state */
243 dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
244 dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
245 dev_priv->saveCURABASE = I915_READ(_CURABASE);
246 dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
247 dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
248 dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
249 if (IS_GEN2(dev))
250 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
251
242 if (HAS_PCH_SPLIT(dev)) { 252 if (HAS_PCH_SPLIT(dev)) {
243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); 253 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); 254 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
245 } 255 }
246 256
247 /* Pipe & plane A info */ 257 /* Pipe & plane A info */
248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 258 dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 259 dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
250 if (HAS_PCH_SPLIT(dev)) { 260 if (HAS_PCH_SPLIT(dev)) {
251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 261 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 262 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); 263 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
254 } else { 264 } else {
255 dev_priv->saveFPA0 = I915_READ(FPA0); 265 dev_priv->saveFPA0 = I915_READ(_FPA0);
256 dev_priv->saveFPA1 = I915_READ(FPA1); 266 dev_priv->saveFPA1 = I915_READ(_FPA1);
257 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 267 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
258 } 268 }
259 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 269 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 270 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 271 dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 272 dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
263 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); 273 dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 274 dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 275 dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 276 dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
267 if (!HAS_PCH_SPLIT(dev)) 277 if (!HAS_PCH_SPLIT(dev))
268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 278 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
269 279
270 if (HAS_PCH_SPLIT(dev)) { 280 if (HAS_PCH_SPLIT(dev)) {
271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1); 281 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1); 282 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1); 283 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
274 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1); 284 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
275 285
276 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL); 286 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
277 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL); 287 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
278 288
279 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1); 289 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
280 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ); 290 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
281 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS); 291 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
282 292
283 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF); 293 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
284 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A); 294 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
285 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A); 295 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
286 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A); 296 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
287 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A); 297 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
288 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A); 298 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
289 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A); 299 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
290 } 300 }
291 301
292 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 302 dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
293 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 303 dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
294 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 304 dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
295 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 305 dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
296 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); 306 dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
297 if (IS_I965G(dev)) { 307 if (INTEL_INFO(dev)->gen >= 4) {
298 dev_priv->saveDSPASURF = I915_READ(DSPASURF); 308 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
299 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 309 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
300 } 310 }
301 i915_save_palette(dev, PIPE_A); 311 i915_save_palette(dev, PIPE_A);
302 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); 312 dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
303 313
304 /* Pipe & plane B info */ 314 /* Pipe & plane B info */
305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 315 dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 316 dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
307 if (HAS_PCH_SPLIT(dev)) { 317 if (HAS_PCH_SPLIT(dev)) {
308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 318 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 319 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); 320 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
311 } else { 321 } else {
312 dev_priv->saveFPB0 = I915_READ(FPB0); 322 dev_priv->saveFPB0 = I915_READ(_FPB0);
313 dev_priv->saveFPB1 = I915_READ(FPB1); 323 dev_priv->saveFPB1 = I915_READ(_FPB1);
314 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 324 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
315 } 325 }
316 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 326 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 327 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 328 dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 329 dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
320 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); 330 dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 331 dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 332 dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 333 dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
324 if (!HAS_PCH_SPLIT(dev)) 334 if (!HAS_PCH_SPLIT(dev))
325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 335 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
326 336
327 if (HAS_PCH_SPLIT(dev)) { 337 if (HAS_PCH_SPLIT(dev)) {
328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1); 338 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1); 339 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1); 340 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
331 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1); 341 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
332 342
333 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL); 343 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
334 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL); 344 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
335 345
336 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1); 346 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
337 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ); 347 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
338 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS); 348 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
339 349
340 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF); 350 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
341 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B); 351 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
342 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B); 352 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
343 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B); 353 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
344 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B); 354 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
345 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B); 355 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
346 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B); 356 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
347 } 357 }
348 358
349 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 359 dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
350 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 360 dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
351 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 361 dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
352 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 362 dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
353 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); 363 dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
354 if (IS_I965GM(dev) || IS_GM45(dev)) { 364 if (INTEL_INFO(dev)->gen >= 4) {
355 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 365 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
356 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 366 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
357 } 367 }
358 i915_save_palette(dev, PIPE_B); 368 i915_save_palette(dev, PIPE_B);
359 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 369 dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
370
371 /* Fences */
372 switch (INTEL_INFO(dev)->gen) {
373 case 6:
374 for (i = 0; i < 16; i++)
375 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
376 break;
377 case 5:
378 case 4:
379 for (i = 0; i < 16; i++)
380 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
381 break;
382 case 3:
383 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
384 for (i = 0; i < 8; i++)
385 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
386 case 2:
387 for (i = 0; i < 8; i++)
388 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
389 break;
390 }
391
360 return; 392 return;
361} 393}
362 394
@@ -365,24 +397,47 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
365 struct drm_i915_private *dev_priv = dev->dev_private; 397 struct drm_i915_private *dev_priv = dev->dev_private;
366 int dpll_a_reg, fpa0_reg, fpa1_reg; 398 int dpll_a_reg, fpa0_reg, fpa1_reg;
367 int dpll_b_reg, fpb0_reg, fpb1_reg; 399 int dpll_b_reg, fpb0_reg, fpb1_reg;
400 int i;
368 401
369 if (drm_core_check_feature(dev, DRIVER_MODESET)) 402 if (drm_core_check_feature(dev, DRIVER_MODESET))
370 return; 403 return;
371 404
405 /* Fences */
406 switch (INTEL_INFO(dev)->gen) {
407 case 6:
408 for (i = 0; i < 16; i++)
409 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
410 break;
411 case 5:
412 case 4:
413 for (i = 0; i < 16; i++)
414 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
415 break;
416 case 3:
417 case 2:
418 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
419 for (i = 0; i < 8; i++)
420 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
421 for (i = 0; i < 8; i++)
422 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
423 break;
424 }
425
426
372 if (HAS_PCH_SPLIT(dev)) { 427 if (HAS_PCH_SPLIT(dev)) {
373 dpll_a_reg = PCH_DPLL_A; 428 dpll_a_reg = _PCH_DPLL_A;
374 dpll_b_reg = PCH_DPLL_B; 429 dpll_b_reg = _PCH_DPLL_B;
375 fpa0_reg = PCH_FPA0; 430 fpa0_reg = _PCH_FPA0;
376 fpb0_reg = PCH_FPB0; 431 fpb0_reg = _PCH_FPB0;
377 fpa1_reg = PCH_FPA1; 432 fpa1_reg = _PCH_FPA1;
378 fpb1_reg = PCH_FPB1; 433 fpb1_reg = _PCH_FPB1;
379 } else { 434 } else {
380 dpll_a_reg = DPLL_A; 435 dpll_a_reg = _DPLL_A;
381 dpll_b_reg = DPLL_B; 436 dpll_b_reg = _DPLL_B;
382 fpa0_reg = FPA0; 437 fpa0_reg = _FPA0;
383 fpb0_reg = FPB0; 438 fpb0_reg = _FPB0;
384 fpa1_reg = FPA1; 439 fpa1_reg = _FPA1;
385 fpb1_reg = FPB1; 440 fpb1_reg = _FPB1;
386 } 441 }
387 442
388 if (HAS_PCH_SPLIT(dev)) { 443 if (HAS_PCH_SPLIT(dev)) {
@@ -404,61 +459,61 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 459 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
405 POSTING_READ(dpll_a_reg); 460 POSTING_READ(dpll_a_reg);
406 udelay(150); 461 udelay(150);
407 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { 462 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 463 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
409 POSTING_READ(DPLL_A_MD); 464 POSTING_READ(_DPLL_A_MD);
410 } 465 }
411 udelay(150); 466 udelay(150);
412 467
413 /* Restore mode */ 468 /* Restore mode */
414 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 469 I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
415 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); 470 I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
416 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); 471 I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
417 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 472 I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
418 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 473 I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
419 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 474 I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
420 if (!HAS_PCH_SPLIT(dev)) 475 if (!HAS_PCH_SPLIT(dev))
421 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 476 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
422 477
423 if (HAS_PCH_SPLIT(dev)) { 478 if (HAS_PCH_SPLIT(dev)) {
424 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 479 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
425 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 480 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
426 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); 481 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
427 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1); 482 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
428 483
429 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); 484 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
430 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); 485 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
431 486
432 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1); 487 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
433 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); 488 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
434 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS); 489 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
435 490
436 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF); 491 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
437 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); 492 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
438 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); 493 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
439 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); 494 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
440 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); 495 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
441 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); 496 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
442 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); 497 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
443 } 498 }
444 499
445 /* Restore plane info */ 500 /* Restore plane info */
446 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 501 I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
447 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 502 I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
448 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 503 I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
449 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); 504 I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
450 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 505 I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
451 if (IS_I965G(dev)) { 506 if (INTEL_INFO(dev)->gen >= 4) {
452 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 507 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
453 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); 508 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
454 } 509 }
455 510
456 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); 511 I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
457 512
458 i915_restore_palette(dev, PIPE_A); 513 i915_restore_palette(dev, PIPE_A);
459 /* Enable the plane */ 514 /* Enable the plane */
460 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 515 I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
461 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); 516 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
462 517
463 /* Pipe & plane B info */ 518 /* Pipe & plane B info */
464 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 519 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
@@ -473,66 +528,76 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
473 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); 528 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
474 POSTING_READ(dpll_b_reg); 529 POSTING_READ(dpll_b_reg);
475 udelay(150); 530 udelay(150);
476 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { 531 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
477 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 532 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
478 POSTING_READ(DPLL_B_MD); 533 POSTING_READ(_DPLL_B_MD);
479 } 534 }
480 udelay(150); 535 udelay(150);
481 536
482 /* Restore mode */ 537 /* Restore mode */
483 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 538 I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
484 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); 539 I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
485 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); 540 I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
486 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 541 I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
487 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 542 I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
488 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 543 I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
489 if (!HAS_PCH_SPLIT(dev)) 544 if (!HAS_PCH_SPLIT(dev))
490 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 545 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
491 546
492 if (HAS_PCH_SPLIT(dev)) { 547 if (HAS_PCH_SPLIT(dev)) {
493 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 548 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
494 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 549 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
495 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); 550 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
496 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1); 551 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
497 552
498 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); 553 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
499 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); 554 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
500 555
501 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1); 556 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
502 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); 557 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
503 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS); 558 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
504 559
505 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF); 560 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
506 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); 561 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
507 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); 562 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
508 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); 563 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
509 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); 564 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
510 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); 565 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
511 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); 566 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
512 } 567 }
513 568
514 /* Restore plane info */ 569 /* Restore plane info */
515 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 570 I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
516 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 571 I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
517 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 572 I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
518 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); 573 I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
519 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 574 I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
520 if (IS_I965G(dev)) { 575 if (INTEL_INFO(dev)->gen >= 4) {
521 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 576 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
522 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 577 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
523 } 578 }
524 579
525 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); 580 I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
526 581
527 i915_restore_palette(dev, PIPE_B); 582 i915_restore_palette(dev, PIPE_B);
528 /* Enable the plane */ 583 /* Enable the plane */
529 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 584 I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
530 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 585 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
586
587 /* Cursor state */
588 I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
589 I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
590 I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
591 I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
592 I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
593 I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
594 if (IS_GEN2(dev))
595 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
531 596
532 return; 597 return;
533} 598}
534 599
535void i915_save_display(struct drm_device *dev) 600static void i915_save_display(struct drm_device *dev)
536{ 601{
537 struct drm_i915_private *dev_priv = dev->dev_private; 602 struct drm_i915_private *dev_priv = dev->dev_private;
538 603
@@ -543,16 +608,6 @@ void i915_save_display(struct drm_device *dev)
543 /* Don't save them in KMS mode */ 608 /* Don't save them in KMS mode */
544 i915_save_modeset_reg(dev); 609 i915_save_modeset_reg(dev);
545 610
546 /* Cursor state */
547 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
548 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
549 dev_priv->saveCURABASE = I915_READ(CURABASE);
550 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
551 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
552 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
553 if (!IS_I9XX(dev))
554 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
555
556 /* CRT state */ 611 /* CRT state */
557 if (HAS_PCH_SPLIT(dev)) { 612 if (HAS_PCH_SPLIT(dev)) {
558 dev_priv->saveADPA = I915_READ(PCH_ADPA); 613 dev_priv->saveADPA = I915_READ(PCH_ADPA);
@@ -573,7 +628,7 @@ void i915_save_display(struct drm_device *dev)
573 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 628 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
574 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 629 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
575 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); 630 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
576 if (IS_I965G(dev)) 631 if (INTEL_INFO(dev)->gen >= 4)
577 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 632 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
578 if (IS_MOBILE(dev) && !IS_I830(dev)) 633 if (IS_MOBILE(dev) && !IS_I830(dev))
579 dev_priv->saveLVDS = I915_READ(LVDS); 634 dev_priv->saveLVDS = I915_READ(LVDS);
@@ -597,14 +652,14 @@ void i915_save_display(struct drm_device *dev)
597 dev_priv->saveDP_B = I915_READ(DP_B); 652 dev_priv->saveDP_B = I915_READ(DP_B);
598 dev_priv->saveDP_C = I915_READ(DP_C); 653 dev_priv->saveDP_C = I915_READ(DP_C);
599 dev_priv->saveDP_D = I915_READ(DP_D); 654 dev_priv->saveDP_D = I915_READ(DP_D);
600 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M); 655 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
601 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M); 656 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
602 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N); 657 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
603 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N); 658 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
604 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M); 659 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
605 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M); 660 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
606 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N); 661 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
607 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N); 662 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
608 } 663 }
609 /* FIXME: save TV & SDVO state */ 664 /* FIXME: save TV & SDVO state */
610 665
@@ -634,7 +689,7 @@ void i915_save_display(struct drm_device *dev)
634 i915_save_vga(dev); 689 i915_save_vga(dev);
635} 690}
636 691
637void i915_restore_display(struct drm_device *dev) 692static void i915_restore_display(struct drm_device *dev)
638{ 693{
639 struct drm_i915_private *dev_priv = dev->dev_private; 694 struct drm_i915_private *dev_priv = dev->dev_private;
640 695
@@ -643,30 +698,20 @@ void i915_restore_display(struct drm_device *dev)
643 698
644 /* Display port ratios (must be done before clock is set) */ 699 /* Display port ratios (must be done before clock is set) */
645 if (SUPPORTS_INTEGRATED_DP(dev)) { 700 if (SUPPORTS_INTEGRATED_DP(dev)) {
646 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M); 701 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
647 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M); 702 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
648 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N); 703 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
649 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N); 704 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
650 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M); 705 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
651 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M); 706 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
652 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N); 707 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
653 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N); 708 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
654 } 709 }
655 710
656 /* This is only meaningful in non-KMS mode */ 711 /* This is only meaningful in non-KMS mode */
657 /* Don't restore them in KMS mode */ 712 /* Don't restore them in KMS mode */
658 i915_restore_modeset_reg(dev); 713 i915_restore_modeset_reg(dev);
659 714
660 /* Cursor state */
661 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
662 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
663 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
664 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
665 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
666 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
667 if (!IS_I9XX(dev))
668 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
669
670 /* CRT state */ 715 /* CRT state */
671 if (HAS_PCH_SPLIT(dev)) 716 if (HAS_PCH_SPLIT(dev))
672 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 717 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
@@ -674,7 +719,7 @@ void i915_restore_display(struct drm_device *dev)
674 I915_WRITE(ADPA, dev_priv->saveADPA); 719 I915_WRITE(ADPA, dev_priv->saveADPA);
675 720
676 /* LVDS state */ 721 /* LVDS state */
677 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 722 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
678 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 723 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
679 724
680 if (HAS_PCH_SPLIT(dev)) { 725 if (HAS_PCH_SPLIT(dev)) {
@@ -694,7 +739,7 @@ void i915_restore_display(struct drm_device *dev)
694 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 739 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
695 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); 740 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
696 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); 741 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
697 I915_WRITE(MCHBAR_RENDER_STANDBY, 742 I915_WRITE(RSTDBYCTL,
698 dev_priv->saveMCHBAR_RENDER_STANDBY); 743 dev_priv->saveMCHBAR_RENDER_STANDBY);
699 } else { 744 } else {
700 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 745 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
@@ -735,6 +780,7 @@ void i915_restore_display(struct drm_device *dev)
735 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 780 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
736 else 781 else
737 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 782 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
783
738 I915_WRITE(VGA0, dev_priv->saveVGA0); 784 I915_WRITE(VGA0, dev_priv->saveVGA0);
739 I915_WRITE(VGA1, dev_priv->saveVGA1); 785 I915_WRITE(VGA1, dev_priv->saveVGA1);
740 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 786 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@ -751,6 +797,8 @@ int i915_save_state(struct drm_device *dev)
751 797
752 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 798 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
753 799
800 mutex_lock(&dev->struct_mutex);
801
754 /* Hardware status page */ 802 /* Hardware status page */
755 dev_priv->saveHWS = I915_READ(HWS_PGA); 803 dev_priv->saveHWS = I915_READ(HWS_PGA);
756 804
@@ -762,17 +810,19 @@ int i915_save_state(struct drm_device *dev)
762 dev_priv->saveDEIMR = I915_READ(DEIMR); 810 dev_priv->saveDEIMR = I915_READ(DEIMR);
763 dev_priv->saveGTIER = I915_READ(GTIER); 811 dev_priv->saveGTIER = I915_READ(GTIER);
764 dev_priv->saveGTIMR = I915_READ(GTIMR); 812 dev_priv->saveGTIMR = I915_READ(GTIMR);
765 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); 813 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
766 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); 814 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
767 dev_priv->saveMCHBAR_RENDER_STANDBY = 815 dev_priv->saveMCHBAR_RENDER_STANDBY =
768 I915_READ(MCHBAR_RENDER_STANDBY); 816 I915_READ(RSTDBYCTL);
769 } else { 817 } else {
770 dev_priv->saveIER = I915_READ(IER); 818 dev_priv->saveIER = I915_READ(IER);
771 dev_priv->saveIMR = I915_READ(IMR); 819 dev_priv->saveIMR = I915_READ(IMR);
772 } 820 }
773 821
774 if (HAS_PCH_SPLIT(dev)) 822 if (IS_IRONLAKE_M(dev))
775 ironlake_disable_drps(dev); 823 ironlake_disable_drps(dev);
824 if (IS_GEN6(dev))
825 gen6_disable_rps(dev);
776 826
777 /* Cache mode state */ 827 /* Cache mode state */
778 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 828 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -788,27 +838,7 @@ int i915_save_state(struct drm_device *dev)
788 for (i = 0; i < 3; i++) 838 for (i = 0; i < 3; i++)
789 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 839 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
790 840
791 /* Fences */ 841 mutex_unlock(&dev->struct_mutex);
792 switch (INTEL_INFO(dev)->gen) {
793 case 6:
794 for (i = 0; i < 16; i++)
795 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
796 break;
797 case 5:
798 case 4:
799 for (i = 0; i < 16; i++)
800 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
801 break;
802 case 3:
803 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
804 for (i = 0; i < 8; i++)
805 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
806 case 2:
807 for (i = 0; i < 8; i++)
808 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
809 break;
810
811 }
812 842
813 return 0; 843 return 0;
814} 844}
@@ -820,30 +850,11 @@ int i915_restore_state(struct drm_device *dev)
820 850
821 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 851 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
822 852
853 mutex_lock(&dev->struct_mutex);
854
823 /* Hardware status page */ 855 /* Hardware status page */
824 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 856 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
825 857
826 /* Fences */
827 switch (INTEL_INFO(dev)->gen) {
828 case 6:
829 for (i = 0; i < 16; i++)
830 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
831 break;
832 case 5:
833 case 4:
834 for (i = 0; i < 16; i++)
835 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
836 break;
837 case 3:
838 case 2:
839 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
840 for (i = 0; i < 8; i++)
841 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
842 for (i = 0; i < 8; i++)
843 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
844 break;
845 }
846
847 i915_restore_display(dev); 858 i915_restore_display(dev);
848 859
849 /* Interrupt state */ 860 /* Interrupt state */
@@ -852,18 +863,25 @@ int i915_restore_state(struct drm_device *dev)
852 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 863 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
853 I915_WRITE(GTIER, dev_priv->saveGTIER); 864 I915_WRITE(GTIER, dev_priv->saveGTIER);
854 I915_WRITE(GTIMR, dev_priv->saveGTIMR); 865 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
855 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); 866 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
856 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); 867 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
857 } else { 868 } else {
858 I915_WRITE (IER, dev_priv->saveIER); 869 I915_WRITE(IER, dev_priv->saveIER);
859 I915_WRITE (IMR, dev_priv->saveIMR); 870 I915_WRITE(IMR, dev_priv->saveIMR);
860 } 871 }
872 mutex_unlock(&dev->struct_mutex);
861 873
862 /* Clock gating state */
863 intel_init_clock_gating(dev); 874 intel_init_clock_gating(dev);
864 875
865 if (HAS_PCH_SPLIT(dev)) 876 if (IS_IRONLAKE_M(dev)) {
866 ironlake_enable_drps(dev); 877 ironlake_enable_drps(dev);
878 intel_init_emon(dev);
879 }
880
881 if (IS_GEN6(dev))
882 gen6_enable_rps(dev_priv);
883
884 mutex_lock(&dev->struct_mutex);
867 885
868 /* Cache mode state */ 886 /* Cache mode state */
869 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 887 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
@@ -878,9 +896,9 @@ int i915_restore_state(struct drm_device *dev)
878 for (i = 0; i < 3; i++) 896 for (i = 0; i < 3; i++)
879 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 897 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
880 898
881 /* I2C state */ 899 mutex_unlock(&dev->struct_mutex);
882 intel_i2c_reset_gmbus(dev); 900
901 intel_i2c_reset(dev);
883 902
884 return 0; 903 return 0;
885} 904}
886
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 16:57:40 -0400