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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c159e1a6810f..ef9b35479f01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -604,6 +604,10 @@
604#define ARB_MODE_SWIZZLE_IVB (1<<5) 604#define ARB_MODE_SWIZZLE_IVB (1<<5)
605#define RENDER_HWS_PGA_GEN7 (0x04080) 605#define RENDER_HWS_PGA_GEN7 (0x04080)
606#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 606#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
607#define RING_FAULT_GTTSEL_MASK (1<<11)
608#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
609#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
610#define RING_FAULT_VALID (1<<0)
607#define DONE_REG 0x40b0 611#define DONE_REG 0x40b0
608#define BSD_HWS_PGA_GEN7 (0x04180) 612#define BSD_HWS_PGA_GEN7 (0x04180)
609#define BLT_HWS_PGA_GEN7 (0x04280) 613#define BLT_HWS_PGA_GEN7 (0x04280)
@@ -3881,6 +3885,9 @@
3881#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3885#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3882#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3886#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3883 3887
3888#define HSW_SCRATCH1 0xb038
3889#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
3890
3884#define HSW_FUSE_STRAP 0x42014 3891#define HSW_FUSE_STRAP 0x42014
3885#define HSW_CDCLK_LIMIT (1 << 24) 3892#define HSW_CDCLK_LIMIT (1 << 24)
3886 3893
@@ -4276,7 +4283,9 @@
4276#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 4283#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4277 4284
4278#define SOUTH_DSPCLK_GATE_D 0xc2020 4285#define SOUTH_DSPCLK_GATE_D 0xc2020
4286#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
4279#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 4287#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4288#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
4280#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 4289#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
4281 4290
4282/* CPU: FDI_TX */ 4291/* CPU: FDI_TX */
@@ -4728,6 +4737,9 @@
4728#define GEN7_ROW_CHICKEN2_GT2 0xf4f4 4737#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
4729#define DOP_CLOCK_GATING_DISABLE (1<<0) 4738#define DOP_CLOCK_GATING_DISABLE (1<<0)
4730 4739
4740#define HSW_ROW_CHICKEN3 0xe49c
4741#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
4742
4731#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) 4743#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
4732#define INTEL_AUDIO_DEVCL 0x808629FB 4744#define INTEL_AUDIO_DEVCL 0x808629FB
4733#define INTEL_AUDIO_DEVBLC 0x80862801 4745#define INTEL_AUDIO_DEVBLC 0x80862801