1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d675d79efd48..6f6eed169630 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -243,14 +243,20 @@
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
 #define GFX_OP_PIPE_CONTROL(len)        ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
+#define   PIPE_CONTROL_CS_STALL                         (1<<20)
 #define   PIPE_CONTROL_QW_WRITE                         (1<<14)
 #define   PIPE_CONTROL_DEPTH_STALL                      (1<<13)
 #define   PIPE_CONTROL_WRITE_FLUSH                      (1<<12)
+#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH        (1<<12) /* gen6+ */
 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE     (1<<11) /* MBZ on Ironlake */
 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE         (1<<10) /* GM45+ only */
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE           (1<<9)
 #define   PIPE_CONTROL_NOTIFY                           (1<<8)
+#define   PIPE_CONTROL_VF_CACHE_INVALIDATE              (1<<4)
+#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE           (1<<3)
+#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE           (1<<2)
 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD              (1<<1)
+#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH                (1<<0)
 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */