diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 30 |
1 files changed, 26 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b080cc824001..a26d5b0a3690 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3303,10 +3303,10 @@ | |||
3303 | /* or SDVOB */ | 3303 | /* or SDVOB */ |
3304 | #define HDMIB 0xe1140 | 3304 | #define HDMIB 0xe1140 |
3305 | #define PORT_ENABLE (1 << 31) | 3305 | #define PORT_ENABLE (1 << 31) |
3306 | #define TRANSCODER_A (0) | 3306 | #define TRANSCODER(pipe) ((pipe) << 30) |
3307 | #define TRANSCODER_B (1 << 30) | 3307 | #define TRANSCODER_CPT(pipe) ((pipe) << 29) |
3308 | #define TRANSCODER(pipe) ((pipe) << 30) | 3308 | #define TRANSCODER_MASK (1 << 30) |
3309 | #define TRANSCODER_MASK (1 << 30) | 3309 | #define TRANSCODER_MASK_CPT (3 << 29) |
3310 | #define COLOR_FORMAT_8bpc (0) | 3310 | #define COLOR_FORMAT_8bpc (0) |
3311 | #define COLOR_FORMAT_12bpc (3 << 26) | 3311 | #define COLOR_FORMAT_12bpc (3 << 26) |
3312 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) | 3312 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) |
@@ -3447,8 +3447,30 @@ | |||
3447 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) | 3447 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) |
3448 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) | 3448 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
3449 | 3449 | ||
3450 | /* IVB */ | ||
3451 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) | ||
3452 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) | ||
3453 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) | ||
3454 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) | ||
3455 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) | ||
3456 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) | ||
3457 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) | ||
3458 | |||
3459 | /* legacy values */ | ||
3460 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) | ||
3461 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) | ||
3462 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) | ||
3463 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) | ||
3464 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) | ||
3465 | |||
3466 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) | ||
3467 | |||
3450 | #define FORCEWAKE 0xA18C | 3468 | #define FORCEWAKE 0xA18C |
3451 | #define FORCEWAKE_ACK 0x130090 | 3469 | #define FORCEWAKE_ACK 0x130090 |
3470 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ | ||
3471 | #define FORCEWAKE_MT_ACK 0x130040 | ||
3472 | #define ECOBUS 0xa180 | ||
3473 | #define FORCEWAKE_MT_ENABLE (1<<5) | ||
3452 | 3474 | ||
3453 | #define GT_FIFO_FREE_ENTRIES 0x120008 | 3475 | #define GT_FIFO_FREE_ENTRIES 0x120008 |
3454 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 | 3476 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |