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path: root/drivers/gpu/drm/i915/i915_reg.h
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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1046
1 files changed, 759 insertions, 287 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4f5e15577e89..5d5def756c9e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,52 +25,16 @@
25#ifndef _I915_REG_H_ 25#ifndef _I915_REG_H_
26#define _I915_REG_H_ 26#define _I915_REG_H_
27 27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
28/* 30/*
29 * The Bridge device's PCI config space has information about the 31 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory. 32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
31 */ 35 */
32#define INTEL_GMCH_CTRL 0x52 36#define INTEL_GMCH_CTRL 0x52
33#define INTEL_GMCH_VGA_DISABLE (1 << 1) 37#define INTEL_GMCH_VGA_DISABLE (1 << 1)
34#define INTEL_GMCH_ENABLED 0x4
35#define INTEL_GMCH_MEM_MASK 0x1
36#define INTEL_GMCH_MEM_64M 0x1
37#define INTEL_GMCH_MEM_128M 0
38
39#define INTEL_GMCH_GMS_MASK (0xf << 4)
40#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
41#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
42#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
43#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
44#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
45#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
46
47#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
48#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
49#define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
50#define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
51#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
52#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
53#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
54#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
55
56#define SNB_GMCH_CTRL 0x50
57#define SNB_GMCH_GMS_STOLEN_MASK 0xF8
58#define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
59#define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
60#define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
61#define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
62#define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
63#define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
64#define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
65#define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
66#define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
67#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
68#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
69#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
70#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
71#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
72#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
73#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
74 38
75/* PCI config space */ 39/* PCI config space */
76 40
@@ -106,10 +70,19 @@
106#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
107#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
108#define LBB 0xf4 72#define LBB 0xf4
109#define GDRST 0xc0 73
110#define GDRST_FULL (0<<2) 74/* Graphics reset regs */
111#define GDRST_RENDER (1<<2) 75#define I965_GDRST 0xc0 /* PCI config register */
112#define GDRST_MEDIA (3<<2) 76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
80
81#define GEN6_GDRST 0x941c
82#define GEN6_GRDOM_FULL (1 << 0)
83#define GEN6_GRDOM_RENDER (1 << 1)
84#define GEN6_GRDOM_MEDIA (1 << 2)
85#define GEN6_GRDOM_BLT (1 << 3)
113 86
114/* VGA stuff */ 87/* VGA stuff */
115 88
@@ -172,6 +145,8 @@
172#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 145#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
173#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 146#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
174#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 147#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
148#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
149#define MI_SUSPEND_FLUSH_EN (1<<0)
175#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 150#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
176#define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 151#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
177#define MI_OVERLAY_CONTINUE (0x0<<21) 152#define MI_OVERLAY_CONTINUE (0x0<<21)
@@ -186,17 +161,31 @@
186#define MI_MM_SPACE_PHYSICAL (0<<8) 161#define MI_MM_SPACE_PHYSICAL (0<<8)
187#define MI_SAVE_EXT_STATE_EN (1<<3) 162#define MI_SAVE_EXT_STATE_EN (1<<3)
188#define MI_RESTORE_EXT_STATE_EN (1<<2) 163#define MI_RESTORE_EXT_STATE_EN (1<<2)
164#define MI_FORCE_RESTORE (1<<1)
189#define MI_RESTORE_INHIBIT (1<<0) 165#define MI_RESTORE_INHIBIT (1<<0)
190#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 166#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
191#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 167#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
192#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 168#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
193#define MI_STORE_DWORD_INDEX_SHIFT 2 169#define MI_STORE_DWORD_INDEX_SHIFT 2
194#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 170/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
171 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
172 * simply ignores the register load under certain conditions.
173 * - One can actually load arbitrary many arbitrary registers: Simply issue x
174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
175 */
176#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
177#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
178#define MI_INVALIDATE_TLB (1<<18)
179#define MI_INVALIDATE_BSD (1<<7)
195#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 180#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
196#define MI_BATCH_NON_SECURE (1) 181#define MI_BATCH_NON_SECURE (1)
197#define MI_BATCH_NON_SECURE_I965 (1<<8) 182#define MI_BATCH_NON_SECURE_I965 (1<<8)
198#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 183#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
199 184#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
185#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
186#define MI_SEMAPHORE_UPDATE (1<<21)
187#define MI_SEMAPHORE_COMPARE (1<<20)
188#define MI_SEMAPHORE_REGISTER (1<<18)
200/* 189/*
201 * 3D instructions used by the kernel 190 * 3D instructions used by the kernel
202 */ 191 */
@@ -249,6 +238,16 @@
249#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 238#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
250#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ 239#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
251 240
241
242/*
243 * Reset registers
244 */
245#define DEBUG_RESET_I830 0x6070
246#define DEBUG_RESET_FULL (1<<7)
247#define DEBUG_RESET_RENDER (1<<8)
248#define DEBUG_RESET_DISPLAY (1<<9)
249
250
252/* 251/*
253 * Fence registers 252 * Fence registers
254 */ 253 */
@@ -279,10 +278,25 @@
279 * Instruction and interrupt control regs 278 * Instruction and interrupt control regs
280 */ 279 */
281#define PGTBL_ER 0x02024 280#define PGTBL_ER 0x02024
282#define PRB0_TAIL 0x02030 281#define RENDER_RING_BASE 0x02000
283#define PRB0_HEAD 0x02034 282#define BSD_RING_BASE 0x04000
284#define PRB0_START 0x02038 283#define GEN6_BSD_RING_BASE 0x12000
285#define PRB0_CTL 0x0203c 284#define BLT_RING_BASE 0x22000
285#define RING_TAIL(base) ((base)+0x30)
286#define RING_HEAD(base) ((base)+0x34)
287#define RING_START(base) ((base)+0x38)
288#define RING_CTL(base) ((base)+0x3c)
289#define RING_SYNC_0(base) ((base)+0x40)
290#define RING_SYNC_1(base) ((base)+0x44)
291#define RING_MAX_IDLE(base) ((base)+0x54)
292#define RING_HWS_PGA(base) ((base)+0x80)
293#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
294#define RENDER_HWS_PGA_GEN7 (0x04080)
295#define BSD_HWS_PGA_GEN7 (0x04180)
296#define BLT_HWS_PGA_GEN7 (0x04280)
297#define RING_ACTHD(base) ((base)+0x74)
298#define RING_NOPID(base) ((base)+0x94)
299#define RING_IMR(base) ((base)+0xa8)
286#define TAIL_ADDR 0x001FFFF8 300#define TAIL_ADDR 0x001FFFF8
287#define HEAD_WRAP_COUNT 0xFFE00000 301#define HEAD_WRAP_COUNT 0xFFE00000
288#define HEAD_WRAP_ONE 0x00200000 302#define HEAD_WRAP_ONE 0x00200000
@@ -295,10 +309,19 @@
295#define RING_VALID_MASK 0x00000001 309#define RING_VALID_MASK 0x00000001
296#define RING_VALID 0x00000001 310#define RING_VALID 0x00000001
297#define RING_INVALID 0x00000000 311#define RING_INVALID 0x00000000
312#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
313#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
314#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
315#if 0
316#define PRB0_TAIL 0x02030
317#define PRB0_HEAD 0x02034
318#define PRB0_START 0x02038
319#define PRB0_CTL 0x0203c
298#define PRB1_TAIL 0x02040 /* 915+ only */ 320#define PRB1_TAIL 0x02040 /* 915+ only */
299#define PRB1_HEAD 0x02044 /* 915+ only */ 321#define PRB1_HEAD 0x02044 /* 915+ only */
300#define PRB1_START 0x02048 /* 915+ only */ 322#define PRB1_START 0x02048 /* 915+ only */
301#define PRB1_CTL 0x0204c /* 915+ only */ 323#define PRB1_CTL 0x0204c /* 915+ only */
324#endif
302#define IPEIR_I965 0x02064 325#define IPEIR_I965 0x02064
303#define IPEHR_I965 0x02068 326#define IPEHR_I965 0x02068
304#define INSTDONE_I965 0x0206c 327#define INSTDONE_I965 0x0206c
@@ -306,7 +329,6 @@
306#define INSTDONE1 0x0207c /* 965+ only */ 329#define INSTDONE1 0x0207c /* 965+ only */
307#define ACTHD_I965 0x02074 330#define ACTHD_I965 0x02074
308#define HWS_PGA 0x02080 331#define HWS_PGA 0x02080
309#define HWS_PGA_GEN6 0x04080
310#define HWS_ADDRESS_MASK 0xfffff000 332#define HWS_ADDRESS_MASK 0xfffff000
311#define HWS_START_ADDRESS_SHIFT 4 333#define HWS_START_ADDRESS_SHIFT 4
312#define PWRCTXA 0x2088 /* 965GM+ only */ 334#define PWRCTXA 0x2088 /* 965GM+ only */
@@ -316,11 +338,42 @@
316#define INSTDONE 0x02090 338#define INSTDONE 0x02090
317#define NOPID 0x02094 339#define NOPID 0x02094
318#define HWSTAM 0x02098 340#define HWSTAM 0x02098
341#define VCS_INSTDONE 0x1206C
342#define VCS_IPEIR 0x12064
343#define VCS_IPEHR 0x12068
344#define VCS_ACTHD 0x12074
345#define BCS_INSTDONE 0x2206C
346#define BCS_IPEIR 0x22064
347#define BCS_IPEHR 0x22068
348#define BCS_ACTHD 0x22074
349
350#define ERROR_GEN6 0x040a0
351
352/* GM45+ chicken bits -- debug workaround bits that may be required
353 * for various sorts of correct behavior. The top 16 bits of each are
354 * the enables for writing to the corresponding low bit.
355 */
356#define _3D_CHICKEN 0x02084
357#define _3D_CHICKEN2 0x0208c
358/* Disables pipelining of read flushes past the SF-WIZ interface.
359 * Required on all Ironlake steppings according to the B-Spec, but the
360 * particular danger of not doing so is not specified.
361 */
362# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
363#define _3D_CHICKEN3 0x02090
319 364
320#define MI_MODE 0x0209c 365#define MI_MODE 0x0209c
321# define VS_TIMER_DISPATCH (1 << 6) 366# define VS_TIMER_DISPATCH (1 << 6)
322# define MI_FLUSH_ENABLE (1 << 11) 367# define MI_FLUSH_ENABLE (1 << 11)
323 368
369#define GFX_MODE 0x02520
370#define GFX_RUN_LIST_ENABLE (1<<15)
371#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
372#define GFX_SURFACE_FAULT_ENABLE (1<<12)
373#define GFX_REPLAY_MODE (1<<11)
374#define GFX_PSMI_GRANULARITY (1<<10)
375#define GFX_PPGTT_ENABLE (1<<9)
376
324#define SCPD0 0x0209c /* 915+ only */ 377#define SCPD0 0x0209c /* 915+ only */
325#define IER 0x020a0 378#define IER 0x020a0
326#define IIR 0x020a4 379#define IIR 0x020a4
@@ -355,9 +408,12 @@
355#define I915_ERROR_INSTRUCTION (1<<0) 408#define I915_ERROR_INSTRUCTION (1<<0)
356#define INSTPM 0x020c0 409#define INSTPM 0x020c0
357#define INSTPM_SELF_EN (1<<12) /* 915GM only */ 410#define INSTPM_SELF_EN (1<<12) /* 915GM only */
411#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
412 will not assert AGPBUSY# and will only
413 be delivered when out of C3. */
358#define ACTHD 0x020c8 414#define ACTHD 0x020c8
359#define FW_BLC 0x020d8 415#define FW_BLC 0x020d8
360#define FW_BLC2 0x020dc 416#define FW_BLC2 0x020dc
361#define FW_BLC_SELF 0x020e0 /* 915+ only */ 417#define FW_BLC_SELF 0x020e0 /* 915+ only */
362#define FW_BLC_SELF_EN_MASK (1<<31) 418#define FW_BLC_SELF_EN_MASK (1<<31)
363#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 419#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
@@ -464,17 +520,22 @@
464#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 520#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
465#define GEN6_BLITTER_SYNC_STATUS (1 << 24) 521#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
466#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 522#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
467/*
468 * BSD (bit stream decoder instruction and interrupt control register defines
469 * (G4X and Ironlake only)
470 */
471 523
472#define BSD_RING_TAIL 0x04030 524#define GEN6_BLITTER_ECOSKPD 0x221d0
473#define BSD_RING_HEAD 0x04034 525#define GEN6_BLITTER_LOCK_SHIFT 16
474#define BSD_RING_START 0x04038 526#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
475#define BSD_RING_CTL 0x0403c 527
476#define BSD_RING_ACTHD 0x04074 528#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
477#define BSD_HWS_PGA 0x04080 529#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
530#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
531#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
532#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
533
534#define GEN6_BSD_HWSTAM 0x12098
535#define GEN6_BSD_IMR 0x120a8
536#define GEN6_BSD_USER_INTERRUPT (1 << 12)
537
538#define GEN6_BSD_RNCID 0x12198
478 539
479/* 540/*
480 * Framebuffer compression (915+ only) 541 * Framebuffer compression (915+ only)
@@ -552,6 +613,18 @@
552 613
553#define ILK_DISPLAY_CHICKEN1 0x42000 614#define ILK_DISPLAY_CHICKEN1 0x42000
554#define ILK_FBCQ_DIS (1<<22) 615#define ILK_FBCQ_DIS (1<<22)
616#define ILK_PABSTRETCH_DIS (1<<21)
617
618
619/*
620 * Framebuffer compression for Sandybridge
621 *
622 * The following two registers are of type GTTMMADR
623 */
624#define SNB_DPFC_CTL_SA 0x100100
625#define SNB_CPU_FENCE_ENABLE (1<<29)
626#define DPFC_CPU_FENCE_OFFSET 0x100104
627
555 628
556/* 629/*
557 * GPIO regs 630 * GPIO regs
@@ -579,12 +652,51 @@
579# define GPIO_DATA_VAL_IN (1 << 12) 652# define GPIO_DATA_VAL_IN (1 << 12)
580# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 653# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
581 654
582#define GMBUS0 0x5100 655#define GMBUS0 0x5100 /* clock/port select */
583#define GMBUS1 0x5104 656#define GMBUS_RATE_100KHZ (0<<8)
584#define GMBUS2 0x5108 657#define GMBUS_RATE_50KHZ (1<<8)
585#define GMBUS3 0x510c 658#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
586#define GMBUS4 0x5110 659#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
587#define GMBUS5 0x5120 660#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
661#define GMBUS_PORT_DISABLED 0
662#define GMBUS_PORT_SSC 1
663#define GMBUS_PORT_VGADDC 2
664#define GMBUS_PORT_PANEL 3
665#define GMBUS_PORT_DPC 4 /* HDMIC */
666#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
667 /* 6 reserved */
668#define GMBUS_PORT_DPD 7 /* HDMID */
669#define GMBUS_NUM_PORTS 8
670#define GMBUS1 0x5104 /* command/status */
671#define GMBUS_SW_CLR_INT (1<<31)
672#define GMBUS_SW_RDY (1<<30)
673#define GMBUS_ENT (1<<29) /* enable timeout */
674#define GMBUS_CYCLE_NONE (0<<25)
675#define GMBUS_CYCLE_WAIT (1<<25)
676#define GMBUS_CYCLE_INDEX (2<<25)
677#define GMBUS_CYCLE_STOP (4<<25)
678#define GMBUS_BYTE_COUNT_SHIFT 16
679#define GMBUS_SLAVE_INDEX_SHIFT 8
680#define GMBUS_SLAVE_ADDR_SHIFT 1
681#define GMBUS_SLAVE_READ (1<<0)
682#define GMBUS_SLAVE_WRITE (0<<0)
683#define GMBUS2 0x5108 /* status */
684#define GMBUS_INUSE (1<<15)
685#define GMBUS_HW_WAIT_PHASE (1<<14)
686#define GMBUS_STALL_TIMEOUT (1<<13)
687#define GMBUS_INT (1<<12)
688#define GMBUS_HW_RDY (1<<11)
689#define GMBUS_SATOER (1<<10)
690#define GMBUS_ACTIVE (1<<9)
691#define GMBUS3 0x510c /* data buffer bytes 3-0 */
692#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
693#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
694#define GMBUS_NAK_EN (1<<3)
695#define GMBUS_IDLE_EN (1<<2)
696#define GMBUS_HW_WAIT_EN (1<<1)
697#define GMBUS_HW_RDY_EN (1<<0)
698#define GMBUS5 0x5120 /* byte index */
699#define GMBUS_2BYTE_INDEX_EN (1<<31)
588 700
589/* 701/*
590 * Clock control & power management 702 * Clock control & power management
@@ -601,8 +713,9 @@
601#define VGA1_PD_P1_DIV_2 (1 << 13) 713#define VGA1_PD_P1_DIV_2 (1 << 13)
602#define VGA1_PD_P1_SHIFT 8 714#define VGA1_PD_P1_SHIFT 8
603#define VGA1_PD_P1_MASK (0x1f << 8) 715#define VGA1_PD_P1_MASK (0x1f << 8)
604#define DPLL_A 0x06014 716#define _DPLL_A 0x06014
605#define DPLL_B 0x06018 717#define _DPLL_B 0x06018
718#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
606#define DPLL_VCO_ENABLE (1 << 31) 719#define DPLL_VCO_ENABLE (1 << 31)
607#define DPLL_DVO_HIGH_SPEED (1 << 30) 720#define DPLL_DVO_HIGH_SPEED (1 << 30)
608#define DPLL_SYNCLOCK_ENABLE (1 << 29) 721#define DPLL_SYNCLOCK_ENABLE (1 << 29)
@@ -633,31 +746,6 @@
633#define LVDS 0x61180 746#define LVDS 0x61180
634#define LVDS_ON (1<<31) 747#define LVDS_ON (1<<31)
635 748
636#define ADPA 0x61100
637#define ADPA_DPMS_MASK (~(3<<10))
638#define ADPA_DPMS_ON (0<<10)
639#define ADPA_DPMS_SUSPEND (1<<10)
640#define ADPA_DPMS_STANDBY (2<<10)
641#define ADPA_DPMS_OFF (3<<10)
642
643#define RING_TAIL 0x00
644#define TAIL_ADDR 0x001FFFF8
645#define RING_HEAD 0x04
646#define HEAD_WRAP_COUNT 0xFFE00000
647#define HEAD_WRAP_ONE 0x00200000
648#define HEAD_ADDR 0x001FFFFC
649#define RING_START 0x08
650#define START_ADDR 0xFFFFF000
651#define RING_LEN 0x0C
652#define RING_NR_PAGES 0x001FF000
653#define RING_REPORT_MASK 0x00000006
654#define RING_REPORT_64K 0x00000002
655#define RING_REPORT_128K 0x00000004
656#define RING_NO_REPORT 0x00000000
657#define RING_VALID_MASK 0x00000001
658#define RING_VALID 0x00000001
659#define RING_INVALID 0x00000000
660
661/* Scratch pad debug 0 reg: 749/* Scratch pad debug 0 reg:
662 */ 750 */
663#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 751#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
@@ -698,7 +786,7 @@
698#define SDVO_MULTIPLIER_MASK 0x000000ff 786#define SDVO_MULTIPLIER_MASK 0x000000ff
699#define SDVO_MULTIPLIER_SHIFT_HIRES 4 787#define SDVO_MULTIPLIER_SHIFT_HIRES 4
700#define SDVO_MULTIPLIER_SHIFT_VGA 0 788#define SDVO_MULTIPLIER_SHIFT_VGA 0
701#define DPLL_A_MD 0x0601c /* 965+ only */ 789#define _DPLL_A_MD 0x0601c /* 965+ only */
702/* 790/*
703 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 791 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
704 * 792 *
@@ -735,11 +823,14 @@
735 */ 823 */
736#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 824#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
737#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 825#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
738#define DPLL_B_MD 0x06020 /* 965+ only */ 826#define _DPLL_B_MD 0x06020 /* 965+ only */
739#define FPA0 0x06040 827#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
740#define FPA1 0x06044 828#define _FPA0 0x06040
741#define FPB0 0x06048 829#define _FPA1 0x06044
742#define FPB1 0x0604c 830#define _FPB0 0x06048
831#define _FPB1 0x0604c
832#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
833#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
743#define FP_N_DIV_MASK 0x003f0000 834#define FP_N_DIV_MASK 0x003f0000
744#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 835#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
745#define FP_N_DIV_SHIFT 16 836#define FP_N_DIV_SHIFT 16
@@ -760,6 +851,7 @@
760#define DPLLA_TEST_M_BYPASS (1 << 2) 851#define DPLLA_TEST_M_BYPASS (1 << 2)
761#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 852#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
762#define D_STATE 0x6104 853#define D_STATE 0x6104
854#define DSTATE_GFX_RESET_I830 (1<<6)
763#define DSTATE_PLL_D3_OFF (1<<3) 855#define DSTATE_PLL_D3_OFF (1<<3)
764#define DSTATE_GFX_CLOCK_GATING (1<<1) 856#define DSTATE_GFX_CLOCK_GATING (1<<1)
765#define DSTATE_DOT_CLOCK_GATING (1<<0) 857#define DSTATE_DOT_CLOCK_GATING (1<<0)
@@ -877,8 +969,9 @@
877 * Palette regs 969 * Palette regs
878 */ 970 */
879 971
880#define PALETTE_A 0x0a000 972#define _PALETTE_A 0x0a000
881#define PALETTE_B 0x0a800 973#define _PALETTE_B 0x0a800
974#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
882 975
883/* MCH MMIO space */ 976/* MCH MMIO space */
884 977
@@ -892,6 +985,8 @@
892 */ 985 */
893#define MCHBAR_MIRROR_BASE 0x10000 986#define MCHBAR_MIRROR_BASE 0x10000
894 987
988#define MCHBAR_MIRROR_BASE_SNB 0x140000
989
895/** 915-945 and GM965 MCH register controlling DRAM channel access */ 990/** 915-945 and GM965 MCH register controlling DRAM channel access */
896#define DCC 0x10200 991#define DCC 0x10200
897#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 992#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
@@ -926,6 +1021,8 @@
926#define CLKCFG_MEM_800 (3 << 4) 1021#define CLKCFG_MEM_800 (3 << 4)
927#define CLKCFG_MEM_MASK (7 << 4) 1022#define CLKCFG_MEM_MASK (7 << 4)
928 1023
1024#define TSC1 0x11001
1025#define TSE (1<<0)
929#define TR1 0x11006 1026#define TR1 0x11006
930#define TSFS 0x11020 1027#define TSFS 0x11020
931#define TSFS_SLOPE_MASK 0x0000ff00 1028#define TSFS_SLOPE_MASK 0x0000ff00
@@ -1051,9 +1148,50 @@
1051#define RCBMINAVG 0x111a0 1148#define RCBMINAVG 0x111a0
1052#define RCUPEI 0x111b0 1149#define RCUPEI 0x111b0
1053#define RCDNEI 0x111b4 1150#define RCDNEI 0x111b4
1054#define MCHBAR_RENDER_STANDBY 0x111b8 1151#define RSTDBYCTL 0x111b8
1055#define RCX_SW_EXIT (1<<23) 1152#define RS1EN (1<<31)
1056#define RSX_STATUS_MASK 0x00700000 1153#define RS2EN (1<<30)
1154#define RS3EN (1<<29)
1155#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1156#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1157#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1158#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1159#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1160#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1161#define RSX_STATUS_MASK (7<<20)
1162#define RSX_STATUS_ON (0<<20)
1163#define RSX_STATUS_RC1 (1<<20)
1164#define RSX_STATUS_RC1E (2<<20)
1165#define RSX_STATUS_RS1 (3<<20)
1166#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1167#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1168#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1169#define RSX_STATUS_RSVD2 (7<<20)
1170#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1171#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1172#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1173#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1174#define RS1CONTSAV_MASK (3<<14)
1175#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1176#define RS1CONTSAV_RSVD (1<<14)
1177#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1178#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1179#define NORMSLEXLAT_MASK (3<<12)
1180#define SLOW_RS123 (0<<12)
1181#define SLOW_RS23 (1<<12)
1182#define SLOW_RS3 (2<<12)
1183#define NORMAL_RS123 (3<<12)
1184#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1185#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1186#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1187#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1188#define RS_CSTATE_MASK (3<<4)
1189#define RS_CSTATE_C367_RS1 (0<<4)
1190#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1191#define RS_CSTATE_RSVD (2<<4)
1192#define RS_CSTATE_C367_RS2 (3<<4)
1193#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1194#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1057#define VIDCTL 0x111c0 1195#define VIDCTL 0x111c0
1058#define VIDSTS 0x111c8 1196#define VIDSTS 0x111c8
1059#define VIDSTART 0x111cc /* 8 bits */ 1197#define VIDSTART 0x111cc /* 8 bits */
@@ -1070,6 +1208,8 @@
1070#define MEMSTAT_SRC_CTL_STDBY 3 1208#define MEMSTAT_SRC_CTL_STDBY 3
1071#define RCPREVBSYTUPAVG 0x113b8 1209#define RCPREVBSYTUPAVG 0x113b8
1072#define RCPREVBSYTDNAVG 0x113bc 1210#define RCPREVBSYTDNAVG 0x113bc
1211#define PMMISC 0x11214
1212#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1073#define SDEW 0x1124c 1213#define SDEW 0x1124c
1074#define CSIEW0 0x11250 1214#define CSIEW0 0x11250
1075#define CSIEW1 0x11254 1215#define CSIEW1 0x11254
@@ -1107,6 +1247,10 @@
1107#define DDRMPLL1 0X12c20 1247#define DDRMPLL1 0X12c20
1108#define PEG_BAND_GAP_DATA 0x14d68 1248#define PEG_BAND_GAP_DATA 0x14d68
1109 1249
1250#define GEN6_GT_PERF_STATUS 0x145948
1251#define GEN6_RP_STATE_LIMITS 0x145994
1252#define GEN6_RP_STATE_CAP 0x145998
1253
1110/* 1254/*
1111 * Logical Context regs 1255 * Logical Context regs
1112 */ 1256 */
@@ -1131,24 +1275,32 @@
1131 */ 1275 */
1132 1276
1133/* Pipe A timing regs */ 1277/* Pipe A timing regs */
1134#define HTOTAL_A 0x60000 1278#define _HTOTAL_A 0x60000
1135#define HBLANK_A 0x60004 1279#define _HBLANK_A 0x60004
1136#define HSYNC_A 0x60008 1280#define _HSYNC_A 0x60008
1137#define VTOTAL_A 0x6000c 1281#define _VTOTAL_A 0x6000c
1138#define VBLANK_A 0x60010 1282#define _VBLANK_A 0x60010
1139#define VSYNC_A 0x60014 1283#define _VSYNC_A 0x60014
1140#define PIPEASRC 0x6001c 1284#define _PIPEASRC 0x6001c
1141#define BCLRPAT_A 0x60020 1285#define _BCLRPAT_A 0x60020
1142 1286
1143/* Pipe B timing regs */ 1287/* Pipe B timing regs */
1144#define HTOTAL_B 0x61000 1288#define _HTOTAL_B 0x61000
1145#define HBLANK_B 0x61004 1289#define _HBLANK_B 0x61004
1146#define HSYNC_B 0x61008 1290#define _HSYNC_B 0x61008
1147#define VTOTAL_B 0x6100c 1291#define _VTOTAL_B 0x6100c
1148#define VBLANK_B 0x61010 1292#define _VBLANK_B 0x61010
1149#define VSYNC_B 0x61014 1293#define _VSYNC_B 0x61014
1150#define PIPEBSRC 0x6101c 1294#define _PIPEBSRC 0x6101c
1151#define BCLRPAT_B 0x61020 1295#define _BCLRPAT_B 0x61020
1296
1297#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1298#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1299#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1300#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1301#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1302#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1303#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1152 1304
1153/* VGA port control */ 1305/* VGA port control */
1154#define ADPA 0x61100 1306#define ADPA 0x61100
@@ -1173,6 +1325,7 @@
1173#define ADPA_DPMS_STANDBY (2<<10) 1325#define ADPA_DPMS_STANDBY (2<<10)
1174#define ADPA_DPMS_OFF (3<<10) 1326#define ADPA_DPMS_OFF (3<<10)
1175 1327
1328
1176/* Hotplug control (945+ only) */ 1329/* Hotplug control (945+ only) */
1177#define PORT_HOTPLUG_EN 0x61110 1330#define PORT_HOTPLUG_EN 0x61110
1178#define HDMIB_HOTPLUG_INT_EN (1 << 29) 1331#define HDMIB_HOTPLUG_INT_EN (1 << 29)
@@ -1241,6 +1394,7 @@
1241#define SDVO_ENCODING_HDMI (0x2 << 10) 1394#define SDVO_ENCODING_HDMI (0x2 << 10)
1242/** Requird for HDMI operation */ 1395/** Requird for HDMI operation */
1243#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1396#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1397#define SDVO_COLOR_RANGE_16_235 (1 << 8)
1244#define SDVO_BORDER_ENABLE (1 << 7) 1398#define SDVO_BORDER_ENABLE (1 << 7)
1245#define SDVO_AUDIO_ENABLE (1 << 6) 1399#define SDVO_AUDIO_ENABLE (1 << 6)
1246/** New with 965, default is to be set */ 1400/** New with 965, default is to be set */
@@ -1296,8 +1450,13 @@
1296#define LVDS_PORT_EN (1 << 31) 1450#define LVDS_PORT_EN (1 << 31)
1297/* Selects pipe B for LVDS data. Must be set on pre-965. */ 1451/* Selects pipe B for LVDS data. Must be set on pre-965. */
1298#define LVDS_PIPEB_SELECT (1 << 30) 1452#define LVDS_PIPEB_SELECT (1 << 30)
1453#define LVDS_PIPE_MASK (1 << 30)
1299/* LVDS dithering flag on 965/g4x platform */ 1454/* LVDS dithering flag on 965/g4x platform */
1300#define LVDS_ENABLE_DITHER (1 << 25) 1455#define LVDS_ENABLE_DITHER (1 << 25)
1456/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1457#define LVDS_VSYNC_POLARITY (1 << 21)
1458#define LVDS_HSYNC_POLARITY (1 << 20)
1459
1301/* Enable border for unscaled (or aspect-scaled) display */ 1460/* Enable border for unscaled (or aspect-scaled) display */
1302#define LVDS_BORDER_ENABLE (1 << 15) 1461#define LVDS_BORDER_ENABLE (1 << 15)
1303/* 1462/*
@@ -1331,6 +1490,25 @@
1331#define LVDS_B0B3_POWER_DOWN (0 << 2) 1490#define LVDS_B0B3_POWER_DOWN (0 << 2)
1332#define LVDS_B0B3_POWER_UP (3 << 2) 1491#define LVDS_B0B3_POWER_UP (3 << 2)
1333 1492
1493#define LVDS_PIPE_ENABLED(V, P) \
1494 (((V) & (LVDS_PIPE_MASK | LVDS_PORT_EN)) == ((P) << 30 | LVDS_PORT_EN))
1495
1496/* Video Data Island Packet control */
1497#define VIDEO_DIP_DATA 0x61178
1498#define VIDEO_DIP_CTL 0x61170
1499#define VIDEO_DIP_ENABLE (1 << 31)
1500#define VIDEO_DIP_PORT_B (1 << 29)
1501#define VIDEO_DIP_PORT_C (2 << 29)
1502#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1503#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1504#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1505#define VIDEO_DIP_SELECT_AVI (0 << 19)
1506#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1507#define VIDEO_DIP_SELECT_SPD (3 << 19)
1508#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1509#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1510#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1511
1334/* Panel power sequencing */ 1512/* Panel power sequencing */
1335#define PP_STATUS 0x61200 1513#define PP_STATUS 0x61200
1336#define PP_ON (1 << 31) 1514#define PP_ON (1 << 31)
@@ -1346,6 +1524,9 @@
1346#define PP_SEQUENCE_ON (1 << 28) 1524#define PP_SEQUENCE_ON (1 << 28)
1347#define PP_SEQUENCE_OFF (2 << 28) 1525#define PP_SEQUENCE_OFF (2 << 28)
1348#define PP_SEQUENCE_MASK 0x30000000 1526#define PP_SEQUENCE_MASK 0x30000000
1527#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1528#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1529#define PP_SEQUENCE_STATE_MASK 0x0000000f
1349#define PP_CONTROL 0x61204 1530#define PP_CONTROL 0x61204
1350#define POWER_TARGET_ON (1 << 0) 1531#define POWER_TARGET_ON (1 << 0)
1351#define PP_ON_DELAYS 0x61208 1532#define PP_ON_DELAYS 0x61208
@@ -1481,6 +1662,7 @@
1481# define TV_TEST_MODE_MASK (7 << 0) 1662# define TV_TEST_MODE_MASK (7 << 0)
1482 1663
1483#define TV_DAC 0x68004 1664#define TV_DAC 0x68004
1665# define TV_DAC_SAVE 0x00ffff00
1484/** 1666/**
1485 * Reports that DAC state change logic has reported change (RO). 1667 * Reports that DAC state change logic has reported change (RO).
1486 * 1668 *
@@ -1899,6 +2081,10 @@
1899 2081
1900#define DP_PORT_EN (1 << 31) 2082#define DP_PORT_EN (1 << 31)
1901#define DP_PIPEB_SELECT (1 << 30) 2083#define DP_PIPEB_SELECT (1 << 30)
2084#define DP_PIPE_MASK (1 << 30)
2085
2086#define DP_PIPE_ENABLED(V, P) \
2087 (((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
1902 2088
1903/* Link training mode - select a suitable mode for each stage */ 2089/* Link training mode - select a suitable mode for each stage */
1904#define DP_LINK_TRAIN_PAT_1 (0 << 28) 2090#define DP_LINK_TRAIN_PAT_1 (0 << 28)
@@ -2041,8 +2227,8 @@
2041 * which is after the LUTs, so we want the bytes for our color format. 2227 * which is after the LUTs, so we want the bytes for our color format.
2042 * For our current usage, this is always 3, one byte for R, G and B. 2228 * For our current usage, this is always 3, one byte for R, G and B.
2043 */ 2229 */
2044#define PIPEA_GMCH_DATA_M 0x70050 2230#define _PIPEA_GMCH_DATA_M 0x70050
2045#define PIPEB_GMCH_DATA_M 0x71050 2231#define _PIPEB_GMCH_DATA_M 0x71050
2046 2232
2047/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2233/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2048#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2234#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
@@ -2050,8 +2236,8 @@
2050 2236
2051#define PIPE_GMCH_DATA_M_MASK (0xffffff) 2237#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2052 2238
2053#define PIPEA_GMCH_DATA_N 0x70054 2239#define _PIPEA_GMCH_DATA_N 0x70054
2054#define PIPEB_GMCH_DATA_N 0x71054 2240#define _PIPEB_GMCH_DATA_N 0x71054
2055#define PIPE_GMCH_DATA_N_MASK (0xffffff) 2241#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2056 2242
2057/* 2243/*
@@ -2065,40 +2251,51 @@
2065 * Attributes and VB-ID. 2251 * Attributes and VB-ID.
2066 */ 2252 */
2067 2253
2068#define PIPEA_DP_LINK_M 0x70060 2254#define _PIPEA_DP_LINK_M 0x70060
2069#define PIPEB_DP_LINK_M 0x71060 2255#define _PIPEB_DP_LINK_M 0x71060
2070#define PIPEA_DP_LINK_M_MASK (0xffffff) 2256#define PIPEA_DP_LINK_M_MASK (0xffffff)
2071 2257
2072#define PIPEA_DP_LINK_N 0x70064 2258#define _PIPEA_DP_LINK_N 0x70064
2073#define PIPEB_DP_LINK_N 0x71064 2259#define _PIPEB_DP_LINK_N 0x71064
2074#define PIPEA_DP_LINK_N_MASK (0xffffff) 2260#define PIPEA_DP_LINK_N_MASK (0xffffff)
2075 2261
2262#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2263#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2264#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2265#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2266
2076/* Display & cursor control */ 2267/* Display & cursor control */
2077 2268
2078/* dithering flag on Ironlake */
2079#define PIPE_ENABLE_DITHER (1 << 4)
2080#define PIPE_DITHER_TYPE_MASK (3 << 2)
2081#define PIPE_DITHER_TYPE_SPATIAL (0 << 2)
2082#define PIPE_DITHER_TYPE_ST01 (1 << 2)
2083/* Pipe A */ 2269/* Pipe A */
2084#define PIPEADSL 0x70000 2270#define _PIPEADSL 0x70000
2085#define DSL_LINEMASK 0x00000fff 2271#define DSL_LINEMASK 0x00000fff
2086#define PIPEACONF 0x70008 2272#define _PIPEACONF 0x70008
2087#define PIPEACONF_ENABLE (1<<31) 2273#define PIPECONF_ENABLE (1<<31)
2088#define PIPEACONF_DISABLE 0 2274#define PIPECONF_DISABLE 0
2089#define PIPEACONF_DOUBLE_WIDE (1<<30) 2275#define PIPECONF_DOUBLE_WIDE (1<<30)
2090#define I965_PIPECONF_ACTIVE (1<<30) 2276#define I965_PIPECONF_ACTIVE (1<<30)
2091#define PIPEACONF_SINGLE_WIDE 0 2277#define PIPECONF_SINGLE_WIDE 0
2092#define PIPEACONF_PIPE_UNLOCKED 0 2278#define PIPECONF_PIPE_UNLOCKED 0
2093#define PIPEACONF_PIPE_LOCKED (1<<25) 2279#define PIPECONF_PIPE_LOCKED (1<<25)
2094#define PIPEACONF_PALETTE 0 2280#define PIPECONF_PALETTE 0
2095#define PIPEACONF_GAMMA (1<<24) 2281#define PIPECONF_GAMMA (1<<24)
2096#define PIPECONF_FORCE_BORDER (1<<25) 2282#define PIPECONF_FORCE_BORDER (1<<25)
2097#define PIPECONF_PROGRESSIVE (0 << 21) 2283#define PIPECONF_PROGRESSIVE (0 << 21)
2098#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2284#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2099#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2285#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2100#define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2286#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2101#define PIPEASTAT 0x70024 2287#define PIPECONF_BPP_MASK (0x000000e0)
2288#define PIPECONF_BPP_8 (0<<5)
2289#define PIPECONF_BPP_10 (1<<5)
2290#define PIPECONF_BPP_6 (2<<5)
2291#define PIPECONF_BPP_12 (3<<5)
2292#define PIPECONF_DITHER_EN (1<<4)
2293#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2294#define PIPECONF_DITHER_TYPE_SP (0<<2)
2295#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2296#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2297#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2298#define _PIPEASTAT 0x70024
2102#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2299#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2103#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2300#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2104#define PIPE_CRC_DONE_ENABLE (1UL<<28) 2301#define PIPE_CRC_DONE_ENABLE (1UL<<28)
@@ -2128,12 +2325,19 @@
2128#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2325#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2129#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2326#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2130#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2327#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2131#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2328#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2132#define PIPE_8BPC (0 << 5) 2329#define PIPE_8BPC (0 << 5)
2133#define PIPE_10BPC (1 << 5) 2330#define PIPE_10BPC (1 << 5)
2134#define PIPE_6BPC (2 << 5) 2331#define PIPE_6BPC (2 << 5)
2135#define PIPE_12BPC (3 << 5) 2332#define PIPE_12BPC (3 << 5)
2136 2333
2334#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2335#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2336#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2337#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2338#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2339#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2340
2137#define DSPARB 0x70030 2341#define DSPARB 0x70030
2138#define DSPARB_CSTART_MASK (0x7f << 7) 2342#define DSPARB_CSTART_MASK (0x7f << 7)
2139#define DSPARB_CSTART_SHIFT 7 2343#define DSPARB_CSTART_SHIFT 7
@@ -2206,8 +2410,8 @@
2206#define WM1_LP_SR_EN (1<<31) 2410#define WM1_LP_SR_EN (1<<31)
2207#define WM1_LP_LATENCY_SHIFT 24 2411#define WM1_LP_LATENCY_SHIFT 24
2208#define WM1_LP_LATENCY_MASK (0x7f<<24) 2412#define WM1_LP_LATENCY_MASK (0x7f<<24)
2209#define WM1_LP_FBC_LP1_MASK (0xf<<20) 2413#define WM1_LP_FBC_MASK (0xf<<20)
2210#define WM1_LP_FBC_LP1_SHIFT 20 2414#define WM1_LP_FBC_SHIFT 20
2211#define WM1_LP_SR_MASK (0x1ff<<8) 2415#define WM1_LP_SR_MASK (0x1ff<<8)
2212#define WM1_LP_SR_SHIFT 8 2416#define WM1_LP_SR_SHIFT 8
2213#define WM1_LP_CURSOR_MASK (0x3f) 2417#define WM1_LP_CURSOR_MASK (0x3f)
@@ -2220,8 +2424,13 @@
2220 2424
2221/* Memory latency timer register */ 2425/* Memory latency timer register */
2222#define MLTR_ILK 0x11222 2426#define MLTR_ILK 0x11222
2427#define MLTR_WM1_SHIFT 0
2428#define MLTR_WM2_SHIFT 8
2223/* the unit of memory self-refresh latency time is 0.5us */ 2429/* the unit of memory self-refresh latency time is 0.5us */
2224#define ILK_SRLT_MASK 0x3f 2430#define ILK_SRLT_MASK 0x3f
2431#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2432#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2433#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2225 2434
2226/* define the fifo size on Ironlake */ 2435/* define the fifo size on Ironlake */
2227#define ILK_DISPLAY_FIFO 128 2436#define ILK_DISPLAY_FIFO 128
@@ -2240,6 +2449,40 @@
2240 2449
2241#define ILK_FIFO_LINE_SIZE 64 2450#define ILK_FIFO_LINE_SIZE 64
2242 2451
2452/* define the WM info on Sandybridge */
2453#define SNB_DISPLAY_FIFO 128
2454#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2455#define SNB_DISPLAY_DFTWM 8
2456#define SNB_CURSOR_FIFO 32
2457#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2458#define SNB_CURSOR_DFTWM 8
2459
2460#define SNB_DISPLAY_SR_FIFO 512
2461#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2462#define SNB_DISPLAY_DFT_SRWM 0x3f
2463#define SNB_CURSOR_SR_FIFO 64
2464#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2465#define SNB_CURSOR_DFT_SRWM 8
2466
2467#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2468
2469#define SNB_FIFO_LINE_SIZE 64
2470
2471
2472/* the address where we get all kinds of latency value */
2473#define SSKPD 0x5d10
2474#define SSKPD_WM_MASK 0x3f
2475#define SSKPD_WM0_SHIFT 0
2476#define SSKPD_WM1_SHIFT 8
2477#define SSKPD_WM2_SHIFT 16
2478#define SSKPD_WM3_SHIFT 24
2479
2480#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2481#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2482#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2483#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2484#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2485
2243/* 2486/*
2244 * The two pipe frame counter registers are not synchronized, so 2487 * The two pipe frame counter registers are not synchronized, so
2245 * reading a stable value is somewhat tricky. The following code 2488 * reading a stable value is somewhat tricky. The following code
@@ -2255,20 +2498,21 @@
2255 * } while (high1 != high2); 2498 * } while (high1 != high2);
2256 * frame = (high1 << 8) | low1; 2499 * frame = (high1 << 8) | low1;
2257 */ 2500 */
2258#define PIPEAFRAMEHIGH 0x70040 2501#define _PIPEAFRAMEHIGH 0x70040
2259#define PIPE_FRAME_HIGH_MASK 0x0000ffff 2502#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2260#define PIPE_FRAME_HIGH_SHIFT 0 2503#define PIPE_FRAME_HIGH_SHIFT 0
2261#define PIPEAFRAMEPIXEL 0x70044 2504#define _PIPEAFRAMEPIXEL 0x70044
2262#define PIPE_FRAME_LOW_MASK 0xff000000 2505#define PIPE_FRAME_LOW_MASK 0xff000000
2263#define PIPE_FRAME_LOW_SHIFT 24 2506#define PIPE_FRAME_LOW_SHIFT 24
2264#define PIPE_PIXEL_MASK 0x00ffffff 2507#define PIPE_PIXEL_MASK 0x00ffffff
2265#define PIPE_PIXEL_SHIFT 0 2508#define PIPE_PIXEL_SHIFT 0
2266/* GM45+ just has to be different */ 2509/* GM45+ just has to be different */
2267#define PIPEA_FRMCOUNT_GM45 0x70040 2510#define _PIPEA_FRMCOUNT_GM45 0x70040
2268#define PIPEA_FLIPCOUNT_GM45 0x70044 2511#define _PIPEA_FLIPCOUNT_GM45 0x70044
2512#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2269 2513
2270/* Cursor A & B regs */ 2514/* Cursor A & B regs */
2271#define CURACNTR 0x70080 2515#define _CURACNTR 0x70080
2272/* Old style CUR*CNTR flags (desktop 8xx) */ 2516/* Old style CUR*CNTR flags (desktop 8xx) */
2273#define CURSOR_ENABLE 0x80000000 2517#define CURSOR_ENABLE 0x80000000
2274#define CURSOR_GAMMA_ENABLE 0x40000000 2518#define CURSOR_GAMMA_ENABLE 0x40000000
@@ -2289,19 +2533,23 @@
2289#define MCURSOR_PIPE_A 0x00 2533#define MCURSOR_PIPE_A 0x00
2290#define MCURSOR_PIPE_B (1 << 28) 2534#define MCURSOR_PIPE_B (1 << 28)
2291#define MCURSOR_GAMMA_ENABLE (1 << 26) 2535#define MCURSOR_GAMMA_ENABLE (1 << 26)
2292#define CURABASE 0x70084 2536#define _CURABASE 0x70084
2293#define CURAPOS 0x70088 2537#define _CURAPOS 0x70088
2294#define CURSOR_POS_MASK 0x007FF 2538#define CURSOR_POS_MASK 0x007FF
2295#define CURSOR_POS_SIGN 0x8000 2539#define CURSOR_POS_SIGN 0x8000
2296#define CURSOR_X_SHIFT 0 2540#define CURSOR_X_SHIFT 0
2297#define CURSOR_Y_SHIFT 16 2541#define CURSOR_Y_SHIFT 16
2298#define CURSIZE 0x700a0 2542#define CURSIZE 0x700a0
2299#define CURBCNTR 0x700c0 2543#define _CURBCNTR 0x700c0
2300#define CURBBASE 0x700c4 2544#define _CURBBASE 0x700c4
2301#define CURBPOS 0x700c8 2545#define _CURBPOS 0x700c8
2546
2547#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2548#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2549#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2302 2550
2303/* Display A control */ 2551/* Display A control */
2304#define DSPACNTR 0x70180 2552#define _DSPACNTR 0x70180
2305#define DISPLAY_PLANE_ENABLE (1<<31) 2553#define DISPLAY_PLANE_ENABLE (1<<31)
2306#define DISPLAY_PLANE_DISABLE 0 2554#define DISPLAY_PLANE_DISABLE 0
2307#define DISPPLANE_GAMMA_ENABLE (1<<30) 2555#define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -2315,9 +2563,10 @@
2315#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2563#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2316#define DISPPLANE_STEREO_ENABLE (1<<25) 2564#define DISPPLANE_STEREO_ENABLE (1<<25)
2317#define DISPPLANE_STEREO_DISABLE 0 2565#define DISPPLANE_STEREO_DISABLE 0
2318#define DISPPLANE_SEL_PIPE_MASK (1<<24) 2566#define DISPPLANE_SEL_PIPE_SHIFT 24
2567#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2319#define DISPPLANE_SEL_PIPE_A 0 2568#define DISPPLANE_SEL_PIPE_A 0
2320#define DISPPLANE_SEL_PIPE_B (1<<24) 2569#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2321#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2570#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2322#define DISPPLANE_SRC_KEY_DISABLE 0 2571#define DISPPLANE_SRC_KEY_DISABLE 0
2323#define DISPPLANE_LINE_DOUBLE (1<<20) 2572#define DISPPLANE_LINE_DOUBLE (1<<20)
@@ -2326,12 +2575,20 @@
2326#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2575#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2327#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2576#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2328#define DISPPLANE_TILED (1<<10) 2577#define DISPPLANE_TILED (1<<10)
2329#define DSPAADDR 0x70184 2578#define _DSPAADDR 0x70184
2330#define DSPASTRIDE 0x70188 2579#define _DSPASTRIDE 0x70188
2331#define DSPAPOS 0x7018C /* reserved */ 2580#define _DSPAPOS 0x7018C /* reserved */
2332#define DSPASIZE 0x70190 2581#define _DSPASIZE 0x70190
2333#define DSPASURF 0x7019C /* 965+ only */ 2582#define _DSPASURF 0x7019C /* 965+ only */
2334#define DSPATILEOFF 0x701A4 /* 965+ only */ 2583#define _DSPATILEOFF 0x701A4 /* 965+ only */
2584
2585#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2586#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2587#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2588#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2589#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2590#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2591#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2335 2592
2336/* VBIOS flags */ 2593/* VBIOS flags */
2337#define SWF00 0x71410 2594#define SWF00 0x71410
@@ -2349,27 +2606,27 @@
2349#define SWF32 0x7241c 2606#define SWF32 0x7241c
2350 2607
2351/* Pipe B */ 2608/* Pipe B */
2352#define PIPEBDSL 0x71000 2609#define _PIPEBDSL 0x71000
2353#define PIPEBCONF 0x71008 2610#define _PIPEBCONF 0x71008
2354#define PIPEBSTAT 0x71024 2611#define _PIPEBSTAT 0x71024
2355#define PIPEBFRAMEHIGH 0x71040 2612#define _PIPEBFRAMEHIGH 0x71040
2356#define PIPEBFRAMEPIXEL 0x71044 2613#define _PIPEBFRAMEPIXEL 0x71044
2357#define PIPEB_FRMCOUNT_GM45 0x71040 2614#define _PIPEB_FRMCOUNT_GM45 0x71040
2358#define PIPEB_FLIPCOUNT_GM45 0x71044 2615#define _PIPEB_FLIPCOUNT_GM45 0x71044
2359 2616
2360 2617
2361/* Display B control */ 2618/* Display B control */
2362#define DSPBCNTR 0x71180 2619#define _DSPBCNTR 0x71180
2363#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2620#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2364#define DISPPLANE_ALPHA_TRANS_DISABLE 0 2621#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2365#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2622#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2366#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2623#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2367#define DSPBADDR 0x71184 2624#define _DSPBADDR 0x71184
2368#define DSPBSTRIDE 0x71188 2625#define _DSPBSTRIDE 0x71188
2369#define DSPBPOS 0x7118C 2626#define _DSPBPOS 0x7118C
2370#define DSPBSIZE 0x71190 2627#define _DSPBSIZE 0x71190
2371#define DSPBSURF 0x7119C 2628#define _DSPBSURF 0x7119C
2372#define DSPBTILEOFF 0x711A4 2629#define _DSPBTILEOFF 0x711A4
2373 2630
2374/* VBIOS regs */ 2631/* VBIOS regs */
2375#define VGACNTRL 0x71400 2632#define VGACNTRL 0x71400
@@ -2397,6 +2654,7 @@
2397#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2654#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2398 2655
2399#define FDI_PLL_BIOS_0 0x46000 2656#define FDI_PLL_BIOS_0 0x46000
2657#define FDI_PLL_FB_CLOCK_MASK 0xff
2400#define FDI_PLL_BIOS_1 0x46004 2658#define FDI_PLL_BIOS_1 0x46004
2401#define FDI_PLL_BIOS_2 0x46008 2659#define FDI_PLL_BIOS_2 0x46008
2402#define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2660#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
@@ -2404,6 +2662,8 @@
2404#define DISPLAY_PORT_PLL_BIOS_2 0x46014 2662#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2405 2663
2406#define PCH_DSPCLK_GATE_D 0x42020 2664#define PCH_DSPCLK_GATE_D 0x42020
2665# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2666# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2407# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 2667# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2408# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 2668# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2409 2669
@@ -2411,73 +2671,89 @@
2411# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2671# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2412# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2672# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2413 2673
2674#define PCH_3DCGDIS1 0x46024
2675# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2676
2414#define FDI_PLL_FREQ_CTL 0x46030 2677#define FDI_PLL_FREQ_CTL 0x46030
2415#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2678#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2416#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2679#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2417#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2680#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2418 2681
2419 2682
2420#define PIPEA_DATA_M1 0x60030 2683#define _PIPEA_DATA_M1 0x60030
2421#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2684#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2422#define TU_SIZE_MASK 0x7e000000 2685#define TU_SIZE_MASK 0x7e000000
2423#define PIPEA_DATA_M1_OFFSET 0 2686#define PIPE_DATA_M1_OFFSET 0
2424#define PIPEA_DATA_N1 0x60034 2687#define _PIPEA_DATA_N1 0x60034
2425#define PIPEA_DATA_N1_OFFSET 0 2688#define PIPE_DATA_N1_OFFSET 0
2426 2689
2427#define PIPEA_DATA_M2 0x60038 2690#define _PIPEA_DATA_M2 0x60038
2428#define PIPEA_DATA_M2_OFFSET 0 2691#define PIPE_DATA_M2_OFFSET 0
2429#define PIPEA_DATA_N2 0x6003c 2692#define _PIPEA_DATA_N2 0x6003c
2430#define PIPEA_DATA_N2_OFFSET 0 2693#define PIPE_DATA_N2_OFFSET 0
2431 2694
2432#define PIPEA_LINK_M1 0x60040 2695#define _PIPEA_LINK_M1 0x60040
2433#define PIPEA_LINK_M1_OFFSET 0 2696#define PIPE_LINK_M1_OFFSET 0
2434#define PIPEA_LINK_N1 0x60044 2697#define _PIPEA_LINK_N1 0x60044
2435#define PIPEA_LINK_N1_OFFSET 0 2698#define PIPE_LINK_N1_OFFSET 0
2436 2699
2437#define PIPEA_LINK_M2 0x60048 2700#define _PIPEA_LINK_M2 0x60048
2438#define PIPEA_LINK_M2_OFFSET 0 2701#define PIPE_LINK_M2_OFFSET 0
2439#define PIPEA_LINK_N2 0x6004c 2702#define _PIPEA_LINK_N2 0x6004c
2440#define PIPEA_LINK_N2_OFFSET 0 2703#define PIPE_LINK_N2_OFFSET 0
2441 2704
2442/* PIPEB timing regs are same start from 0x61000 */ 2705/* PIPEB timing regs are same start from 0x61000 */
2443 2706
2444#define PIPEB_DATA_M1 0x61030 2707#define _PIPEB_DATA_M1 0x61030
2445#define PIPEB_DATA_M1_OFFSET 0 2708#define _PIPEB_DATA_N1 0x61034
2446#define PIPEB_DATA_N1 0x61034 2709
2447#define PIPEB_DATA_N1_OFFSET 0 2710#define _PIPEB_DATA_M2 0x61038
2711#define _PIPEB_DATA_N2 0x6103c
2448 2712
2449#define PIPEB_DATA_M2 0x61038 2713#define _PIPEB_LINK_M1 0x61040
2450#define PIPEB_DATA_M2_OFFSET 0 2714#define _PIPEB_LINK_N1 0x61044
2451#define PIPEB_DATA_N2 0x6103c
2452#define PIPEB_DATA_N2_OFFSET 0
2453 2715
2454#define PIPEB_LINK_M1 0x61040 2716#define _PIPEB_LINK_M2 0x61048
2455#define PIPEB_LINK_M1_OFFSET 0 2717#define _PIPEB_LINK_N2 0x6104c
2456#define PIPEB_LINK_N1 0x61044
2457#define PIPEB_LINK_N1_OFFSET 0
2458 2718
2459#define PIPEB_LINK_M2 0x61048 2719#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2460#define PIPEB_LINK_M2_OFFSET 0 2720#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2461#define PIPEB_LINK_N2 0x6104c 2721#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2462#define PIPEB_LINK_N2_OFFSET 0 2722#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2723#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2724#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2725#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2726#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2463 2727
2464/* CPU panel fitter */ 2728/* CPU panel fitter */
2465#define PFA_CTL_1 0x68080 2729/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2466#define PFB_CTL_1 0x68880 2730#define _PFA_CTL_1 0x68080
2731#define _PFB_CTL_1 0x68880
2467#define PF_ENABLE (1<<31) 2732#define PF_ENABLE (1<<31)
2468#define PF_FILTER_MASK (3<<23) 2733#define PF_FILTER_MASK (3<<23)
2469#define PF_FILTER_PROGRAMMED (0<<23) 2734#define PF_FILTER_PROGRAMMED (0<<23)
2470#define PF_FILTER_MED_3x3 (1<<23) 2735#define PF_FILTER_MED_3x3 (1<<23)
2471#define PF_FILTER_EDGE_ENHANCE (2<<23) 2736#define PF_FILTER_EDGE_ENHANCE (2<<23)
2472#define PF_FILTER_EDGE_SOFTEN (3<<23) 2737#define PF_FILTER_EDGE_SOFTEN (3<<23)
2473#define PFA_WIN_SZ 0x68074 2738#define _PFA_WIN_SZ 0x68074
2474#define PFB_WIN_SZ 0x68874 2739#define _PFB_WIN_SZ 0x68874
2475#define PFA_WIN_POS 0x68070 2740#define _PFA_WIN_POS 0x68070
2476#define PFB_WIN_POS 0x68870 2741#define _PFB_WIN_POS 0x68870
2742#define _PFA_VSCALE 0x68084
2743#define _PFB_VSCALE 0x68884
2744#define _PFA_HSCALE 0x68090
2745#define _PFB_HSCALE 0x68890
2746
2747#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2748#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2749#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2750#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2751#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2477 2752
2478/* legacy palette */ 2753/* legacy palette */
2479#define LGC_PALETTE_A 0x4a000 2754#define _LGC_PALETTE_A 0x4a000
2480#define LGC_PALETTE_B 0x4a800 2755#define _LGC_PALETTE_B 0x4a800
2756#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2481 2757
2482/* interrupts */ 2758/* interrupts */
2483#define DE_MASTER_IRQ_CONTROL (1 << 31) 2759#define DE_MASTER_IRQ_CONTROL (1 << 31)
@@ -2506,6 +2782,19 @@
2506#define DE_PIPEA_VSYNC (1 << 3) 2782#define DE_PIPEA_VSYNC (1 << 3)
2507#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2783#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2508 2784
2785/* More Ivybridge lolz */
2786#define DE_ERR_DEBUG_IVB (1<<30)
2787#define DE_GSE_IVB (1<<29)
2788#define DE_PCH_EVENT_IVB (1<<28)
2789#define DE_DP_A_HOTPLUG_IVB (1<<27)
2790#define DE_AUX_CHANNEL_A_IVB (1<<26)
2791#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2792#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2793#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2794#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2795#define DE_PIPEB_VBLANK_IVB (1<<5)
2796#define DE_PIPEA_VBLANK_IVB (1<<0)
2797
2509#define DEISR 0x44000 2798#define DEISR 0x44000
2510#define DEIMR 0x44004 2799#define DEIMR 0x44004
2511#define DEIIR 0x44008 2800#define DEIIR 0x44008
@@ -2516,7 +2805,8 @@
2516#define GT_SYNC_STATUS (1 << 2) 2805#define GT_SYNC_STATUS (1 << 2)
2517#define GT_USER_INTERRUPT (1 << 0) 2806#define GT_USER_INTERRUPT (1 << 0)
2518#define GT_BSD_USER_INTERRUPT (1 << 5) 2807#define GT_BSD_USER_INTERRUPT (1 << 5)
2519 2808#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2809#define GT_BLT_USER_INTERRUPT (1 << 22)
2520 2810
2521#define GTISR 0x44010 2811#define GTISR 0x44010
2522#define GTIMR 0x44014 2812#define GTIMR 0x44014
@@ -2524,10 +2814,22 @@
2524#define GTIER 0x4401c 2814#define GTIER 0x4401c
2525 2815
2526#define ILK_DISPLAY_CHICKEN2 0x42004 2816#define ILK_DISPLAY_CHICKEN2 0x42004
2817/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2818#define ILK_ELPIN_409_SELECT (1 << 25)
2527#define ILK_DPARB_GATE (1<<22) 2819#define ILK_DPARB_GATE (1<<22)
2528#define ILK_VSDPFD_FULL (1<<21) 2820#define ILK_VSDPFD_FULL (1<<21)
2821#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2822#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2823#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2824#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2825#define ILK_HDCP_DISABLE (1<<25)
2826#define ILK_eDP_A_DISABLE (1<<24)
2827#define ILK_DESKTOP (1<<23)
2529#define ILK_DSPCLK_GATE 0x42020 2828#define ILK_DSPCLK_GATE 0x42020
2829#define IVB_VRHUNIT_CLK_GATE (1<<28)
2530#define ILK_DPARB_CLK_GATE (1<<5) 2830#define ILK_DPARB_CLK_GATE (1<<5)
2831#define ILK_DPFD_CLK_GATE (1<<7)
2832
2531/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 2833/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2532#define ILK_CLK_FBC (1<<7) 2834#define ILK_CLK_FBC (1<<7)
2533#define ILK_DPFC_DIS1 (1<<8) 2835#define ILK_DPFC_DIS1 (1<<8)
@@ -2540,17 +2842,50 @@
2540/* PCH */ 2842/* PCH */
2541 2843
2542/* south display engine interrupt */ 2844/* south display engine interrupt */
2845#define SDE_AUDIO_POWER_D (1 << 27)
2846#define SDE_AUDIO_POWER_C (1 << 26)
2847#define SDE_AUDIO_POWER_B (1 << 25)
2848#define SDE_AUDIO_POWER_SHIFT (25)
2849#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2850#define SDE_GMBUS (1 << 24)
2851#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2852#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2853#define SDE_AUDIO_HDCP_MASK (3 << 22)
2854#define SDE_AUDIO_TRANSB (1 << 21)
2855#define SDE_AUDIO_TRANSA (1 << 20)
2856#define SDE_AUDIO_TRANS_MASK (3 << 20)
2857#define SDE_POISON (1 << 19)
2858/* 18 reserved */
2859#define SDE_FDI_RXB (1 << 17)
2860#define SDE_FDI_RXA (1 << 16)
2861#define SDE_FDI_MASK (3 << 16)
2862#define SDE_AUXD (1 << 15)
2863#define SDE_AUXC (1 << 14)
2864#define SDE_AUXB (1 << 13)
2865#define SDE_AUX_MASK (7 << 13)
2866/* 12 reserved */
2543#define SDE_CRT_HOTPLUG (1 << 11) 2867#define SDE_CRT_HOTPLUG (1 << 11)
2544#define SDE_PORTD_HOTPLUG (1 << 10) 2868#define SDE_PORTD_HOTPLUG (1 << 10)
2545#define SDE_PORTC_HOTPLUG (1 << 9) 2869#define SDE_PORTC_HOTPLUG (1 << 9)
2546#define SDE_PORTB_HOTPLUG (1 << 8) 2870#define SDE_PORTB_HOTPLUG (1 << 8)
2547#define SDE_SDVOB_HOTPLUG (1 << 6) 2871#define SDE_SDVOB_HOTPLUG (1 << 6)
2548#define SDE_HOTPLUG_MASK (0xf << 8) 2872#define SDE_HOTPLUG_MASK (0xf << 8)
2873#define SDE_TRANSB_CRC_DONE (1 << 5)
2874#define SDE_TRANSB_CRC_ERR (1 << 4)
2875#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2876#define SDE_TRANSA_CRC_DONE (1 << 2)
2877#define SDE_TRANSA_CRC_ERR (1 << 1)
2878#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2879#define SDE_TRANS_MASK (0x3f)
2549/* CPT */ 2880/* CPT */
2550#define SDE_CRT_HOTPLUG_CPT (1 << 19) 2881#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2551#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2882#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2552#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2883#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2553#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2884#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2885#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2886 SDE_PORTD_HOTPLUG_CPT | \
2887 SDE_PORTC_HOTPLUG_CPT | \
2888 SDE_PORTB_HOTPLUG_CPT)
2554 2889
2555#define SDEISR 0xc4000 2890#define SDEISR 0xc4000
2556#define SDEIMR 0xc4004 2891#define SDEIMR 0xc4004
@@ -2598,13 +2933,17 @@
2598#define PCH_GMBUS4 0xc5110 2933#define PCH_GMBUS4 0xc5110
2599#define PCH_GMBUS5 0xc5120 2934#define PCH_GMBUS5 0xc5120
2600 2935
2601#define PCH_DPLL_A 0xc6014 2936#define _PCH_DPLL_A 0xc6014
2602#define PCH_DPLL_B 0xc6018 2937#define _PCH_DPLL_B 0xc6018
2938#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2603 2939
2604#define PCH_FPA0 0xc6040 2940#define _PCH_FPA0 0xc6040
2605#define PCH_FPA1 0xc6044 2941#define FP_CB_TUNE (0x3<<22)
2606#define PCH_FPB0 0xc6048 2942#define _PCH_FPA1 0xc6044
2607#define PCH_FPB1 0xc604c 2943#define _PCH_FPB0 0xc6048
2944#define _PCH_FPB1 0xc604c
2945#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2946#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2608 2947
2609#define PCH_DPLL_TEST 0xc606c 2948#define PCH_DPLL_TEST 0xc606c
2610 2949
@@ -2623,6 +2962,7 @@
2623#define DREF_NONSPREAD_SOURCE_MASK (3<<9) 2962#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2624#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2963#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2625#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2964#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2965#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2626#define DREF_SSC4_DOWNSPREAD (0<<6) 2966#define DREF_SSC4_DOWNSPREAD (0<<6)
2627#define DREF_SSC4_CENTERSPREAD (1<<6) 2967#define DREF_SSC4_CENTERSPREAD (1<<6)
2628#define DREF_SSC1_DISABLE (0<<1) 2968#define DREF_SSC1_DISABLE (0<<1)
@@ -2655,52 +2995,69 @@
2655 2995
2656/* transcoder */ 2996/* transcoder */
2657 2997
2658#define TRANS_HTOTAL_A 0xe0000 2998#define _TRANS_HTOTAL_A 0xe0000
2659#define TRANS_HTOTAL_SHIFT 16 2999#define TRANS_HTOTAL_SHIFT 16
2660#define TRANS_HACTIVE_SHIFT 0 3000#define TRANS_HACTIVE_SHIFT 0
2661#define TRANS_HBLANK_A 0xe0004 3001#define _TRANS_HBLANK_A 0xe0004
2662#define TRANS_HBLANK_END_SHIFT 16 3002#define TRANS_HBLANK_END_SHIFT 16
2663#define TRANS_HBLANK_START_SHIFT 0 3003#define TRANS_HBLANK_START_SHIFT 0
2664#define TRANS_HSYNC_A 0xe0008 3004#define _TRANS_HSYNC_A 0xe0008
2665#define TRANS_HSYNC_END_SHIFT 16 3005#define TRANS_HSYNC_END_SHIFT 16
2666#define TRANS_HSYNC_START_SHIFT 0 3006#define TRANS_HSYNC_START_SHIFT 0
2667#define TRANS_VTOTAL_A 0xe000c 3007#define _TRANS_VTOTAL_A 0xe000c
2668#define TRANS_VTOTAL_SHIFT 16 3008#define TRANS_VTOTAL_SHIFT 16
2669#define TRANS_VACTIVE_SHIFT 0 3009#define TRANS_VACTIVE_SHIFT 0
2670#define TRANS_VBLANK_A 0xe0010 3010#define _TRANS_VBLANK_A 0xe0010
2671#define TRANS_VBLANK_END_SHIFT 16 3011#define TRANS_VBLANK_END_SHIFT 16
2672#define TRANS_VBLANK_START_SHIFT 0 3012#define TRANS_VBLANK_START_SHIFT 0
2673#define TRANS_VSYNC_A 0xe0014 3013#define _TRANS_VSYNC_A 0xe0014
2674#define TRANS_VSYNC_END_SHIFT 16 3014#define TRANS_VSYNC_END_SHIFT 16
2675#define TRANS_VSYNC_START_SHIFT 0 3015#define TRANS_VSYNC_START_SHIFT 0
2676 3016
2677#define TRANSA_DATA_M1 0xe0030 3017#define _TRANSA_DATA_M1 0xe0030
2678#define TRANSA_DATA_N1 0xe0034 3018#define _TRANSA_DATA_N1 0xe0034
2679#define TRANSA_DATA_M2 0xe0038 3019#define _TRANSA_DATA_M2 0xe0038
2680#define TRANSA_DATA_N2 0xe003c 3020#define _TRANSA_DATA_N2 0xe003c
2681#define TRANSA_DP_LINK_M1 0xe0040 3021#define _TRANSA_DP_LINK_M1 0xe0040
2682#define TRANSA_DP_LINK_N1 0xe0044 3022#define _TRANSA_DP_LINK_N1 0xe0044
2683#define TRANSA_DP_LINK_M2 0xe0048 3023#define _TRANSA_DP_LINK_M2 0xe0048
2684#define TRANSA_DP_LINK_N2 0xe004c 3024#define _TRANSA_DP_LINK_N2 0xe004c
2685 3025
2686#define TRANS_HTOTAL_B 0xe1000 3026#define _TRANS_HTOTAL_B 0xe1000
2687#define TRANS_HBLANK_B 0xe1004 3027#define _TRANS_HBLANK_B 0xe1004
2688#define TRANS_HSYNC_B 0xe1008 3028#define _TRANS_HSYNC_B 0xe1008
2689#define TRANS_VTOTAL_B 0xe100c 3029#define _TRANS_VTOTAL_B 0xe100c
2690#define TRANS_VBLANK_B 0xe1010 3030#define _TRANS_VBLANK_B 0xe1010
2691#define TRANS_VSYNC_B 0xe1014 3031#define _TRANS_VSYNC_B 0xe1014
2692 3032
2693#define TRANSB_DATA_M1 0xe1030 3033#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
2694#define TRANSB_DATA_N1 0xe1034 3034#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
2695#define TRANSB_DATA_M2 0xe1038 3035#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
2696#define TRANSB_DATA_N2 0xe103c 3036#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
2697#define TRANSB_DP_LINK_M1 0xe1040 3037#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
2698#define TRANSB_DP_LINK_N1 0xe1044 3038#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
2699#define TRANSB_DP_LINK_M2 0xe1048 3039
2700#define TRANSB_DP_LINK_N2 0xe104c 3040#define _TRANSB_DATA_M1 0xe1030
2701 3041#define _TRANSB_DATA_N1 0xe1034
2702#define TRANSACONF 0xf0008 3042#define _TRANSB_DATA_M2 0xe1038
2703#define TRANSBCONF 0xf1008 3043#define _TRANSB_DATA_N2 0xe103c
3044#define _TRANSB_DP_LINK_M1 0xe1040
3045#define _TRANSB_DP_LINK_N1 0xe1044
3046#define _TRANSB_DP_LINK_M2 0xe1048
3047#define _TRANSB_DP_LINK_N2 0xe104c
3048
3049#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3050#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3051#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3052#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3053#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3054#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3055#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3056#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3057
3058#define _TRANSACONF 0xf0008
3059#define _TRANSBCONF 0xf1008
3060#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
2704#define TRANS_DISABLE (0<<31) 3061#define TRANS_DISABLE (0<<31)
2705#define TRANS_ENABLE (1<<31) 3062#define TRANS_ENABLE (1<<31)
2706#define TRANS_STATE_MASK (1<<30) 3063#define TRANS_STATE_MASK (1<<30)
@@ -2718,13 +3075,22 @@
2718#define TRANS_6BPC (2<<5) 3075#define TRANS_6BPC (2<<5)
2719#define TRANS_12BPC (3<<5) 3076#define TRANS_12BPC (3<<5)
2720 3077
2721#define FDI_RXA_CHICKEN 0xc200c 3078#define SOUTH_CHICKEN2 0xc2004
2722#define FDI_RXB_CHICKEN 0xc2010 3079#define DPLS_EDP_PPS_FIX_DIS (1<<0)
2723#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 3080
3081#define _FDI_RXA_CHICKEN 0xc200c
3082#define _FDI_RXB_CHICKEN 0xc2010
3083#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3084#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3085#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3086
3087#define SOUTH_DSPCLK_GATE_D 0xc2020
3088#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
2724 3089
2725/* CPU: FDI_TX */ 3090/* CPU: FDI_TX */
2726#define FDI_TXA_CTL 0x60100 3091#define _FDI_TXA_CTL 0x60100
2727#define FDI_TXB_CTL 0x61100 3092#define _FDI_TXB_CTL 0x61100
3093#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
2728#define FDI_TX_DISABLE (0<<31) 3094#define FDI_TX_DISABLE (0<<31)
2729#define FDI_TX_ENABLE (1<<31) 3095#define FDI_TX_ENABLE (1<<31)
2730#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3096#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
@@ -2759,16 +3125,26 @@
2759#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3125#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2760/* Ironlake: hardwired to 1 */ 3126/* Ironlake: hardwired to 1 */
2761#define FDI_TX_PLL_ENABLE (1<<14) 3127#define FDI_TX_PLL_ENABLE (1<<14)
3128
3129/* Ivybridge has different bits for lolz */
3130#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3131#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3132#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3133#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3134
2762/* both Tx and Rx */ 3135/* both Tx and Rx */
3136#define FDI_LINK_TRAIN_AUTO (1<<10)
2763#define FDI_SCRAMBLING_ENABLE (0<<7) 3137#define FDI_SCRAMBLING_ENABLE (0<<7)
2764#define FDI_SCRAMBLING_DISABLE (1<<7) 3138#define FDI_SCRAMBLING_DISABLE (1<<7)
2765 3139
2766/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3140/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2767#define FDI_RXA_CTL 0xf000c 3141#define _FDI_RXA_CTL 0xf000c
2768#define FDI_RXB_CTL 0xf100c 3142#define _FDI_RXB_CTL 0xf100c
3143#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
2769#define FDI_RX_ENABLE (1<<31) 3144#define FDI_RX_ENABLE (1<<31)
2770#define FDI_RX_DISABLE (0<<31)
2771/* train, dp width same as FDI_TX */ 3145/* train, dp width same as FDI_TX */
3146#define FDI_FS_ERRC_ENABLE (1<<27)
3147#define FDI_FE_ERRC_ENABLE (1<<26)
2772#define FDI_DP_PORT_WIDTH_X8 (7<<19) 3148#define FDI_DP_PORT_WIDTH_X8 (7<<19)
2773#define FDI_8BPC (0<<16) 3149#define FDI_8BPC (0<<16)
2774#define FDI_10BPC (1<<16) 3150#define FDI_10BPC (1<<16)
@@ -2782,8 +3158,7 @@
2782#define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3158#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2783#define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3159#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2784#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3160#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2785#define FDI_SEL_RAWCLK (0<<4) 3161#define FDI_PCDCLK (1<<4)
2786#define FDI_SEL_PCDCLK (1<<4)
2787/* CPT */ 3162/* CPT */
2788#define FDI_AUTO_TRAINING (1<<10) 3163#define FDI_AUTO_TRAINING (1<<10)
2789#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3164#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
@@ -2792,12 +3167,15 @@
2792#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3167#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
2793#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3168#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
2794 3169
2795#define FDI_RXA_MISC 0xf0010 3170#define _FDI_RXA_MISC 0xf0010
2796#define FDI_RXB_MISC 0xf1010 3171#define _FDI_RXB_MISC 0xf1010
2797#define FDI_RXA_TUSIZE1 0xf0030 3172#define _FDI_RXA_TUSIZE1 0xf0030
2798#define FDI_RXA_TUSIZE2 0xf0038 3173#define _FDI_RXA_TUSIZE2 0xf0038
2799#define FDI_RXB_TUSIZE1 0xf1030 3174#define _FDI_RXB_TUSIZE1 0xf1030
2800#define FDI_RXB_TUSIZE2 0xf1038 3175#define _FDI_RXB_TUSIZE2 0xf1038
3176#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3177#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3178#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
2801 3179
2802/* FDI_RX interrupt register format */ 3180/* FDI_RX interrupt register format */
2803#define FDI_RX_INTER_LANE_ALIGN (1<<10) 3181#define FDI_RX_INTER_LANE_ALIGN (1<<10)
@@ -2812,10 +3190,12 @@
2812#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3190#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2813#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3191#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2814 3192
2815#define FDI_RXA_IIR 0xf0014 3193#define _FDI_RXA_IIR 0xf0014
2816#define FDI_RXA_IMR 0xf0018 3194#define _FDI_RXA_IMR 0xf0018
2817#define FDI_RXB_IIR 0xf1014 3195#define _FDI_RXB_IIR 0xf1014
2818#define FDI_RXB_IMR 0xf1018 3196#define _FDI_RXB_IMR 0xf1018
3197#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3198#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
2819 3199
2820#define FDI_PLL_CTL_1 0xfe000 3200#define FDI_PLL_CTL_1 0xfe000
2821#define FDI_PLL_CTL_2 0xfe004 3201#define FDI_PLL_CTL_2 0xfe004
@@ -2845,11 +3225,15 @@
2845#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3225#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2846#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3226#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2847 3227
3228#define ADPA_PIPE_ENABLED(V, P) \
3229 (((V) & (ADPA_TRANS_SELECT_MASK | ADPA_DAC_ENABLE)) == ((P) << 30 | ADPA_DAC_ENABLE))
3230
2848/* or SDVOB */ 3231/* or SDVOB */
2849#define HDMIB 0xe1140 3232#define HDMIB 0xe1140
2850#define PORT_ENABLE (1 << 31) 3233#define PORT_ENABLE (1 << 31)
2851#define TRANSCODER_A (0) 3234#define TRANSCODER_A (0)
2852#define TRANSCODER_B (1 << 30) 3235#define TRANSCODER_B (1 << 30)
3236#define TRANSCODER_MASK (1 << 30)
2853#define COLOR_FORMAT_8bpc (0) 3237#define COLOR_FORMAT_8bpc (0)
2854#define COLOR_FORMAT_12bpc (3 << 26) 3238#define COLOR_FORMAT_12bpc (3 << 26)
2855#define SDVOB_HOTPLUG_ENABLE (1 << 23) 3239#define SDVOB_HOTPLUG_ENABLE (1 << 23)
@@ -2865,6 +3249,9 @@
2865#define HSYNC_ACTIVE_HIGH (1 << 3) 3249#define HSYNC_ACTIVE_HIGH (1 << 3)
2866#define PORT_DETECTED (1 << 2) 3250#define PORT_DETECTED (1 << 2)
2867 3251
3252#define HDMI_PIPE_ENABLED(V, P) \
3253 (((V) & (TRANSCODER_MASK | PORT_ENABLE)) == ((P) << 30 | PORT_ENABLE))
3254
2868/* PCH SDVOB multiplex with HDMIB */ 3255/* PCH SDVOB multiplex with HDMIB */
2869#define PCH_SDVOB HDMIB 3256#define PCH_SDVOB HDMIB
2870 3257
@@ -2935,10 +3322,12 @@
2935#define TRANS_DP_CTL_A 0xe0300 3322#define TRANS_DP_CTL_A 0xe0300
2936#define TRANS_DP_CTL_B 0xe1300 3323#define TRANS_DP_CTL_B 0xe1300
2937#define TRANS_DP_CTL_C 0xe2300 3324#define TRANS_DP_CTL_C 0xe2300
3325#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
2938#define TRANS_DP_OUTPUT_ENABLE (1<<31) 3326#define TRANS_DP_OUTPUT_ENABLE (1<<31)
2939#define TRANS_DP_PORT_SEL_B (0<<29) 3327#define TRANS_DP_PORT_SEL_B (0<<29)
2940#define TRANS_DP_PORT_SEL_C (1<<29) 3328#define TRANS_DP_PORT_SEL_C (1<<29)
2941#define TRANS_DP_PORT_SEL_D (2<<29) 3329#define TRANS_DP_PORT_SEL_D (2<<29)
3330#define TRANS_DP_PORT_SEL_NONE (3<<29)
2942#define TRANS_DP_PORT_SEL_MASK (3<<29) 3331#define TRANS_DP_PORT_SEL_MASK (3<<29)
2943#define TRANS_DP_AUDIO_ONLY (1<<26) 3332#define TRANS_DP_AUDIO_ONLY (1<<26)
2944#define TRANS_DP_ENH_FRAMING (1<<18) 3333#define TRANS_DP_ENH_FRAMING (1<<18)
@@ -2946,6 +3335,7 @@
2946#define TRANS_DP_10BPC (1<<9) 3335#define TRANS_DP_10BPC (1<<9)
2947#define TRANS_DP_6BPC (2<<9) 3336#define TRANS_DP_6BPC (2<<9)
2948#define TRANS_DP_12BPC (3<<9) 3337#define TRANS_DP_12BPC (3<<9)
3338#define TRANS_DP_BPC_MASK (3<<9)
2949#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3339#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
2950#define TRANS_DP_VSYNC_ACTIVE_LOW 0 3340#define TRANS_DP_VSYNC_ACTIVE_LOW 0
2951#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3341#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
@@ -2959,10 +3349,92 @@
2959#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3349#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
2960#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3350#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
2961/* SNB B-stepping */ 3351/* SNB B-stepping */
2962#define EDP_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3352#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
2963#define EDP_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3353#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
2964#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3354#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
2965#define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3355#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3356#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
2966#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3357#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
2967 3358
3359#define FORCEWAKE 0xA18C
3360#define FORCEWAKE_ACK 0x130090
3361
3362#define GT_FIFO_FREE_ENTRIES 0x120008
3363
3364#define GEN6_RPNSWREQ 0xA008
3365#define GEN6_TURBO_DISABLE (1<<31)
3366#define GEN6_FREQUENCY(x) ((x)<<25)
3367#define GEN6_OFFSET(x) ((x)<<19)
3368#define GEN6_AGGRESSIVE_TURBO (0<<15)
3369#define GEN6_RC_VIDEO_FREQ 0xA00C
3370#define GEN6_RC_CONTROL 0xA090
3371#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3372#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3373#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3374#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3375#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3376#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3377#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3378#define GEN6_RP_DOWN_TIMEOUT 0xA010
3379#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3380#define GEN6_RPSTAT1 0xA01C
3381#define GEN6_CAGF_SHIFT 8
3382#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3383#define GEN6_RP_CONTROL 0xA024
3384#define GEN6_RP_MEDIA_TURBO (1<<11)
3385#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3386#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3387#define GEN6_RP_ENABLE (1<<7)
3388#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3389#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3390#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3391#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3392#define GEN6_RP_UP_THRESHOLD 0xA02C
3393#define GEN6_RP_DOWN_THRESHOLD 0xA030
3394#define GEN6_RP_CUR_UP_EI 0xA050
3395#define GEN6_CURICONT_MASK 0xffffff
3396#define GEN6_RP_CUR_UP 0xA054
3397#define GEN6_CURBSYTAVG_MASK 0xffffff
3398#define GEN6_RP_PREV_UP 0xA058
3399#define GEN6_RP_CUR_DOWN_EI 0xA05C
3400#define GEN6_CURIAVG_MASK 0xffffff
3401#define GEN6_RP_CUR_DOWN 0xA060
3402#define GEN6_RP_PREV_DOWN 0xA064
3403#define GEN6_RP_UP_EI 0xA068
3404#define GEN6_RP_DOWN_EI 0xA06C
3405#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3406#define GEN6_RC_STATE 0xA094
3407#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3408#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3409#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3410#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3411#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3412#define GEN6_RC_SLEEP 0xA0B0
3413#define GEN6_RC1e_THRESHOLD 0xA0B4
3414#define GEN6_RC6_THRESHOLD 0xA0B8
3415#define GEN6_RC6p_THRESHOLD 0xA0BC
3416#define GEN6_RC6pp_THRESHOLD 0xA0C0
3417#define GEN6_PMINTRMSK 0xA168
3418
3419#define GEN6_PMISR 0x44020
3420#define GEN6_PMIMR 0x44024 /* rps_lock */
3421#define GEN6_PMIIR 0x44028
3422#define GEN6_PMIER 0x4402C
3423#define GEN6_PM_MBOX_EVENT (1<<25)
3424#define GEN6_PM_THERMAL_EVENT (1<<24)
3425#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3426#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3427#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3428#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3429#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3430#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3431 GEN6_PM_RP_DOWN_THRESHOLD | \
3432 GEN6_PM_RP_DOWN_TIMEOUT)
3433
3434#define GEN6_PCODE_MAILBOX 0x138124
3435#define GEN6_PCODE_READY (1<<31)
3436#define GEN6_READ_OC_PARAMS 0xc
3437#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x9
3438#define GEN6_PCODE_DATA 0x138128
3439
2968#endif /* _I915_REG_H_ */ 3440#endif /* _I915_REG_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 18:15:08 -0400