diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4f5e15577e89..7103d24c8213 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -2551,6 +2551,10 @@ | |||
| 2551 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) | 2551 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
| 2552 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) | 2552 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
| 2553 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) | 2553 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
| 2554 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ | ||
| 2555 | SDE_PORTD_HOTPLUG_CPT | \ | ||
| 2556 | SDE_PORTC_HOTPLUG_CPT | \ | ||
| 2557 | SDE_PORTB_HOTPLUG_CPT) | ||
| 2554 | 2558 | ||
| 2555 | #define SDEISR 0xc4000 | 2559 | #define SDEISR 0xc4000 |
| 2556 | #define SDEIMR 0xc4004 | 2560 | #define SDEIMR 0xc4004 |
| @@ -2722,6 +2726,9 @@ | |||
| 2722 | #define FDI_RXB_CHICKEN 0xc2010 | 2726 | #define FDI_RXB_CHICKEN 0xc2010 |
| 2723 | #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) | 2727 | #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) |
| 2724 | 2728 | ||
| 2729 | #define SOUTH_DSPCLK_GATE_D 0xc2020 | ||
| 2730 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) | ||
| 2731 | |||
| 2725 | /* CPU: FDI_TX */ | 2732 | /* CPU: FDI_TX */ |
| 2726 | #define FDI_TXA_CTL 0x60100 | 2733 | #define FDI_TXA_CTL 0x60100 |
| 2727 | #define FDI_TXB_CTL 0x61100 | 2734 | #define FDI_TXB_CTL 0x61100 |
| @@ -2946,6 +2953,7 @@ | |||
| 2946 | #define TRANS_DP_10BPC (1<<9) | 2953 | #define TRANS_DP_10BPC (1<<9) |
| 2947 | #define TRANS_DP_6BPC (2<<9) | 2954 | #define TRANS_DP_6BPC (2<<9) |
| 2948 | #define TRANS_DP_12BPC (3<<9) | 2955 | #define TRANS_DP_12BPC (3<<9) |
| 2956 | #define TRANS_DP_BPC_MASK (3<<9) | ||
| 2949 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) | 2957 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
| 2950 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | 2958 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
| 2951 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | 2959 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
| @@ -2959,10 +2967,11 @@ | |||
| 2959 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | 2967 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
| 2960 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | 2968 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
| 2961 | /* SNB B-stepping */ | 2969 | /* SNB B-stepping */ |
| 2962 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) | 2970 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
| 2963 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) | 2971 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) |
| 2964 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) | 2972 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) |
| 2965 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) | 2973 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) |
| 2974 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) | ||
| 2966 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) | 2975 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
| 2967 | 2976 | ||
| 2968 | #endif /* _I915_REG_H_ */ | 2977 | #endif /* _I915_REG_H_ */ |