diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 280 |
1 files changed, 243 insertions, 37 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1687edf68795..4cbc5210fd30 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -53,6 +53,25 @@ | |||
| 53 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | 53 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) |
| 54 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | 54 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) |
| 55 | 55 | ||
| 56 | #define SNB_GMCH_CTRL 0x50 | ||
| 57 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 | ||
| 58 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) | ||
| 59 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) | ||
| 60 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) | ||
| 61 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) | ||
| 62 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) | ||
| 63 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) | ||
| 64 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) | ||
| 65 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) | ||
| 66 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) | ||
| 67 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) | ||
| 68 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) | ||
| 69 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) | ||
| 70 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) | ||
| 71 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | ||
| 72 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | ||
| 73 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | ||
| 74 | |||
| 56 | /* PCI config space */ | 75 | /* PCI config space */ |
| 57 | 76 | ||
| 58 | #define HPLLCC 0xc0 /* 855 only */ | 77 | #define HPLLCC 0xc0 /* 855 only */ |
| @@ -61,6 +80,7 @@ | |||
| 61 | #define GC_CLOCK_100_200 (1 << 0) | 80 | #define GC_CLOCK_100_200 (1 << 0) |
| 62 | #define GC_CLOCK_100_133 (2 << 0) | 81 | #define GC_CLOCK_100_133 (2 << 0) |
| 63 | #define GC_CLOCK_166_250 (3 << 0) | 82 | #define GC_CLOCK_166_250 (3 << 0) |
| 83 | #define GCFGC2 0xda | ||
| 64 | #define GCFGC 0xf0 /* 915+ only */ | 84 | #define GCFGC 0xf0 /* 915+ only */ |
| 65 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | 85 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
| 66 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | 86 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
| @@ -140,6 +160,7 @@ | |||
| 140 | #define MI_NOOP MI_INSTR(0, 0) | 160 | #define MI_NOOP MI_INSTR(0, 0) |
| 141 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) | 161 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
| 142 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) | 162 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) |
| 163 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) | ||
| 143 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) | 164 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
| 144 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | 165 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
| 145 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | 166 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
| @@ -151,7 +172,13 @@ | |||
| 151 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | 172 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
| 152 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) | 173 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
| 153 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) | 174 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
| 175 | #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) | ||
| 176 | #define MI_OVERLAY_CONTINUE (0x0<<21) | ||
| 177 | #define MI_OVERLAY_ON (0x1<<21) | ||
| 178 | #define MI_OVERLAY_OFF (0x2<<21) | ||
| 154 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) | 179 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
| 180 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) | ||
| 181 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) | ||
| 155 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) | 182 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
| 156 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ | 183 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
| 157 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | 184 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
| @@ -203,6 +230,16 @@ | |||
| 203 | #define ASYNC_FLIP (1<<22) | 230 | #define ASYNC_FLIP (1<<22) |
| 204 | #define DISPLAY_PLANE_A (0<<20) | 231 | #define DISPLAY_PLANE_A (0<<20) |
| 205 | #define DISPLAY_PLANE_B (1<<20) | 232 | #define DISPLAY_PLANE_B (1<<20) |
| 233 | #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) | ||
| 234 | #define PIPE_CONTROL_QW_WRITE (1<<14) | ||
| 235 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) | ||
| 236 | #define PIPE_CONTROL_WC_FLUSH (1<<12) | ||
| 237 | #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ | ||
| 238 | #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ | ||
| 239 | #define PIPE_CONTROL_ISP_DIS (1<<9) | ||
| 240 | #define PIPE_CONTROL_NOTIFY (1<<8) | ||
| 241 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ | ||
| 242 | #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ | ||
| 206 | 243 | ||
| 207 | /* | 244 | /* |
| 208 | * Fence registers | 245 | * Fence registers |
| @@ -214,7 +251,7 @@ | |||
| 214 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) | 251 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
| 215 | #define I830_FENCE_PITCH_SHIFT 4 | 252 | #define I830_FENCE_PITCH_SHIFT 4 |
| 216 | #define I830_FENCE_REG_VALID (1<<0) | 253 | #define I830_FENCE_REG_VALID (1<<0) |
| 217 | #define I915_FENCE_MAX_PITCH_VAL 0x10 | 254 | #define I915_FENCE_MAX_PITCH_VAL 4 |
| 218 | #define I830_FENCE_MAX_PITCH_VAL 6 | 255 | #define I830_FENCE_MAX_PITCH_VAL 6 |
| 219 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) | 256 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
| 220 | 257 | ||
| @@ -227,6 +264,9 @@ | |||
| 227 | #define I965_FENCE_REG_VALID (1<<0) | 264 | #define I965_FENCE_REG_VALID (1<<0) |
| 228 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 | 265 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
| 229 | 266 | ||
| 267 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 | ||
| 268 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 | ||
| 269 | |||
| 230 | /* | 270 | /* |
| 231 | * Instruction and interrupt control regs | 271 | * Instruction and interrupt control regs |
| 232 | */ | 272 | */ |
| @@ -258,13 +298,20 @@ | |||
| 258 | #define INSTDONE1 0x0207c /* 965+ only */ | 298 | #define INSTDONE1 0x0207c /* 965+ only */ |
| 259 | #define ACTHD_I965 0x02074 | 299 | #define ACTHD_I965 0x02074 |
| 260 | #define HWS_PGA 0x02080 | 300 | #define HWS_PGA 0x02080 |
| 301 | #define HWS_PGA_GEN6 0x04080 | ||
| 261 | #define HWS_ADDRESS_MASK 0xfffff000 | 302 | #define HWS_ADDRESS_MASK 0xfffff000 |
| 262 | #define HWS_START_ADDRESS_SHIFT 4 | 303 | #define HWS_START_ADDRESS_SHIFT 4 |
| 304 | #define PWRCTXA 0x2088 /* 965GM+ only */ | ||
| 305 | #define PWRCTX_EN (1<<0) | ||
| 263 | #define IPEIR 0x02088 | 306 | #define IPEIR 0x02088 |
| 264 | #define IPEHR 0x0208c | 307 | #define IPEHR 0x0208c |
| 265 | #define INSTDONE 0x02090 | 308 | #define INSTDONE 0x02090 |
| 266 | #define NOPID 0x02094 | 309 | #define NOPID 0x02094 |
| 267 | #define HWSTAM 0x02098 | 310 | #define HWSTAM 0x02098 |
| 311 | |||
| 312 | #define MI_MODE 0x0209c | ||
| 313 | # define VS_TIMER_DISPATCH (1 << 6) | ||
| 314 | |||
| 268 | #define SCPD0 0x0209c /* 915+ only */ | 315 | #define SCPD0 0x0209c /* 915+ only */ |
| 269 | #define IER 0x020a0 | 316 | #define IER 0x020a0 |
| 270 | #define IIR 0x020a4 | 317 | #define IIR 0x020a4 |
| @@ -273,7 +320,7 @@ | |||
| 273 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) | 320 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
| 274 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | 321 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
| 275 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | 322 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
| 276 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) | 323 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
| 277 | #define I915_HWB_OOM_INTERRUPT (1<<13) | 324 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
| 278 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) | 325 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) |
| 279 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) | 326 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
| @@ -297,11 +344,14 @@ | |||
| 297 | #define I915_ERROR_MEMORY_REFRESH (1<<1) | 344 | #define I915_ERROR_MEMORY_REFRESH (1<<1) |
| 298 | #define I915_ERROR_INSTRUCTION (1<<0) | 345 | #define I915_ERROR_INSTRUCTION (1<<0) |
| 299 | #define INSTPM 0x020c0 | 346 | #define INSTPM 0x020c0 |
| 347 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ | ||
| 300 | #define ACTHD 0x020c8 | 348 | #define ACTHD 0x020c8 |
| 301 | #define FW_BLC 0x020d8 | 349 | #define FW_BLC 0x020d8 |
| 302 | #define FW_BLC2 0x020dc | 350 | #define FW_BLC2 0x020dc |
| 303 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ | 351 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
| 304 | #define FW_BLC_SELF_EN (1<<15) | 352 | #define FW_BLC_SELF_EN_MASK (1<<31) |
| 353 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ | ||
| 354 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ | ||
| 305 | #define MM_BURST_LENGTH 0x00700000 | 355 | #define MM_BURST_LENGTH 0x00700000 |
| 306 | #define MM_FIFO_WATERMARK 0x0001F000 | 356 | #define MM_FIFO_WATERMARK 0x0001F000 |
| 307 | #define LM_BURST_LENGTH 0x00000700 | 357 | #define LM_BURST_LENGTH 0x00000700 |
| @@ -315,6 +365,7 @@ | |||
| 315 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | 365 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
| 316 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | 366 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
| 317 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | 367 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
| 368 | #define BB_ADDR 0x02140 /* 8 bytes */ | ||
| 318 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ | 369 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
| 319 | 370 | ||
| 320 | 371 | ||
| @@ -329,6 +380,7 @@ | |||
| 329 | #define FBC_CTL_PERIODIC (1<<30) | 380 | #define FBC_CTL_PERIODIC (1<<30) |
| 330 | #define FBC_CTL_INTERVAL_SHIFT (16) | 381 | #define FBC_CTL_INTERVAL_SHIFT (16) |
| 331 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | 382 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
| 383 | #define FBC_CTL_C3_IDLE (1<<13) | ||
| 332 | #define FBC_CTL_STRIDE_SHIFT (5) | 384 | #define FBC_CTL_STRIDE_SHIFT (5) |
| 333 | #define FBC_CTL_FENCENO (1<<0) | 385 | #define FBC_CTL_FENCENO (1<<0) |
| 334 | #define FBC_COMMAND 0x0320c | 386 | #define FBC_COMMAND 0x0320c |
| @@ -405,6 +457,13 @@ | |||
| 405 | # define GPIO_DATA_VAL_IN (1 << 12) | 457 | # define GPIO_DATA_VAL_IN (1 << 12) |
| 406 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | 458 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
| 407 | 459 | ||
| 460 | #define GMBUS0 0x5100 | ||
| 461 | #define GMBUS1 0x5104 | ||
| 462 | #define GMBUS2 0x5108 | ||
| 463 | #define GMBUS3 0x510c | ||
| 464 | #define GMBUS4 0x5110 | ||
| 465 | #define GMBUS5 0x5120 | ||
| 466 | |||
| 408 | /* | 467 | /* |
| 409 | * Clock control & power management | 468 | * Clock control & power management |
| 410 | */ | 469 | */ |
| @@ -435,7 +494,7 @@ | |||
| 435 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | 494 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 436 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | 495 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
| 437 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | 496 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
| 438 | #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ | 497 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
| 439 | 498 | ||
| 440 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) | 499 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) |
| 441 | #define I915_CRC_ERROR_ENABLE (1UL<<29) | 500 | #define I915_CRC_ERROR_ENABLE (1UL<<29) |
| @@ -512,7 +571,7 @@ | |||
| 512 | */ | 571 | */ |
| 513 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | 572 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
| 514 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | 573 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
| 515 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 | 574 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
| 516 | /* i830, required in DVO non-gang */ | 575 | /* i830, required in DVO non-gang */ |
| 517 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | 576 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) |
| 518 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | 577 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
| @@ -522,7 +581,7 @@ | |||
| 522 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | 581 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
| 523 | #define PLL_REF_INPUT_MASK (3 << 13) | 582 | #define PLL_REF_INPUT_MASK (3 << 13) |
| 524 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | 583 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
| 525 | /* IGDNG */ | 584 | /* Ironlake */ |
| 526 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 | 585 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
| 527 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) | 586 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
| 528 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) | 587 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) |
| @@ -586,12 +645,12 @@ | |||
| 586 | #define FPB0 0x06048 | 645 | #define FPB0 0x06048 |
| 587 | #define FPB1 0x0604c | 646 | #define FPB1 0x0604c |
| 588 | #define FP_N_DIV_MASK 0x003f0000 | 647 | #define FP_N_DIV_MASK 0x003f0000 |
| 589 | #define FP_N_IGD_DIV_MASK 0x00ff0000 | 648 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
| 590 | #define FP_N_DIV_SHIFT 16 | 649 | #define FP_N_DIV_SHIFT 16 |
| 591 | #define FP_M1_DIV_MASK 0x00003f00 | 650 | #define FP_M1_DIV_MASK 0x00003f00 |
| 592 | #define FP_M1_DIV_SHIFT 8 | 651 | #define FP_M1_DIV_SHIFT 8 |
| 593 | #define FP_M2_DIV_MASK 0x0000003f | 652 | #define FP_M2_DIV_MASK 0x0000003f |
| 594 | #define FP_M2_IGD_DIV_MASK 0x000000ff | 653 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
| 595 | #define FP_M2_DIV_SHIFT 0 | 654 | #define FP_M2_DIV_SHIFT 0 |
| 596 | #define DPLL_TEST 0x606c | 655 | #define DPLL_TEST 0x606c |
| 597 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | 656 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
| @@ -767,9 +826,144 @@ | |||
| 767 | #define CLKCFG_MEM_800 (3 << 4) | 826 | #define CLKCFG_MEM_800 (3 << 4) |
| 768 | #define CLKCFG_MEM_MASK (7 << 4) | 827 | #define CLKCFG_MEM_MASK (7 << 4) |
| 769 | 828 | ||
| 770 | /** GM965 GM45 render standby register */ | 829 | #define CRSTANDVID 0x11100 |
| 771 | #define MCHBAR_RENDER_STANDBY 0x111B8 | 830 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
| 772 | 831 | #define PXVFREQ_PX_MASK 0x7f000000 | |
| 832 | #define PXVFREQ_PX_SHIFT 24 | ||
| 833 | #define VIDFREQ_BASE 0x11110 | ||
| 834 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ | ||
| 835 | #define VIDFREQ2 0x11114 | ||
| 836 | #define VIDFREQ3 0x11118 | ||
| 837 | #define VIDFREQ4 0x1111c | ||
| 838 | #define VIDFREQ_P0_MASK 0x1f000000 | ||
| 839 | #define VIDFREQ_P0_SHIFT 24 | ||
| 840 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 | ||
| 841 | #define VIDFREQ_P0_CSCLK_SHIFT 20 | ||
| 842 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 | ||
| 843 | #define VIDFREQ_P0_CRCLK_SHIFT 16 | ||
| 844 | #define VIDFREQ_P1_MASK 0x00001f00 | ||
| 845 | #define VIDFREQ_P1_SHIFT 8 | ||
| 846 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 | ||
| 847 | #define VIDFREQ_P1_CSCLK_SHIFT 4 | ||
| 848 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f | ||
| 849 | #define INTTOEXT_BASE_ILK 0x11300 | ||
| 850 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ | ||
| 851 | #define INTTOEXT_MAP3_SHIFT 24 | ||
| 852 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) | ||
| 853 | #define INTTOEXT_MAP2_SHIFT 16 | ||
| 854 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) | ||
| 855 | #define INTTOEXT_MAP1_SHIFT 8 | ||
| 856 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) | ||
| 857 | #define INTTOEXT_MAP0_SHIFT 0 | ||
| 858 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) | ||
| 859 | #define MEMSWCTL 0x11170 /* Ironlake only */ | ||
| 860 | #define MEMCTL_CMD_MASK 0xe000 | ||
| 861 | #define MEMCTL_CMD_SHIFT 13 | ||
| 862 | #define MEMCTL_CMD_RCLK_OFF 0 | ||
| 863 | #define MEMCTL_CMD_RCLK_ON 1 | ||
| 864 | #define MEMCTL_CMD_CHFREQ 2 | ||
| 865 | #define MEMCTL_CMD_CHVID 3 | ||
| 866 | #define MEMCTL_CMD_VMMOFF 4 | ||
| 867 | #define MEMCTL_CMD_VMMON 5 | ||
| 868 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears | ||
| 869 | when command complete */ | ||
| 870 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ | ||
| 871 | #define MEMCTL_FREQ_SHIFT 8 | ||
| 872 | #define MEMCTL_SFCAVM (1<<7) | ||
| 873 | #define MEMCTL_TGT_VID_MASK 0x007f | ||
| 874 | #define MEMIHYST 0x1117c | ||
| 875 | #define MEMINTREN 0x11180 /* 16 bits */ | ||
| 876 | #define MEMINT_RSEXIT_EN (1<<8) | ||
| 877 | #define MEMINT_CX_SUPR_EN (1<<7) | ||
| 878 | #define MEMINT_CONT_BUSY_EN (1<<6) | ||
| 879 | #define MEMINT_AVG_BUSY_EN (1<<5) | ||
| 880 | #define MEMINT_EVAL_CHG_EN (1<<4) | ||
| 881 | #define MEMINT_MON_IDLE_EN (1<<3) | ||
| 882 | #define MEMINT_UP_EVAL_EN (1<<2) | ||
| 883 | #define MEMINT_DOWN_EVAL_EN (1<<1) | ||
| 884 | #define MEMINT_SW_CMD_EN (1<<0) | ||
| 885 | #define MEMINTRSTR 0x11182 /* 16 bits */ | ||
| 886 | #define MEM_RSEXIT_MASK 0xc000 | ||
| 887 | #define MEM_RSEXIT_SHIFT 14 | ||
| 888 | #define MEM_CONT_BUSY_MASK 0x3000 | ||
| 889 | #define MEM_CONT_BUSY_SHIFT 12 | ||
| 890 | #define MEM_AVG_BUSY_MASK 0x0c00 | ||
| 891 | #define MEM_AVG_BUSY_SHIFT 10 | ||
| 892 | #define MEM_EVAL_CHG_MASK 0x0300 | ||
| 893 | #define MEM_EVAL_BUSY_SHIFT 8 | ||
| 894 | #define MEM_MON_IDLE_MASK 0x00c0 | ||
| 895 | #define MEM_MON_IDLE_SHIFT 6 | ||
| 896 | #define MEM_UP_EVAL_MASK 0x0030 | ||
| 897 | #define MEM_UP_EVAL_SHIFT 4 | ||
| 898 | #define MEM_DOWN_EVAL_MASK 0x000c | ||
| 899 | #define MEM_DOWN_EVAL_SHIFT 2 | ||
| 900 | #define MEM_SW_CMD_MASK 0x0003 | ||
| 901 | #define MEM_INT_STEER_GFX 0 | ||
| 902 | #define MEM_INT_STEER_CMR 1 | ||
| 903 | #define MEM_INT_STEER_SMI 2 | ||
| 904 | #define MEM_INT_STEER_SCI 3 | ||
| 905 | #define MEMINTRSTS 0x11184 | ||
| 906 | #define MEMINT_RSEXIT (1<<7) | ||
| 907 | #define MEMINT_CONT_BUSY (1<<6) | ||
| 908 | #define MEMINT_AVG_BUSY (1<<5) | ||
| 909 | #define MEMINT_EVAL_CHG (1<<4) | ||
| 910 | #define MEMINT_MON_IDLE (1<<3) | ||
| 911 | #define MEMINT_UP_EVAL (1<<2) | ||
| 912 | #define MEMINT_DOWN_EVAL (1<<1) | ||
| 913 | #define MEMINT_SW_CMD (1<<0) | ||
| 914 | #define MEMMODECTL 0x11190 | ||
| 915 | #define MEMMODE_BOOST_EN (1<<31) | ||
| 916 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ | ||
| 917 | #define MEMMODE_BOOST_FREQ_SHIFT 24 | ||
| 918 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 | ||
| 919 | #define MEMMODE_IDLE_MODE_SHIFT 16 | ||
| 920 | #define MEMMODE_IDLE_MODE_EVAL 0 | ||
| 921 | #define MEMMODE_IDLE_MODE_CONT 1 | ||
| 922 | #define MEMMODE_HWIDLE_EN (1<<15) | ||
| 923 | #define MEMMODE_SWMODE_EN (1<<14) | ||
| 924 | #define MEMMODE_RCLK_GATE (1<<13) | ||
| 925 | #define MEMMODE_HW_UPDATE (1<<12) | ||
| 926 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ | ||
| 927 | #define MEMMODE_FSTART_SHIFT 8 | ||
| 928 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ | ||
| 929 | #define MEMMODE_FMAX_SHIFT 4 | ||
| 930 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ | ||
| 931 | #define RCBMAXAVG 0x1119c | ||
| 932 | #define MEMSWCTL2 0x1119e /* Cantiga only */ | ||
| 933 | #define SWMEMCMD_RENDER_OFF (0 << 13) | ||
| 934 | #define SWMEMCMD_RENDER_ON (1 << 13) | ||
| 935 | #define SWMEMCMD_SWFREQ (2 << 13) | ||
| 936 | #define SWMEMCMD_TARVID (3 << 13) | ||
| 937 | #define SWMEMCMD_VRM_OFF (4 << 13) | ||
| 938 | #define SWMEMCMD_VRM_ON (5 << 13) | ||
| 939 | #define CMDSTS (1<<12) | ||
| 940 | #define SFCAVM (1<<11) | ||
| 941 | #define SWFREQ_MASK 0x0380 /* P0-7 */ | ||
| 942 | #define SWFREQ_SHIFT 7 | ||
| 943 | #define TARVID_MASK 0x001f | ||
| 944 | #define MEMSTAT_CTG 0x111a0 | ||
| 945 | #define RCBMINAVG 0x111a0 | ||
| 946 | #define RCUPEI 0x111b0 | ||
| 947 | #define RCDNEI 0x111b4 | ||
| 948 | #define MCHBAR_RENDER_STANDBY 0x111b8 | ||
| 949 | #define RCX_SW_EXIT (1<<23) | ||
| 950 | #define RSX_STATUS_MASK 0x00700000 | ||
| 951 | #define VIDCTL 0x111c0 | ||
| 952 | #define VIDSTS 0x111c8 | ||
| 953 | #define VIDSTART 0x111cc /* 8 bits */ | ||
| 954 | #define MEMSTAT_ILK 0x111f8 | ||
| 955 | #define MEMSTAT_VID_MASK 0x7f00 | ||
| 956 | #define MEMSTAT_VID_SHIFT 8 | ||
| 957 | #define MEMSTAT_PSTATE_MASK 0x00f8 | ||
| 958 | #define MEMSTAT_PSTATE_SHIFT 3 | ||
| 959 | #define MEMSTAT_MON_ACTV (1<<2) | ||
| 960 | #define MEMSTAT_SRC_CTL_MASK 0x0003 | ||
| 961 | #define MEMSTAT_SRC_CTL_CORE 0 | ||
| 962 | #define MEMSTAT_SRC_CTL_TRB 1 | ||
| 963 | #define MEMSTAT_SRC_CTL_THM 2 | ||
| 964 | #define MEMSTAT_SRC_CTL_STDBY 3 | ||
| 965 | #define RCPREVBSYTUPAVG 0x113b8 | ||
| 966 | #define RCPREVBSYTDNAVG 0x113bc | ||
| 773 | #define PEG_BAND_GAP_DATA 0x14d68 | 967 | #define PEG_BAND_GAP_DATA 0x14d68 |
| 774 | 968 | ||
| 775 | /* | 969 | /* |
| @@ -844,7 +1038,6 @@ | |||
| 844 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) | 1038 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
| 845 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | 1039 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
| 846 | #define TV_HOTPLUG_INT_EN (1 << 18) | 1040 | #define TV_HOTPLUG_INT_EN (1 << 18) |
| 847 | #define CRT_EOS_INT_EN (1 << 10) | ||
| 848 | #define CRT_HOTPLUG_INT_EN (1 << 9) | 1041 | #define CRT_HOTPLUG_INT_EN (1 << 9) |
| 849 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) | 1042 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
| 850 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) | 1043 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
| @@ -863,14 +1056,6 @@ | |||
| 863 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | 1056 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
| 864 | #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ | 1057 | #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ |
| 865 | #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f | 1058 | #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f |
| 866 | #define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \ | ||
| 867 | HDMIC_HOTPLUG_INT_EN | \ | ||
| 868 | HDMID_HOTPLUG_INT_EN | \ | ||
| 869 | SDVOB_HOTPLUG_INT_EN | \ | ||
| 870 | SDVOC_HOTPLUG_INT_EN | \ | ||
| 871 | TV_HOTPLUG_INT_EN | \ | ||
| 872 | CRT_HOTPLUG_INT_EN) | ||
| 873 | |||
| 874 | 1059 | ||
| 875 | #define PORT_HOTPLUG_STAT 0x61114 | 1060 | #define PORT_HOTPLUG_STAT 0x61114 |
| 876 | #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) | 1061 | #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) |
| @@ -879,7 +1064,6 @@ | |||
| 879 | #define DPC_HOTPLUG_INT_STATUS (1 << 28) | 1064 | #define DPC_HOTPLUG_INT_STATUS (1 << 28) |
| 880 | #define HDMID_HOTPLUG_INT_STATUS (1 << 27) | 1065 | #define HDMID_HOTPLUG_INT_STATUS (1 << 27) |
| 881 | #define DPD_HOTPLUG_INT_STATUS (1 << 27) | 1066 | #define DPD_HOTPLUG_INT_STATUS (1 << 27) |
| 882 | #define CRT_EOS_INT_STATUS (1 << 12) | ||
| 883 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) | 1067 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
| 884 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | 1068 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
| 885 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | 1069 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
| @@ -968,6 +1152,8 @@ | |||
| 968 | #define LVDS_PORT_EN (1 << 31) | 1152 | #define LVDS_PORT_EN (1 << 31) |
| 969 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | 1153 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ |
| 970 | #define LVDS_PIPEB_SELECT (1 << 30) | 1154 | #define LVDS_PIPEB_SELECT (1 << 30) |
| 1155 | /* LVDS dithering flag on 965/g4x platform */ | ||
| 1156 | #define LVDS_ENABLE_DITHER (1 << 25) | ||
| 971 | /* Enable border for unscaled (or aspect-scaled) display */ | 1157 | /* Enable border for unscaled (or aspect-scaled) display */ |
| 972 | #define LVDS_BORDER_ENABLE (1 << 15) | 1158 | #define LVDS_BORDER_ENABLE (1 << 15) |
| 973 | /* | 1159 | /* |
| @@ -1620,7 +1806,7 @@ | |||
| 1620 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) | 1806 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
| 1621 | 1807 | ||
| 1622 | #define DP_SCRAMBLING_DISABLE (1 << 12) | 1808 | #define DP_SCRAMBLING_DISABLE (1 << 12) |
| 1623 | #define DP_SCRAMBLING_DISABLE_IGDNG (1 << 7) | 1809 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
| 1624 | 1810 | ||
| 1625 | /** limit RGB values to avoid confusing TVs */ | 1811 | /** limit RGB values to avoid confusing TVs */ |
| 1626 | #define DP_COLOR_RANGE_16_235 (1 << 8) | 1812 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
| @@ -1737,6 +1923,8 @@ | |||
| 1737 | 1923 | ||
| 1738 | /* Display & cursor control */ | 1924 | /* Display & cursor control */ |
| 1739 | 1925 | ||
| 1926 | /* dithering flag on Ironlake */ | ||
| 1927 | #define PIPE_ENABLE_DITHER (1 << 4) | ||
| 1740 | /* Pipe A */ | 1928 | /* Pipe A */ |
| 1741 | #define PIPEADSL 0x70000 | 1929 | #define PIPEADSL 0x70000 |
| 1742 | #define PIPEACONF 0x70008 | 1930 | #define PIPEACONF 0x70008 |
| @@ -1804,11 +1992,11 @@ | |||
| 1804 | #define DSPFW_PLANEB_SHIFT 8 | 1992 | #define DSPFW_PLANEB_SHIFT 8 |
| 1805 | #define DSPFW2 0x70038 | 1993 | #define DSPFW2 0x70038 |
| 1806 | #define DSPFW_CURSORA_MASK 0x00003f00 | 1994 | #define DSPFW_CURSORA_MASK 0x00003f00 |
| 1807 | #define DSPFW_CURSORA_SHIFT 16 | 1995 | #define DSPFW_CURSORA_SHIFT 8 |
| 1808 | #define DSPFW3 0x7003c | 1996 | #define DSPFW3 0x7003c |
| 1809 | #define DSPFW_HPLL_SR_EN (1<<31) | 1997 | #define DSPFW_HPLL_SR_EN (1<<31) |
| 1810 | #define DSPFW_CURSOR_SR_SHIFT 24 | 1998 | #define DSPFW_CURSOR_SR_SHIFT 24 |
| 1811 | #define IGD_SELF_REFRESH_EN (1<<30) | 1999 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
| 1812 | 2000 | ||
| 1813 | /* FIFO watermark sizes etc */ | 2001 | /* FIFO watermark sizes etc */ |
| 1814 | #define G4X_FIFO_LINE_SIZE 64 | 2002 | #define G4X_FIFO_LINE_SIZE 64 |
| @@ -1824,16 +2012,16 @@ | |||
| 1824 | #define G4X_MAX_WM 0x3f | 2012 | #define G4X_MAX_WM 0x3f |
| 1825 | #define I915_MAX_WM 0x3f | 2013 | #define I915_MAX_WM 0x3f |
| 1826 | 2014 | ||
| 1827 | #define IGD_DISPLAY_FIFO 512 /* in 64byte unit */ | 2015 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
| 1828 | #define IGD_FIFO_LINE_SIZE 64 | 2016 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
| 1829 | #define IGD_MAX_WM 0x1ff | 2017 | #define PINEVIEW_MAX_WM 0x1ff |
| 1830 | #define IGD_DFT_WM 0x3f | 2018 | #define PINEVIEW_DFT_WM 0x3f |
| 1831 | #define IGD_DFT_HPLLOFF_WM 0 | 2019 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
| 1832 | #define IGD_GUARD_WM 10 | 2020 | #define PINEVIEW_GUARD_WM 10 |
| 1833 | #define IGD_CURSOR_FIFO 64 | 2021 | #define PINEVIEW_CURSOR_FIFO 64 |
| 1834 | #define IGD_CURSOR_MAX_WM 0x3f | 2022 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
| 1835 | #define IGD_CURSOR_DFT_WM 0 | 2023 | #define PINEVIEW_CURSOR_DFT_WM 0 |
| 1836 | #define IGD_CURSOR_GUARD_WM 5 | 2024 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
| 1837 | 2025 | ||
| 1838 | /* | 2026 | /* |
| 1839 | * The two pipe frame counter registers are not synchronized, so | 2027 | * The two pipe frame counter registers are not synchronized, so |
| @@ -1907,6 +2095,7 @@ | |||
| 1907 | #define DISPPLANE_16BPP (0x5<<26) | 2095 | #define DISPPLANE_16BPP (0x5<<26) |
| 1908 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) | 2096 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) |
| 1909 | #define DISPPLANE_32BPP (0x7<<26) | 2097 | #define DISPPLANE_32BPP (0x7<<26) |
| 2098 | #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) | ||
| 1910 | #define DISPPLANE_STEREO_ENABLE (1<<25) | 2099 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
| 1911 | #define DISPPLANE_STEREO_DISABLE 0 | 2100 | #define DISPPLANE_STEREO_DISABLE 0 |
| 1912 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) | 2101 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) |
| @@ -1918,7 +2107,7 @@ | |||
| 1918 | #define DISPPLANE_NO_LINE_DOUBLE 0 | 2107 | #define DISPPLANE_NO_LINE_DOUBLE 0 |
| 1919 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | 2108 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
| 1920 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | 2109 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
| 1921 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */ | 2110 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
| 1922 | #define DISPPLANE_TILED (1<<10) | 2111 | #define DISPPLANE_TILED (1<<10) |
| 1923 | #define DSPAADDR 0x70184 | 2112 | #define DSPAADDR 0x70184 |
| 1924 | #define DSPASTRIDE 0x70188 | 2113 | #define DSPASTRIDE 0x70188 |
| @@ -1971,7 +2160,7 @@ | |||
| 1971 | # define VGA_2X_MODE (1 << 30) | 2160 | # define VGA_2X_MODE (1 << 30) |
| 1972 | # define VGA_PIPE_B_SELECT (1 << 29) | 2161 | # define VGA_PIPE_B_SELECT (1 << 29) |
| 1973 | 2162 | ||
| 1974 | /* IGDNG */ | 2163 | /* Ironlake */ |
| 1975 | 2164 | ||
| 1976 | #define CPU_VGACNTRL 0x41000 | 2165 | #define CPU_VGACNTRL 0x41000 |
| 1977 | 2166 | ||
| @@ -1997,6 +2186,14 @@ | |||
| 1997 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 | 2186 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
| 1998 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | 2187 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
| 1999 | 2188 | ||
| 2189 | #define PCH_DSPCLK_GATE_D 0x42020 | ||
| 2190 | # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) | ||
| 2191 | # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) | ||
| 2192 | |||
| 2193 | #define PCH_3DCGDIS0 0x46020 | ||
| 2194 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | ||
| 2195 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | ||
| 2196 | |||
| 2000 | #define FDI_PLL_FREQ_CTL 0x46030 | 2197 | #define FDI_PLL_FREQ_CTL 0x46030 |
| 2001 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) | 2198 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
| 2002 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | 2199 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
| @@ -2098,6 +2295,7 @@ | |||
| 2098 | #define DEIER 0x4400c | 2295 | #define DEIER 0x4400c |
| 2099 | 2296 | ||
| 2100 | /* GT interrupt */ | 2297 | /* GT interrupt */ |
| 2298 | #define GT_PIPE_NOTIFY (1 << 4) | ||
| 2101 | #define GT_SYNC_STATUS (1 << 2) | 2299 | #define GT_SYNC_STATUS (1 << 2) |
| 2102 | #define GT_USER_INTERRUPT (1 << 0) | 2300 | #define GT_USER_INTERRUPT (1 << 0) |
| 2103 | 2301 | ||
| @@ -2117,6 +2315,7 @@ | |||
| 2117 | #define SDE_PORTC_HOTPLUG (1 << 9) | 2315 | #define SDE_PORTC_HOTPLUG (1 << 9) |
| 2118 | #define SDE_PORTB_HOTPLUG (1 << 8) | 2316 | #define SDE_PORTB_HOTPLUG (1 << 8) |
| 2119 | #define SDE_SDVOB_HOTPLUG (1 << 6) | 2317 | #define SDE_SDVOB_HOTPLUG (1 << 6) |
| 2318 | #define SDE_HOTPLUG_MASK (0xf << 8) | ||
| 2120 | 2319 | ||
| 2121 | #define SDEISR 0xc4000 | 2320 | #define SDEISR 0xc4000 |
| 2122 | #define SDEIMR 0xc4004 | 2321 | #define SDEIMR 0xc4004 |
| @@ -2157,6 +2356,13 @@ | |||
| 2157 | #define PCH_GPIOE 0xc5020 | 2356 | #define PCH_GPIOE 0xc5020 |
| 2158 | #define PCH_GPIOF 0xc5024 | 2357 | #define PCH_GPIOF 0xc5024 |
| 2159 | 2358 | ||
| 2359 | #define PCH_GMBUS0 0xc5100 | ||
| 2360 | #define PCH_GMBUS1 0xc5104 | ||
| 2361 | #define PCH_GMBUS2 0xc5108 | ||
| 2362 | #define PCH_GMBUS3 0xc510c | ||
| 2363 | #define PCH_GMBUS4 0xc5110 | ||
| 2364 | #define PCH_GMBUS5 0xc5120 | ||
| 2365 | |||
| 2160 | #define PCH_DPLL_A 0xc6014 | 2366 | #define PCH_DPLL_A 0xc6014 |
| 2161 | #define PCH_DPLL_B 0xc6018 | 2367 | #define PCH_DPLL_B 0xc6018 |
| 2162 | 2368 | ||
| @@ -2292,7 +2498,7 @@ | |||
| 2292 | #define FDI_DP_PORT_WIDTH_X3 (2<<19) | 2498 | #define FDI_DP_PORT_WIDTH_X3 (2<<19) |
| 2293 | #define FDI_DP_PORT_WIDTH_X4 (3<<19) | 2499 | #define FDI_DP_PORT_WIDTH_X4 (3<<19) |
| 2294 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) | 2500 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
| 2295 | /* IGDNG: hardwired to 1 */ | 2501 | /* Ironlake: hardwired to 1 */ |
| 2296 | #define FDI_TX_PLL_ENABLE (1<<14) | 2502 | #define FDI_TX_PLL_ENABLE (1<<14) |
| 2297 | /* both Tx and Rx */ | 2503 | /* both Tx and Rx */ |
| 2298 | #define FDI_SCRAMBLING_ENABLE (0<<7) | 2504 | #define FDI_SCRAMBLING_ENABLE (0<<7) |