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path: root/drivers/gpu/drm/i915/i915_irq.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c161
1 files changed, 85 insertions, 76 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f13d5edc39d5..17d8fcb1b6f7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -62,7 +62,7 @@ static const u32 hpd_mask_i915[] = {
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN 62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63}; 63};
64 64
65static const u32 hpd_status_gen4[] = { 65static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
@@ -600,7 +600,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
600 * Cook up a vblank counter by also checking the pixel 600 * Cook up a vblank counter by also checking the pixel
601 * counter against vblank start. 601 * counter against vblank start.
602 */ 602 */
603 return ((high1 << 8) | low) + (pixel >= vbl_start); 603 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
604} 604}
605 605
606static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 606static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
@@ -621,36 +621,15 @@ static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
621#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) 621#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
622#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) 622#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
623 623
624static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) 624static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
625{ 625{
626 struct drm_i915_private *dev_priv = dev->dev_private; 626 struct drm_i915_private *dev_priv = dev->dev_private;
627 uint32_t status; 627 uint32_t status;
628 int reg;
629 628
630 if (IS_VALLEYVIEW(dev)) { 629 if (INTEL_INFO(dev)->gen < 7) {
631 status = pipe == PIPE_A ?
632 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
633 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
634
635 reg = VLV_ISR;
636 } else if (IS_GEN2(dev)) {
637 status = pipe == PIPE_A ?
638 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
639 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
640
641 reg = ISR;
642 } else if (INTEL_INFO(dev)->gen < 5) {
643 status = pipe == PIPE_A ?
644 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
645 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
646
647 reg = ISR;
648 } else if (INTEL_INFO(dev)->gen < 7) {
649 status = pipe == PIPE_A ? 630 status = pipe == PIPE_A ?
650 DE_PIPEA_VBLANK : 631 DE_PIPEA_VBLANK :
651 DE_PIPEB_VBLANK; 632 DE_PIPEB_VBLANK;
652
653 reg = DEISR;
654 } else { 633 } else {
655 switch (pipe) { 634 switch (pipe) {
656 default: 635 default:
@@ -664,18 +643,14 @@ static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
664 status = DE_PIPEC_VBLANK_IVB; 643 status = DE_PIPEC_VBLANK_IVB;
665 break; 644 break;
666 } 645 }
667
668 reg = DEISR;
669 } 646 }
670 647
671 if (IS_GEN2(dev)) 648 return __raw_i915_read32(dev_priv, DEISR) & status;
672 return __raw_i915_read16(dev_priv, reg) & status;
673 else
674 return __raw_i915_read32(dev_priv, reg) & status;
675} 649}
676 650
677static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 651static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
678 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) 652 unsigned int flags, int *vpos, int *hpos,
653 ktime_t *stime, ktime_t *etime)
679{ 654{
680 struct drm_i915_private *dev_priv = dev->dev_private; 655 struct drm_i915_private *dev_priv = dev->dev_private;
681 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 656 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
@@ -698,6 +673,12 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
698 vbl_start = mode->crtc_vblank_start; 673 vbl_start = mode->crtc_vblank_start;
699 vbl_end = mode->crtc_vblank_end; 674 vbl_end = mode->crtc_vblank_end;
700 675
676 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
677 vbl_start = DIV_ROUND_UP(vbl_start, 2);
678 vbl_end /= 2;
679 vtotal /= 2;
680 }
681
701 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 682 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
702 683
703 /* 684 /*
@@ -722,17 +703,42 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
722 else 703 else
723 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 704 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
724 705
725 /* 706 if (HAS_PCH_SPLIT(dev)) {
726 * The scanline counter increments at the leading edge 707 /*
727 * of hsync, ie. it completely misses the active portion 708 * The scanline counter increments at the leading edge
728 * of the line. Fix up the counter at both edges of vblank 709 * of hsync, ie. it completely misses the active portion
729 * to get a more accurate picture whether we're in vblank 710 * of the line. Fix up the counter at both edges of vblank
730 * or not. 711 * to get a more accurate picture whether we're in vblank
731 */ 712 * or not.
732 in_vbl = intel_pipe_in_vblank_locked(dev, pipe); 713 */
733 if ((in_vbl && position == vbl_start - 1) || 714 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
734 (!in_vbl && position == vbl_end - 1)) 715 if ((in_vbl && position == vbl_start - 1) ||
735 position = (position + 1) % vtotal; 716 (!in_vbl && position == vbl_end - 1))
717 position = (position + 1) % vtotal;
718 } else {
719 /*
720 * ISR vblank status bits don't work the way we'd want
721 * them to work on non-PCH platforms (for
722 * ilk_pipe_in_vblank_locked()), and there doesn't
723 * appear any other way to determine if we're currently
724 * in vblank.
725 *
726 * Instead let's assume that we're already in vblank if
727 * we got called from the vblank interrupt and the
728 * scanline counter value indicates that we're on the
729 * line just prior to vblank start. This should result
730 * in the correct answer, unless the vblank interrupt
731 * delivery really got delayed for almost exactly one
732 * full frame/field.
733 */
734 if (flags & DRM_CALLED_FROM_VBLIRQ &&
735 position == vbl_start - 1) {
736 position = (position + 1) % vtotal;
737
738 /* Signal this correction as "applied". */
739 ret |= 0x8;
740 }
741 }
736 } else { 742 } else {
737 /* Have access to pixelcount since start of frame. 743 /* Have access to pixelcount since start of frame.
738 * We can split this into vertical and horizontal 744 * We can split this into vertical and horizontal
@@ -809,7 +815,8 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
809 /* Helper routine in DRM core does all the work: */ 815 /* Helper routine in DRM core does all the work: */
810 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 816 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
811 vblank_time, flags, 817 vblank_time, flags,
812 crtc); 818 crtc,
819 &to_intel_crtc(crtc)->config.adjusted_mode);
813} 820}
814 821
815static bool intel_hpd_irq_event(struct drm_device *dev, 822static bool intel_hpd_irq_event(struct drm_device *dev,
@@ -1015,10 +1022,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
1015 /* sysfs frequency interfaces may have snuck in while servicing the 1022 /* sysfs frequency interfaces may have snuck in while servicing the
1016 * interrupt 1023 * interrupt
1017 */ 1024 */
1018 if (new_delay < (int)dev_priv->rps.min_delay) 1025 new_delay = clamp_t(int, new_delay,
1019 new_delay = dev_priv->rps.min_delay; 1026 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1020 if (new_delay > (int)dev_priv->rps.max_delay)
1021 new_delay = dev_priv->rps.max_delay;
1022 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; 1027 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1023 1028
1024 if (IS_VALLEYVIEW(dev_priv->dev)) 1029 if (IS_VALLEYVIEW(dev_priv->dev))
@@ -1235,9 +1240,10 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
1235 spin_lock(&dev_priv->irq_lock); 1240 spin_lock(&dev_priv->irq_lock);
1236 for (i = 1; i < HPD_NUM_PINS; i++) { 1241 for (i = 1; i < HPD_NUM_PINS; i++) {
1237 1242
1238 WARN(((hpd[i] & hotplug_trigger) && 1243 WARN_ONCE(hpd[i] & hotplug_trigger &&
1239 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED), 1244 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1240 "Received HPD interrupt although disabled\n"); 1245 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1246 hotplug_trigger, i, hpd[i]);
1241 1247
1242 if (!(hpd[i] & hotplug_trigger) || 1248 if (!(hpd[i] & hotplug_trigger) ||
1243 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) 1249 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
@@ -1474,6 +1480,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1474 1480
1475 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 1481 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1476 1482
1483 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1484 dp_aux_irq_handler(dev);
1485
1477 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1486 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1478 I915_READ(PORT_HOTPLUG_STAT); 1487 I915_READ(PORT_HOTPLUG_STAT);
1479 } 1488 }
@@ -1993,7 +2002,7 @@ static void i915_error_work_func(struct work_struct *work)
1993 kobject_uevent_env(&dev->primary->kdev->kobj, 2002 kobject_uevent_env(&dev->primary->kdev->kobj,
1994 KOBJ_CHANGE, reset_done_event); 2003 KOBJ_CHANGE, reset_done_event);
1995 } else { 2004 } else {
1996 atomic_set(&error->reset_counter, I915_WEDGED); 2005 atomic_set_mask(I915_WEDGED, &error->reset_counter);
1997 } 2006 }
1998 2007
1999 /* 2008 /*
@@ -3140,10 +3149,10 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
3140 * Returns true when a page flip has completed. 3149 * Returns true when a page flip has completed.
3141 */ 3150 */
3142static bool i8xx_handle_vblank(struct drm_device *dev, 3151static bool i8xx_handle_vblank(struct drm_device *dev,
3143 int pipe, u16 iir) 3152 int plane, int pipe, u32 iir)
3144{ 3153{
3145 drm_i915_private_t *dev_priv = dev->dev_private; 3154 drm_i915_private_t *dev_priv = dev->dev_private;
3146 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); 3155 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3147 3156
3148 if (!drm_handle_vblank(dev, pipe)) 3157 if (!drm_handle_vblank(dev, pipe))
3149 return false; 3158 return false;
@@ -3151,7 +3160,7 @@ static bool i8xx_handle_vblank(struct drm_device *dev,
3151 if ((iir & flip_pending) == 0) 3160 if ((iir & flip_pending) == 0)
3152 return false; 3161 return false;
3153 3162
3154 intel_prepare_page_flip(dev, pipe); 3163 intel_prepare_page_flip(dev, plane);
3155 3164
3156 /* We detect FlipDone by looking for the change in PendingFlip from '1' 3165 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3157 * to '0' on the following vblank, i.e. IIR has the Pendingflip 3166 * to '0' on the following vblank, i.e. IIR has the Pendingflip
@@ -3220,9 +3229,13 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3220 notify_ring(dev, &dev_priv->ring[RCS]); 3229 notify_ring(dev, &dev_priv->ring[RCS]);
3221 3230
3222 for_each_pipe(pipe) { 3231 for_each_pipe(pipe) {
3232 int plane = pipe;
3233 if (HAS_FBC(dev))
3234 plane = !plane;
3235
3223 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 3236 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3224 i8xx_handle_vblank(dev, pipe, iir)) 3237 i8xx_handle_vblank(dev, plane, pipe, iir))
3225 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 3238 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3226 3239
3227 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3240 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3228 i9xx_pipe_crc_irq_handler(dev, pipe); 3241 i9xx_pipe_crc_irq_handler(dev, pipe);
@@ -3418,7 +3431,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
3418 3431
3419 for_each_pipe(pipe) { 3432 for_each_pipe(pipe) {
3420 int plane = pipe; 3433 int plane = pipe;
3421 if (IS_MOBILE(dev)) 3434 if (HAS_FBC(dev))
3422 plane = !plane; 3435 plane = !plane;
3423 3436
3424 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 3437 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
@@ -3655,7 +3668,11 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
3655 hotplug_status); 3668 hotplug_status);
3656 3669
3657 intel_hpd_irq_handler(dev, hotplug_trigger, 3670 intel_hpd_irq_handler(dev, hotplug_trigger,
3658 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); 3671 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3672
3673 if (IS_G4X(dev) &&
3674 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3675 dp_aux_irq_handler(dev);
3659 3676
3660 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3677 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3661 I915_READ(PORT_HOTPLUG_STAT); 3678 I915_READ(PORT_HOTPLUG_STAT);
@@ -3893,8 +3910,8 @@ void hsw_pc8_disable_interrupts(struct drm_device *dev)
3893 dev_priv->pc8.regsave.gtier = I915_READ(GTIER); 3910 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3894 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); 3911 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3895 3912
3896 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB); 3913 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3897 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT); 3914 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3898 ilk_disable_gt_irq(dev_priv, 0xffffffff); 3915 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3899 snb_disable_pm_irq(dev_priv, 0xffffffff); 3916 snb_disable_pm_irq(dev_priv, 0xffffffff);
3900 3917
@@ -3908,34 +3925,26 @@ void hsw_pc8_restore_interrupts(struct drm_device *dev)
3908{ 3925{
3909 struct drm_i915_private *dev_priv = dev->dev_private; 3926 struct drm_i915_private *dev_priv = dev->dev_private;
3910 unsigned long irqflags; 3927 unsigned long irqflags;
3911 uint32_t val, expected; 3928 uint32_t val;
3912 3929
3913 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3930 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3914 3931
3915 val = I915_READ(DEIMR); 3932 val = I915_READ(DEIMR);
3916 expected = ~DE_PCH_EVENT_IVB; 3933 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3917 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3918 3934
3919 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT; 3935 val = I915_READ(SDEIMR);
3920 expected = ~SDE_HOTPLUG_MASK_CPT; 3936 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3921 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3922 val, expected);
3923 3937
3924 val = I915_READ(GTIMR); 3938 val = I915_READ(GTIMR);
3925 expected = 0xffffffff; 3939 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3926 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3927 3940
3928 val = I915_READ(GEN6_PMIMR); 3941 val = I915_READ(GEN6_PMIMR);
3929 expected = 0xffffffff; 3942 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3930 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3931 expected);
3932 3943
3933 dev_priv->pc8.irqs_disabled = false; 3944 dev_priv->pc8.irqs_disabled = false;
3934 3945
3935 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); 3946 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3936 ibx_enable_display_interrupt(dev_priv, 3947 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3937 ~dev_priv->pc8.regsave.sdeimr &
3938 ~SDE_HOTPLUG_MASK_CPT);
3939 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); 3948 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3940 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); 3949 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3941 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); 3950 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);