diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 744225ebb4b2..477e4ac66639 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -310,6 +310,7 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
310 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 310 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
311 | int ret = IRQ_NONE; | 311 | int ret = IRQ_NONE; |
312 | u32 de_iir, gt_iir, de_ier, pch_iir; | 312 | u32 de_iir, gt_iir, de_ier, pch_iir; |
313 | u32 hotplug_mask; | ||
313 | struct drm_i915_master_private *master_priv; | 314 | struct drm_i915_master_private *master_priv; |
314 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; | 315 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
315 | 316 | ||
@@ -325,6 +326,11 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
325 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) | 326 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
326 | goto done; | 327 | goto done; |
327 | 328 | ||
329 | if (HAS_PCH_CPT(dev)) | ||
330 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | ||
331 | else | ||
332 | hotplug_mask = SDE_HOTPLUG_MASK; | ||
333 | |||
328 | ret = IRQ_HANDLED; | 334 | ret = IRQ_HANDLED; |
329 | 335 | ||
330 | if (dev->primary->master) { | 336 | if (dev->primary->master) { |
@@ -366,10 +372,8 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
366 | drm_handle_vblank(dev, 1); | 372 | drm_handle_vblank(dev, 1); |
367 | 373 | ||
368 | /* check event from PCH */ | 374 | /* check event from PCH */ |
369 | if ((de_iir & DE_PCH_EVENT) && | 375 | if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask)) |
370 | (pch_iir & SDE_HOTPLUG_MASK)) { | ||
371 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | 376 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
372 | } | ||
373 | 377 | ||
374 | if (de_iir & DE_PCU_EVENT) { | 378 | if (de_iir & DE_PCU_EVENT) { |
375 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); | 379 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
@@ -1424,8 +1428,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1424 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | 1428 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1425 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | 1429 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
1426 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; | 1430 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
1427 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | 1431 | u32 hotplug_mask; |
1428 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | ||
1429 | 1432 | ||
1430 | dev_priv->irq_mask_reg = ~display_mask; | 1433 | dev_priv->irq_mask_reg = ~display_mask; |
1431 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; | 1434 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
@@ -1450,6 +1453,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1450 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | 1453 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
1451 | (void) I915_READ(GTIER); | 1454 | (void) I915_READ(GTIER); |
1452 | 1455 | ||
1456 | if (HAS_PCH_CPT(dev)) { | ||
1457 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | | ||
1458 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; | ||
1459 | } else { | ||
1460 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | ||
1461 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | ||
1462 | } | ||
1463 | |||
1453 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; | 1464 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1454 | dev_priv->pch_irq_enable_reg = hotplug_mask; | 1465 | dev_priv->pch_irq_enable_reg = hotplug_mask; |
1455 | 1466 | ||