1 files changed, 451 insertions, 116 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index aa7fd82aa6eb..df6a9cd82c4d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -27,6 +27,7 @@
  */
 
 #include <linux/sysrq.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "drm.h"
 #include "i915_drm.h"
@@ -43,10 +44,13 @@
  * we leave them always unmasked in IMR and then control enabling them through
  * PIPESTAT alone.
  */
-#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT |                 \
-                                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
-                                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
-                                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+#define I915_INTERRUPT_ENABLE_FIX                       \
+        (I915_ASLE_INTERRUPT |                          \
+         I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
+         I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
+         I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
+         I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
+         I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 
 /** Interrupts that we mask and unmask at runtime. */
 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
@@ -61,7 +65,7 @@
                                          DRM_I915_VBLANK_PIPE_B)
 
 void
-igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
+ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
                 dev_priv->gt_irq_mask_reg &= ~mask;
@@ -71,7 +75,7 @@ igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 }
 
 static inline void
-igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
+ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
                 dev_priv->gt_irq_mask_reg |= mask;
@@ -82,7 +86,7 @@ igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 
 /* For display hotplug interrupt */
 void
-igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
+ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
         if ((dev_priv->irq_mask_reg & mask) != 0) {
                 dev_priv->irq_mask_reg &= ~mask;
@@ -92,7 +96,7 @@ igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 }
 
 static inline void
-igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
+ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
         if ((dev_priv->irq_mask_reg & mask) != mask) {
                 dev_priv->irq_mask_reg |= mask;
@@ -157,6 +161,20 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 }
 
 /**
+ * intel_enable_asle - enable ASLE interrupt for OpRegion
+ */
+void intel_enable_asle (struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+        if (HAS_PCH_SPLIT(dev))
+                ironlake_enable_display_irq(dev_priv, DE_GSE);
+        else
+                i915_enable_pipestat(dev_priv, 1,
+                                     I915_LEGACY_BLC_EVENT_ENABLE);
+}
+
+/**
  * i915_pipe_enabled - check if a pipe is enabled
  * @dev: DRM device
  * @pipe: pipe to check
@@ -191,7 +209,8 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 
         if (!i915_pipe_enabled(dev, pipe)) {
-                DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
+                DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
+                                "pipe %d\n", pipe);
                 return 0;
         }
 
@@ -220,7 +239,8 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 
         if (!i915_pipe_enabled(dev, pipe)) {
-                DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
+                DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
+                                        "pipe %d\n", pipe);
                 return 0;
         }
 
@@ -240,22 +260,72 @@ static void i915_hotplug_work_func(struct work_struct *work)
 
         if (mode_config->num_connector) {
                 list_for_each_entry(connector, &mode_config->connector_list, head) {
-                        struct intel_output *intel_output = to_intel_output(connector);
+                        struct intel_encoder *intel_encoder = to_intel_encoder(connector);
         
-                        if (intel_output->hot_plug)
-                                (*intel_output->hot_plug) (intel_output);
+                        if (intel_encoder->hot_plug)
+                                (*intel_encoder->hot_plug) (intel_encoder);
                 }
         }
         /* Just fire off a uevent and let userspace tell us what to do */
         drm_sysfs_hotplug_event(dev);
 }
 
-irqreturn_t igdng_irq_handler(struct drm_device *dev)
+static void i915_handle_rps_change(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 busy_up, busy_down, max_avg, min_avg;
+        u16 rgvswctl;
+        u8 new_delay = dev_priv->cur_delay;
+
+        I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
+        busy_up = I915_READ(RCPREVBSYTUPAVG);
+        busy_down = I915_READ(RCPREVBSYTDNAVG);
+        max_avg = I915_READ(RCBMAXAVG);
+        min_avg = I915_READ(RCBMINAVG);
+
+        /* Handle RCS change request from hw */
+        if (busy_up > max_avg) {
+                if (dev_priv->cur_delay != dev_priv->max_delay)
+                        new_delay = dev_priv->cur_delay - 1;
+                if (new_delay < dev_priv->max_delay)
+                        new_delay = dev_priv->max_delay;
+        } else if (busy_down < min_avg) {
+                if (dev_priv->cur_delay != dev_priv->min_delay)
+                        new_delay = dev_priv->cur_delay + 1;
+                if (new_delay > dev_priv->min_delay)
+                        new_delay = dev_priv->min_delay;
+        }
+
+        DRM_DEBUG("rps change requested: %d -> %d\n",
+                  dev_priv->cur_delay, new_delay);
+
+        rgvswctl = I915_READ(MEMSWCTL);
+        if (rgvswctl & MEMCTL_CMD_STS) {
+                DRM_ERROR("gpu busy, RCS change rejected\n");
+                return; /* still busy with another command */
+        }
+
+        /* Program the new state */
+        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
+                (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+        POSTING_READ(MEMSWCTL);
+
+        rgvswctl |= MEMCTL_CMD_STS;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+
+        dev_priv->cur_delay = new_delay;
+
+        DRM_DEBUG("rps changed\n");
+
+        return;
+}
+
+irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         int ret = IRQ_NONE;
-        u32 de_iir, gt_iir, de_ier;
-        u32 new_de_iir, new_gt_iir;
+        u32 de_iir, gt_iir, de_ier, pch_iir;
         struct drm_i915_master_private *master_priv;
 
         /* disable master interrupt before clearing iir  */
@@ -265,36 +335,65 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
 
         de_iir = I915_READ(DEIIR);
         gt_iir = I915_READ(GTIIR);
+        pch_iir = I915_READ(SDEIIR);
 
-        for (;;) {
-                if (de_iir == 0 && gt_iir == 0)
-                        break;
+        if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
+                goto done;
 
-                ret = IRQ_HANDLED;
+        ret = IRQ_HANDLED;
 
-                I915_WRITE(DEIIR, de_iir);
-                new_de_iir = I915_READ(DEIIR);
-                I915_WRITE(GTIIR, gt_iir);
-                new_gt_iir = I915_READ(GTIIR);
+        if (dev->primary->master) {
+                master_priv = dev->primary->master->driver_priv;
+                if (master_priv->sarea_priv)
+                        master_priv->sarea_priv->last_dispatch =
+                                READ_BREADCRUMB(dev_priv);
+        }
 
-                if (dev->primary->master) {
-                        master_priv = dev->primary->master->driver_priv;
-                        if (master_priv->sarea_priv)
-                                master_priv->sarea_priv->last_dispatch =
-                                        READ_BREADCRUMB(dev_priv);
-                }
+        if (gt_iir & GT_PIPE_NOTIFY) {
+                u32 seqno = i915_get_gem_seqno(dev);
+                dev_priv->mm.irq_gem_seqno = seqno;
+                trace_i915_gem_request_complete(dev, seqno);
+                DRM_WAKEUP(&dev_priv->irq_queue);
+                dev_priv->hangcheck_count = 0;
+                mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
+        }
 
-                if (gt_iir & GT_USER_INTERRUPT) {
-                        u32 seqno = i915_get_gem_seqno(dev);
-                        dev_priv->mm.irq_gem_seqno = seqno;
-                        trace_i915_gem_request_complete(dev, seqno);
-                        DRM_WAKEUP(&dev_priv->irq_queue);
-                }
+        if (de_iir & DE_GSE)
+                ironlake_opregion_gse_intr(dev);
+
+        if (de_iir & DE_PLANEA_FLIP_DONE) {
+                intel_prepare_page_flip(dev, 0);
+                intel_finish_page_flip(dev, 0);
+        }
+
+        if (de_iir & DE_PLANEB_FLIP_DONE) {
+                intel_prepare_page_flip(dev, 1);
+                intel_finish_page_flip(dev, 1);
+        }
+
+        if (de_iir & DE_PIPEA_VBLANK)
+                drm_handle_vblank(dev, 0);
 
-                de_iir = new_de_iir;
-                gt_iir = new_gt_iir;
+        if (de_iir & DE_PIPEB_VBLANK)
+                drm_handle_vblank(dev, 1);
+
+        /* check event from PCH */
+        if ((de_iir & DE_PCH_EVENT) &&
+            (pch_iir & SDE_HOTPLUG_MASK)) {
+                queue_work(dev_priv->wq, &dev_priv->hotplug_work);
+        }
+
+        if (de_iir & DE_PCU_EVENT) {
+                I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
+                i915_handle_rps_change(dev);
         }
 
+        /* should clear PCH hotplug event before clear CPU irq */
+        I915_WRITE(SDEIIR, pch_iir);
+        I915_WRITE(GTIIR, gt_iir);
+        I915_WRITE(DEIIR, de_iir);
+
+done:
         I915_WRITE(DEIER, de_ier);
         (void)I915_READ(DEIER);
 
@@ -317,23 +416,142 @@ static void i915_error_work_func(struct work_struct *work)
         char *reset_event[] = { "RESET=1", NULL };
         char *reset_done_event[] = { "ERROR=0", NULL };
 
-        DRM_DEBUG("generating error event\n");
+        DRM_DEBUG_DRIVER("generating error event\n");
         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 
         if (atomic_read(&dev_priv->mm.wedged)) {
                 if (IS_I965G(dev)) {
-                        DRM_DEBUG("resetting chip\n");
+                        DRM_DEBUG_DRIVER("resetting chip\n");
                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
                         if (!i965_reset(dev, GDRST_RENDER)) {
                                 atomic_set(&dev_priv->mm.wedged, 0);
                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
                         }
                 } else {
-                        printk("reboot required\n");
+                        DRM_DEBUG_DRIVER("reboot required\n");
                 }
         }
 }
 
+static struct drm_i915_error_object *
+i915_error_object_create(struct drm_device *dev,
+                         struct drm_gem_object *src)
+{
+        struct drm_i915_error_object *dst;
+        struct drm_i915_gem_object *src_priv;
+        int page, page_count;
+
+        if (src == NULL)
+                return NULL;
+
+        src_priv = to_intel_bo(src);
+        if (src_priv->pages == NULL)
+                return NULL;
+
+        page_count = src->size / PAGE_SIZE;
+
+        dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
+        if (dst == NULL)
+                return NULL;
+
+        for (page = 0; page < page_count; page++) {
+                void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
+                unsigned long flags;
+
+                if (d == NULL)
+                        goto unwind;
+                local_irq_save(flags);
+                s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
+                memcpy(d, s, PAGE_SIZE);
+                kunmap_atomic(s, KM_IRQ0);
+                local_irq_restore(flags);
+                dst->pages[page] = d;
+        }
+        dst->page_count = page_count;
+        dst->gtt_offset = src_priv->gtt_offset;
+
+        return dst;
+
+unwind:
+        while (page--)
+                kfree(dst->pages[page]);
+        kfree(dst);
+        return NULL;
+}
+
+static void
+i915_error_object_free(struct drm_i915_error_object *obj)
+{
+        int page;
+
+        if (obj == NULL)
+                return;
+
+        for (page = 0; page < obj->page_count; page++)
+                kfree(obj->pages[page]);
+
+        kfree(obj);
+}
+
+static void
+i915_error_state_free(struct drm_device *dev,
+                      struct drm_i915_error_state *error)
+{
+        i915_error_object_free(error->batchbuffer[0]);
+        i915_error_object_free(error->batchbuffer[1]);
+        i915_error_object_free(error->ringbuffer);
+        kfree(error->active_bo);
+        kfree(error);
+}
+
+static u32
+i915_get_bbaddr(struct drm_device *dev, u32 *ring)
+{
+        u32 cmd;
+
+        if (IS_I830(dev) || IS_845G(dev))
+                cmd = MI_BATCH_BUFFER;
+        else if (IS_I965G(dev))
+                cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
+                       MI_BATCH_NON_SECURE_I965);
+        else
+                cmd = (MI_BATCH_BUFFER_START | (2 << 6));
+
+        return ring[0] == cmd ? ring[1] : 0;
+}
+
+static u32
+i915_ringbuffer_last_batch(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 head, bbaddr;
+        u32 *ring;
+
+        /* Locate the current position in the ringbuffer and walk back
+         * to find the most recently dispatched batch buffer.
+         */
+        bbaddr = 0;
+        head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
+        ring = (u32 *)(dev_priv->ring.virtual_start + head);
+
+        while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
+                bbaddr = i915_get_bbaddr(dev, ring);
+                if (bbaddr)
+                        break;
+        }
+
+        if (bbaddr == 0) {
+                ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
+                while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
+                        bbaddr = i915_get_bbaddr(dev, ring);
+                        if (bbaddr)
+                                break;
+                }
+        }
+
+        return bbaddr;
+}
+
 /**
  * i915_capture_error_state - capture an error record for later analysis
  * @dev: drm device
@@ -346,19 +564,26 @@ static void i915_error_work_func(struct work_struct *work)
 static void i915_capture_error_state(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_gem_object *obj_priv;
         struct drm_i915_error_state *error;
+        struct drm_gem_object *batchbuffer[2];
         unsigned long flags;
+        u32 bbaddr;
+        int count;
 
         spin_lock_irqsave(&dev_priv->error_lock, flags);
-        if (dev_priv->first_error)
-                goto out;
+        error = dev_priv->first_error;
+        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+        if (error)
+                return;
 
         error = kmalloc(sizeof(*error), GFP_ATOMIC);
         if (!error) {
-                DRM_DEBUG("out ot memory, not capturing error state\n");
-                goto out;
+                DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
+                return;
         }
 
+        error->seqno = i915_get_gem_seqno(dev);
         error->eir = I915_READ(EIR);
         error->pgtbl_er = I915_READ(PGTBL_ER);
         error->pipeastat = I915_READ(PIPEASTAT);
@@ -369,6 +594,7 @@ static void i915_capture_error_state(struct drm_device *dev)
                 error->ipehr = I915_READ(IPEHR);
                 error->instdone = I915_READ(INSTDONE);
                 error->acthd = I915_READ(ACTHD);
+                error->bbaddr = 0;
         } else {
                 error->ipeir = I915_READ(IPEIR_I965);
                 error->ipehr = I915_READ(IPEHR_I965);
@@ -376,14 +602,101 @@ static void i915_capture_error_state(struct drm_device *dev)
                 error->instps = I915_READ(INSTPS);
                 error->instdone1 = I915_READ(INSTDONE1);
                 error->acthd = I915_READ(ACTHD_I965);
+                error->bbaddr = I915_READ64(BB_ADDR);
         }
 
-        do_gettimeofday(&error->time);
+        bbaddr = i915_ringbuffer_last_batch(dev);
+
+        /* Grab the current batchbuffer, most likely to have crashed. */
+        batchbuffer[0] = NULL;
+        batchbuffer[1] = NULL;
+        count = 0;
+        list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
+                struct drm_gem_object *obj = obj_priv->obj;
+
+                if (batchbuffer[0] == NULL &&
+                    bbaddr >= obj_priv->gtt_offset &&
+                    bbaddr < obj_priv->gtt_offset + obj->size)
+                        batchbuffer[0] = obj;
+
+                if (batchbuffer[1] == NULL &&
+                    error->acthd >= obj_priv->gtt_offset &&
+                    error->acthd < obj_priv->gtt_offset + obj->size &&
+                    batchbuffer[0] != obj)
+                        batchbuffer[1] = obj;
+
+                count++;
+        }
+
+        /* We need to copy these to an anonymous buffer as the simplest
+         * method to avoid being overwritten by userpace.
+         */
+        error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
+        error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
+
+        /* Record the ringbuffer */
+        error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
+
+        /* Record buffers on the active list. */
+        error->active_bo = NULL;
+        error->active_bo_count = 0;
+
+        if (count)
+                error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
+                                           GFP_ATOMIC);
+
+        if (error->active_bo) {
+                int i = 0;
+                list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
+                        struct drm_gem_object *obj = obj_priv->obj;
+
+                        error->active_bo[i].size = obj->size;
+                        error->active_bo[i].name = obj->name;
+                        error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
+                        error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
+                        error->active_bo[i].read_domains = obj->read_domains;
+                        error->active_bo[i].write_domain = obj->write_domain;
+                        error->active_bo[i].fence_reg = obj_priv->fence_reg;
+                        error->active_bo[i].pinned = 0;
+                        if (obj_priv->pin_count > 0)
+                                error->active_bo[i].pinned = 1;
+                        if (obj_priv->user_pin_count > 0)
+                                error->active_bo[i].pinned = -1;
+                        error->active_bo[i].tiling = obj_priv->tiling_mode;
+                        error->active_bo[i].dirty = obj_priv->dirty;
+                        error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
+
+                        if (++i == count)
+                                break;
+                }
+                error->active_bo_count = i;
+        }
 
-        dev_priv->first_error = error;
+        do_gettimeofday(&error->time);
 
-out:
+        spin_lock_irqsave(&dev_priv->error_lock, flags);
+        if (dev_priv->first_error == NULL) {
+                dev_priv->first_error = error;
+                error = NULL;
+        }
         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+
+        if (error)
+                i915_error_state_free(dev, error);
+}
+
+void i915_destroy_error_state(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_error_state *error;
+
+        spin_lock(&dev_priv->error_lock);
+        error = dev_priv->first_error;
+        dev_priv->first_error = NULL;
+        spin_unlock(&dev_priv->error_lock);
+
+        if (error)
+                i915_error_state_free(dev, error);
 }
 
 /**
@@ -512,7 +825,6 @@ static void i915_handle_error(struct drm_device *dev, bool wedged)
                 /*
                  * Wakeup waiting processes so they don't hang
                  */
-                printk("i915: Waking up sleeping processes\n");
                 DRM_WAKEUP(&dev_priv->irq_queue);
         }
 
@@ -535,8 +847,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
         atomic_inc(&dev_priv->irq_received);
 
-        if (IS_IGDNG(dev))
-                return igdng_irq_handler(dev);
+        if (HAS_PCH_SPLIT(dev))
+                return ironlake_irq_handler(dev);
 
         iir = I915_READ(IIR);
 
@@ -568,14 +880,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                  */
                 if (pipea_stats & 0x8000ffff) {
                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
-                                DRM_DEBUG("pipe a underrun\n");
+                                DRM_DEBUG_DRIVER("pipe a underrun\n");
                         I915_WRITE(PIPEASTAT, pipea_stats);
                         irq_received = 1;
                 }
 
                 if (pipeb_stats & 0x8000ffff) {
                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
-                                DRM_DEBUG("pipe b underrun\n");
+                                DRM_DEBUG_DRIVER("pipe b underrun\n");
                         I915_WRITE(PIPEBSTAT, pipeb_stats);
                         irq_received = 1;
                 }
@@ -591,7 +903,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 
-                        DRM_DEBUG("hotplug event received, stat 0x%08x\n",
+                        DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
                                   hotplug_status);
                         if (hotplug_status & dev_priv->hotplug_supported_mask)
                                 queue_work(dev_priv->wq,
@@ -599,27 +911,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
                         I915_READ(PORT_HOTPLUG_STAT);
-
-                        /* EOS interrupts occurs */
-                        if (IS_IGD(dev) &&
-                                (hotplug_status & CRT_EOS_INT_STATUS)) {
-                                u32 temp;
-
-                                DRM_DEBUG("EOS interrupt occurs\n");
-                                /* status is already cleared */
-                                temp = I915_READ(ADPA);
-                                temp &= ~ADPA_DAC_ENABLE;
-                                I915_WRITE(ADPA, temp);
-
-                                temp = I915_READ(PORT_HOTPLUG_EN);
-                                temp &= ~CRT_EOS_INT_EN;
-                                I915_WRITE(PORT_HOTPLUG_EN, temp);
-
-                                temp = I915_READ(PORT_HOTPLUG_STAT);
-                                if (temp & CRT_EOS_INT_STATUS)
-                                        I915_WRITE(PORT_HOTPLUG_STAT,
-                                                CRT_EOS_INT_STATUS);
-                        }
                 }
 
                 I915_WRITE(IIR, iir);
@@ -641,14 +932,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
                 }
 
+                if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
+                        intel_prepare_page_flip(dev, 0);
+
+                if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
+                        intel_prepare_page_flip(dev, 1);
+
                 if (pipea_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 0);
+                        intel_finish_page_flip(dev, 0);
                 }
 
                 if (pipeb_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 1);
+                        intel_finish_page_flip(dev, 1);
                 }
 
                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
@@ -684,7 +983,7 @@ static int i915_emit_irq(struct drm_device * dev)
 
         i915_kernel_lost_context(dev);
 
-        DRM_DEBUG("\n");
+        DRM_DEBUG_DRIVER("\n");
 
         dev_priv->counter++;
         if (dev_priv->counter > 0x7FFFFFFFUL)
@@ -709,8 +1008,8 @@ void i915_user_irq_get(struct drm_device *dev)
 
         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
-                if (IS_IGDNG(dev))
-                        igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+                if (HAS_PCH_SPLIT(dev))
+                        ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
                 else
                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
         }
@@ -725,8 +1024,8 @@ void i915_user_irq_put(struct drm_device *dev)
         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
-                if (IS_IGDNG(dev))
-                        igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+                if (HAS_PCH_SPLIT(dev))
+                        ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
                 else
                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
         }
@@ -749,7 +1048,7 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
         int ret = 0;
 
-        DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
+        DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
                   READ_BREADCRUMB(dev_priv));
 
         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
@@ -832,11 +1131,11 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
         if (!(pipeconf & PIPEACONF_ENABLE))
                 return -EINVAL;
 
-        if (IS_IGDNG(dev))
-                return 0;
-
         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
-        if (IS_I965G(dev))
+        if (HAS_PCH_SPLIT(dev))
+                ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 
+                                            DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+        else if (IS_I965G(dev))
                 i915_enable_pipestat(dev_priv, pipe,
                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
         else
@@ -854,13 +1153,14 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         unsigned long irqflags;
 
-        if (IS_IGDNG(dev))
-                return;
-
         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
-        i915_disable_pipestat(dev_priv, pipe,
-                              PIPE_VBLANK_INTERRUPT_ENABLE |
-                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
+        if (HAS_PCH_SPLIT(dev))
+                ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 
+                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+        else
+                i915_disable_pipestat(dev_priv, pipe,
+                                      PIPE_VBLANK_INTERRUPT_ENABLE |
+                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 }
 
@@ -868,7 +1168,7 @@ void i915_enable_interrupt (struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (!IS_IGDNG(dev))
+        if (!HAS_PCH_SPLIT(dev))
                 opregion_enable_asle(dev);
         dev_priv->irq_enabled = 1;
 }
@@ -944,7 +1244,11 @@ void i915_hangcheck_elapsed(unsigned long data)
         struct drm_device *dev = (struct drm_device *)data;
         drm_i915_private_t *dev_priv = dev->dev_private;
         uint32_t acthd;
-       
+
+        /* No reset support on this chip yet. */
+        if (IS_GEN6(dev))
+                return;
+
         if (!IS_I965G(dev))
                 acthd = I915_READ(ACTHD);
         else
@@ -976,7 +1280,7 @@ void i915_hangcheck_elapsed(unsigned long data)
 
 /* drm_dma.h hooks
 */
-static void igdng_irq_preinstall(struct drm_device *dev)
+static void ironlake_irq_preinstall(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
@@ -992,17 +1296,25 @@ static void igdng_irq_preinstall(struct drm_device *dev)
         I915_WRITE(GTIMR, 0xffffffff);
         I915_WRITE(GTIER, 0x0);
         (void) I915_READ(GTIER);
+
+        /* south display irq */
+        I915_WRITE(SDEIMR, 0xffffffff);
+        I915_WRITE(SDEIER, 0x0);
+        (void) I915_READ(SDEIER);
 }
 
-static int igdng_irq_postinstall(struct drm_device *dev)
+static int ironlake_irq_postinstall(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         /* enable kind of interrupts always enabled */
-        u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
-        u32 render_mask = GT_USER_INTERRUPT;
+        u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
+                           DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
+        u32 render_mask = GT_PIPE_NOTIFY;
+        u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
+                           SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
 
         dev_priv->irq_mask_reg = ~display_mask;
-        dev_priv->de_irq_enable_reg = display_mask;
+        dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
 
         /* should always can generate irq */
         I915_WRITE(DEIIR, I915_READ(DEIIR));
@@ -1019,6 +1331,21 @@ static int igdng_irq_postinstall(struct drm_device *dev)
         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
         (void) I915_READ(GTIER);
 
+        dev_priv->pch_irq_mask_reg = ~hotplug_mask;
+        dev_priv->pch_irq_enable_reg = hotplug_mask;
+
+        I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+        I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
+        I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
+        (void) I915_READ(SDEIER);
+
+        if (IS_IRONLAKE_M(dev)) {
+                /* Clear & enable PCU event interrupts */
+                I915_WRITE(DEIIR, DE_PCU_EVENT);
+                I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
+                ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
+        }
+
         return 0;
 }
 
@@ -1031,8 +1358,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
 
-        if (IS_IGDNG(dev)) {
-                igdng_irq_preinstall(dev);
+        if (HAS_PCH_SPLIT(dev)) {
+                ironlake_irq_preinstall(dev);
                 return;
         }
 
@@ -1049,6 +1376,10 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
         (void) I915_READ(IER);
 }
 
+/*
+ * Must be called after intel_modeset_init or hotplug interrupts won't be
+ * enabled correctly.
+ */
 int i915_driver_irq_postinstall(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1059,8 +1390,8 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 
         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
-        if (IS_IGDNG(dev))
-                return igdng_irq_postinstall(dev);
+        if (HAS_PCH_SPLIT(dev))
+                return ironlake_irq_postinstall(dev);
 
         /* Unmask the interrupts that we always want on. */
         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
@@ -1071,19 +1402,23 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         if (I915_HAS_HOTPLUG(dev)) {
                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 
-                /* Leave other bits alone */
-                hotplug_en |= HOTPLUG_EN_MASK;
+                /* Note HDMI and DP share bits */
+                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
+                        hotplug_en |= CRT_HOTPLUG_INT_EN;
+                /* Ignore TV since it's buggy */
+
                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 
-                dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
-                        TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
-                        SDVOB_HOTPLUG_INT_STATUS;
-                if (IS_G4X(dev)) {
-                        dev_priv->hotplug_supported_mask |=
-                                HDMIB_HOTPLUG_INT_STATUS |
-                                HDMIC_HOTPLUG_INT_STATUS |
-                                HDMID_HOTPLUG_INT_STATUS;
-                }
                 /* Enable in IER... */
                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
                 /* and unmask in IMR */
@@ -1120,7 +1455,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         return 0;
 }
 
-static void igdng_irq_uninstall(struct drm_device *dev)
+static void ironlake_irq_uninstall(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         I915_WRITE(HWSTAM, 0xffffffff);
@@ -1143,8 +1478,8 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
 
         dev_priv->vblank_pipe = 0;
 
-        if (IS_IGDNG(dev)) {
-                igdng_irq_uninstall(dev);
+        if (HAS_PCH_SPLIT(dev)) {
+                ironlake_irq_uninstall(dev);
                 return;
         }