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path: root/drivers/gpu/drm/i915/i915_gem_tiling.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 5c1ceec49f5b..a2d527b22ec4 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -114,11 +114,13 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
114 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 114 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
115 115
116 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 116 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
117#ifdef CONFIG_PNP
117 if (mchbar_addr && 118 if (mchbar_addr &&
118 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { 119 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
119 ret = 0; 120 ret = 0;
120 goto out_put; 121 goto out_put;
121 } 122 }
123#endif
122 124
123 /* Get some space for it */ 125 /* Get some space for it */
124 ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, 126 ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res,
@@ -519,6 +521,12 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
519 goto err; 521 goto err;
520 } 522 }
521 523
524 /* If we've changed tiling, GTT-mappings of the object
525 * need to re-fault to ensure that the correct fence register
526 * setup is in place.
527 */
528 i915_gem_release_mmap(obj);
529
522 obj_priv->tiling_mode = args->tiling_mode; 530 obj_priv->tiling_mode = args->tiling_mode;
523 obj_priv->stride = args->stride; 531 obj_priv->stride = args->stride;
524 } 532 }