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path: root/drivers/gpu/drm/i915/i915_gem_debug.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_debug.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_debug.c148
1 files changed, 98 insertions, 50 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c
index 80f380b1d951..48644b840a8d 100644
--- a/drivers/gpu/drm/i915/i915_gem_debug.c
+++ b/drivers/gpu/drm/i915/i915_gem_debug.c
@@ -30,29 +30,112 @@
30#include "i915_drm.h" 30#include "i915_drm.h"
31#include "i915_drv.h" 31#include "i915_drv.h"
32 32
33#if WATCH_INACTIVE 33#if WATCH_LISTS
34void 34int
35i915_verify_inactive(struct drm_device *dev, char *file, int line) 35i915_verify_lists(struct drm_device *dev)
36{ 36{
37 static int warned;
37 drm_i915_private_t *dev_priv = dev->dev_private; 38 drm_i915_private_t *dev_priv = dev->dev_private;
38 struct drm_gem_object *obj; 39 struct drm_i915_gem_object *obj;
39 struct drm_i915_gem_object *obj_priv; 40 int err = 0;
40 41
41 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { 42 if (warned)
42 obj = &obj_priv->base; 43 return 0;
43 if (obj_priv->pin_count || obj_priv->active || 44
44 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | 45 list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) {
45 I915_GEM_DOMAIN_GTT))) 46 if (obj->base.dev != dev ||
46 DRM_ERROR("inactive %p (p %d a %d w %x) %s:%d\n", 47 !atomic_read(&obj->base.refcount.refcount)) {
48 DRM_ERROR("freed render active %p\n", obj);
49 err++;
50 break;
51 } else if (!obj->active ||
52 (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
53 DRM_ERROR("invalid render active %p (a %d r %x)\n",
54 obj,
55 obj->active,
56 obj->base.read_domains);
57 err++;
58 } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
59 DRM_ERROR("invalid render active %p (w %x, gwl %d)\n",
60 obj,
61 obj->base.write_domain,
62 !list_empty(&obj->gpu_write_list));
63 err++;
64 }
65 }
66
67 list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) {
68 if (obj->base.dev != dev ||
69 !atomic_read(&obj->base.refcount.refcount)) {
70 DRM_ERROR("freed flushing %p\n", obj);
71 err++;
72 break;
73 } else if (!obj->active ||
74 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
75 list_empty(&obj->gpu_write_list)){
76 DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n",
47 obj, 77 obj,
48 obj_priv->pin_count, obj_priv->active, 78 obj->active,
49 obj->write_domain, file, line); 79 obj->base.write_domain,
80 !list_empty(&obj->gpu_write_list));
81 err++;
82 }
83 }
84
85 list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) {
86 if (obj->base.dev != dev ||
87 !atomic_read(&obj->base.refcount.refcount)) {
88 DRM_ERROR("freed gpu write %p\n", obj);
89 err++;
90 break;
91 } else if (!obj->active ||
92 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) {
93 DRM_ERROR("invalid gpu write %p (a %d w %x)\n",
94 obj,
95 obj->active,
96 obj->base.write_domain);
97 err++;
98 }
99 }
100
101 list_for_each_entry(obj, &dev_priv->mm.inactive_list, list) {
102 if (obj->base.dev != dev ||
103 !atomic_read(&obj->base.refcount.refcount)) {
104 DRM_ERROR("freed inactive %p\n", obj);
105 err++;
106 break;
107 } else if (obj->pin_count || obj->active ||
108 (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
109 DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n",
110 obj,
111 obj->pin_count, obj->active,
112 obj->base.write_domain);
113 err++;
114 }
50 } 115 }
116
117 list_for_each_entry(obj, &dev_priv->mm.pinned_list, list) {
118 if (obj->base.dev != dev ||
119 !atomic_read(&obj->base.refcount.refcount)) {
120 DRM_ERROR("freed pinned %p\n", obj);
121 err++;
122 break;
123 } else if (!obj->pin_count || obj->active ||
124 (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
125 DRM_ERROR("invalid pinned %p (p %d a %d w %x)\n",
126 obj,
127 obj->pin_count, obj->active,
128 obj->base.write_domain);
129 err++;
130 }
131 }
132
133 return warned = err;
51} 134}
52#endif /* WATCH_INACTIVE */ 135#endif /* WATCH_INACTIVE */
53 136
54 137
55#if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE 138#if WATCH_EXEC | WATCH_PWRITE
56static void 139static void
57i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end, 140i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
58 uint32_t bias, uint32_t mark) 141 uint32_t bias, uint32_t mark)
@@ -97,41 +180,6 @@ i915_gem_dump_object(struct drm_gem_object *obj, int len,
97} 180}
98#endif 181#endif
99 182
100#if WATCH_LRU
101void
102i915_dump_lru(struct drm_device *dev, const char *where)
103{
104 drm_i915_private_t *dev_priv = dev->dev_private;
105 struct drm_i915_gem_object *obj_priv;
106
107 DRM_INFO("active list %s {\n", where);
108 spin_lock(&dev_priv->mm.active_list_lock);
109 list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
110 list)
111 {
112 DRM_INFO(" %p: %08x\n", obj_priv,
113 obj_priv->last_rendering_seqno);
114 }
115 spin_unlock(&dev_priv->mm.active_list_lock);
116 DRM_INFO("}\n");
117 DRM_INFO("flushing list %s {\n", where);
118 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
119 list)
120 {
121 DRM_INFO(" %p: %08x\n", obj_priv,
122 obj_priv->last_rendering_seqno);
123 }
124 DRM_INFO("}\n");
125 DRM_INFO("inactive %s {\n", where);
126 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
127 DRM_INFO(" %p: %08x\n", obj_priv,
128 obj_priv->last_rendering_seqno);
129 }
130 DRM_INFO("}\n");
131}
132#endif
133
134
135#if WATCH_COHERENCY 183#if WATCH_COHERENCY
136void 184void
137i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle) 185i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-21 04:28:27 -0400