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path: root/drivers/gpu/drm/i915/i915_gem.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0d53eacd293f..b46a3fd17746 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3721,12 +3721,8 @@ i915_gem_load(struct drm_device *dev)
3721 3721
3722 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 3722 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3723 if (IS_GEN3(dev)) { 3723 if (IS_GEN3(dev)) {
3724 u32 tmp = I915_READ(MI_ARB_STATE); 3724 I915_WRITE(MI_ARB_STATE,
3725 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { 3725 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3726 /* arb state is a masked write, so set bit + bit in mask */
3727 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3728 I915_WRITE(MI_ARB_STATE, tmp);
3729 }
3730 } 3726 }
3731 3727
3732 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; 3728 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;