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path: root/drivers/gpu/drm/i915/i915_drv.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h28
1 files changed, 6 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19c0dd8e255e..16a6f6d187a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -946,23 +946,6 @@ struct intel_rps_ei {
946 u32 media_c0; 946 u32 media_c0;
947}; 947};
948 948
949struct intel_rps_bdw_cal {
950 u32 it_threshold_pct; /* interrupt, in percentage */
951 u32 eval_interval; /* evaluation interval, in us */
952 u32 last_ts;
953 u32 last_c0;
954 bool is_up;
955};
956
957struct intel_rps_bdw_turbo {
958 struct intel_rps_bdw_cal up;
959 struct intel_rps_bdw_cal down;
960 struct timer_list flip_timer;
961 u32 timeout;
962 atomic_t flip_received;
963 struct work_struct work_max_freq;
964};
965
966struct intel_gen6_power_mgmt { 949struct intel_gen6_power_mgmt {
967 /* work and pm_iir are protected by dev_priv->irq_lock */ 950 /* work and pm_iir are protected by dev_priv->irq_lock */
968 struct work_struct work; 951 struct work_struct work;
@@ -996,9 +979,6 @@ struct intel_gen6_power_mgmt {
996 bool enabled; 979 bool enabled;
997 struct delayed_work delayed_resume_work; 980 struct delayed_work delayed_resume_work;
998 981
999 bool is_bdw_sw_turbo; /* Switch of BDW software turbo */
1000 struct intel_rps_bdw_turbo sw_turbo; /* Calculate RP interrupt timing */
1001
1002 /* manual wa residency calculations */ 982 /* manual wa residency calculations */
1003 struct intel_rps_ei up_ei, down_ei; 983 struct intel_rps_ei up_ei, down_ei;
1004 984
@@ -2369,6 +2349,12 @@ int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2369int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2349int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2370 struct drm_file *file_priv); 2350 struct drm_file *file_priv);
2371void i915_gem_load(struct drm_device *dev); 2351void i915_gem_load(struct drm_device *dev);
2352unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2353 long target,
2354 unsigned flags);
2355#define I915_SHRINK_PURGEABLE 0x1
2356#define I915_SHRINK_UNBOUND 0x2
2357#define I915_SHRINK_BOUND 0x4
2372void *i915_gem_object_alloc(struct drm_device *dev); 2358void *i915_gem_object_alloc(struct drm_device *dev);
2373void i915_gem_object_free(struct drm_i915_gem_object *obj); 2359void i915_gem_object_free(struct drm_i915_gem_object *obj);
2374void i915_gem_object_init(struct drm_i915_gem_object *obj, 2360void i915_gem_object_init(struct drm_i915_gem_object *obj,
@@ -2823,8 +2809,6 @@ extern void intel_disable_fbc(struct drm_device *dev);
2823extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2809extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2824extern void intel_init_pch_refclk(struct drm_device *dev); 2810extern void intel_init_pch_refclk(struct drm_device *dev);
2825extern void gen6_set_rps(struct drm_device *dev, u8 val); 2811extern void gen6_set_rps(struct drm_device *dev, u8 val);
2826extern void bdw_software_turbo(struct drm_device *dev);
2827extern void gen8_flip_interrupt(struct drm_device *dev);
2828extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2812extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2829extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 2813extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2830 bool enable); 2814 bool enable);