diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 105 |
1 files changed, 91 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 359a2003086b..9e1bf6dcbb2a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -132,15 +132,38 @@ enum hpd_pin { | |||
132 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | 132 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
133 | if ((intel_encoder)->base.crtc == (__crtc)) | 133 | if ((intel_encoder)->base.crtc == (__crtc)) |
134 | 134 | ||
135 | struct intel_pch_pll { | 135 | struct drm_i915_private; |
136 | |||
137 | enum intel_dpll_id { | ||
138 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | ||
139 | /* real shared dpll ids must be >= 0 */ | ||
140 | DPLL_ID_PCH_PLL_A, | ||
141 | DPLL_ID_PCH_PLL_B, | ||
142 | }; | ||
143 | #define I915_NUM_PLLS 2 | ||
144 | |||
145 | struct intel_dpll_hw_state { | ||
146 | uint32_t dpll; | ||
147 | uint32_t fp0; | ||
148 | uint32_t fp1; | ||
149 | }; | ||
150 | |||
151 | struct intel_shared_dpll { | ||
136 | int refcount; /* count of number of CRTCs sharing this PLL */ | 152 | int refcount; /* count of number of CRTCs sharing this PLL */ |
137 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | 153 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
138 | bool on; /* is the PLL actually active? Disabled during modeset */ | 154 | bool on; /* is the PLL actually active? Disabled during modeset */ |
139 | int pll_reg; | 155 | const char *name; |
140 | int fp0_reg; | 156 | /* should match the index in the dev_priv->shared_dplls array */ |
141 | int fp1_reg; | 157 | enum intel_dpll_id id; |
158 | struct intel_dpll_hw_state hw_state; | ||
159 | void (*enable)(struct drm_i915_private *dev_priv, | ||
160 | struct intel_shared_dpll *pll); | ||
161 | void (*disable)(struct drm_i915_private *dev_priv, | ||
162 | struct intel_shared_dpll *pll); | ||
163 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, | ||
164 | struct intel_shared_dpll *pll, | ||
165 | struct intel_dpll_hw_state *hw_state); | ||
142 | }; | 166 | }; |
143 | #define I915_NUM_PLLS 2 | ||
144 | 167 | ||
145 | /* Used by dp and fdi links */ | 168 | /* Used by dp and fdi links */ |
146 | struct intel_link_m_n { | 169 | struct intel_link_m_n { |
@@ -195,7 +218,6 @@ struct opregion_header; | |||
195 | struct opregion_acpi; | 218 | struct opregion_acpi; |
196 | struct opregion_swsci; | 219 | struct opregion_swsci; |
197 | struct opregion_asle; | 220 | struct opregion_asle; |
198 | struct drm_i915_private; | ||
199 | 221 | ||
200 | struct intel_opregion { | 222 | struct intel_opregion { |
201 | struct opregion_header __iomem *header; | 223 | struct opregion_header __iomem *header; |
@@ -306,6 +328,8 @@ struct drm_i915_error_state { | |||
306 | 328 | ||
307 | struct intel_crtc_config; | 329 | struct intel_crtc_config; |
308 | struct intel_crtc; | 330 | struct intel_crtc; |
331 | struct intel_limit; | ||
332 | struct dpll; | ||
309 | 333 | ||
310 | struct drm_i915_display_funcs { | 334 | struct drm_i915_display_funcs { |
311 | bool (*fbc_enabled)(struct drm_device *dev); | 335 | bool (*fbc_enabled)(struct drm_device *dev); |
@@ -313,6 +337,24 @@ struct drm_i915_display_funcs { | |||
313 | void (*disable_fbc)(struct drm_device *dev); | 337 | void (*disable_fbc)(struct drm_device *dev); |
314 | int (*get_display_clock_speed)(struct drm_device *dev); | 338 | int (*get_display_clock_speed)(struct drm_device *dev); |
315 | int (*get_fifo_size)(struct drm_device *dev, int plane); | 339 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
340 | /** | ||
341 | * find_dpll() - Find the best values for the PLL | ||
342 | * @limit: limits for the PLL | ||
343 | * @crtc: current CRTC | ||
344 | * @target: target frequency in kHz | ||
345 | * @refclk: reference clock frequency in kHz | ||
346 | * @match_clock: if provided, @best_clock P divider must | ||
347 | * match the P divider from @match_clock | ||
348 | * used for LVDS downclocking | ||
349 | * @best_clock: best PLL values found | ||
350 | * | ||
351 | * Returns true on success, false on failure. | ||
352 | */ | ||
353 | bool (*find_dpll)(const struct intel_limit *limit, | ||
354 | struct drm_crtc *crtc, | ||
355 | int target, int refclk, | ||
356 | struct dpll *match_clock, | ||
357 | struct dpll *best_clock); | ||
316 | void (*update_wm)(struct drm_device *dev); | 358 | void (*update_wm)(struct drm_device *dev); |
317 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, | 359 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
318 | uint32_t sprite_width, int pixel_size, | 360 | uint32_t sprite_width, int pixel_size, |
@@ -466,6 +508,13 @@ struct i915_hw_ppgtt { | |||
466 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); | 508 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
467 | }; | 509 | }; |
468 | 510 | ||
511 | struct i915_ctx_hang_stats { | ||
512 | /* This context had batch pending when hang was declared */ | ||
513 | unsigned batch_pending; | ||
514 | |||
515 | /* This context had batch active when hang was declared */ | ||
516 | unsigned batch_active; | ||
517 | }; | ||
469 | 518 | ||
470 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | 519 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
471 | #define DEFAULT_CONTEXT_ID 0 | 520 | #define DEFAULT_CONTEXT_ID 0 |
@@ -476,6 +525,7 @@ struct i915_hw_context { | |||
476 | struct drm_i915_file_private *file_priv; | 525 | struct drm_i915_file_private *file_priv; |
477 | struct intel_ring_buffer *ring; | 526 | struct intel_ring_buffer *ring; |
478 | struct drm_i915_gem_object *obj; | 527 | struct drm_i915_gem_object *obj; |
528 | struct i915_ctx_hang_stats hang_stats; | ||
479 | }; | 529 | }; |
480 | 530 | ||
481 | enum no_fbc_reason { | 531 | enum no_fbc_reason { |
@@ -720,6 +770,15 @@ struct intel_ilk_power_mgmt { | |||
720 | struct drm_i915_gem_object *renderctx; | 770 | struct drm_i915_gem_object *renderctx; |
721 | }; | 771 | }; |
722 | 772 | ||
773 | /* Power well structure for haswell */ | ||
774 | struct i915_power_well { | ||
775 | struct drm_device *device; | ||
776 | spinlock_t lock; | ||
777 | /* power well enable/disable usage count */ | ||
778 | int count; | ||
779 | int i915_request; | ||
780 | }; | ||
781 | |||
723 | struct i915_dri1_state { | 782 | struct i915_dri1_state { |
724 | unsigned allow_batchbuffer : 1; | 783 | unsigned allow_batchbuffer : 1; |
725 | u32 __iomem *gfx_hws_cpu_addr; | 784 | u32 __iomem *gfx_hws_cpu_addr; |
@@ -842,7 +901,6 @@ struct i915_gpu_error { | |||
842 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | 901 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
843 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | 902 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
844 | struct timer_list hangcheck_timer; | 903 | struct timer_list hangcheck_timer; |
845 | int hangcheck_count; | ||
846 | 904 | ||
847 | /* For reset and error_state handling. */ | 905 | /* For reset and error_state handling. */ |
848 | spinlock_t lock; | 906 | spinlock_t lock; |
@@ -998,7 +1056,6 @@ typedef struct drm_i915_private { | |||
998 | u32 hpd_event_bits; | 1056 | u32 hpd_event_bits; |
999 | struct timer_list hotplug_reenable_timer; | 1057 | struct timer_list hotplug_reenable_timer; |
1000 | 1058 | ||
1001 | int num_pch_pll; | ||
1002 | int num_plane; | 1059 | int num_plane; |
1003 | 1060 | ||
1004 | unsigned long cfb_size; | 1061 | unsigned long cfb_size; |
@@ -1059,7 +1116,8 @@ typedef struct drm_i915_private { | |||
1059 | struct drm_crtc *pipe_to_crtc_mapping[3]; | 1116 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
1060 | wait_queue_head_t pending_flip_queue; | 1117 | wait_queue_head_t pending_flip_queue; |
1061 | 1118 | ||
1062 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; | 1119 | int num_shared_dpll; |
1120 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | ||
1063 | struct intel_ddi_plls ddi_plls; | 1121 | struct intel_ddi_plls ddi_plls; |
1064 | 1122 | ||
1065 | /* Reclocking support */ | 1123 | /* Reclocking support */ |
@@ -1080,6 +1138,9 @@ typedef struct drm_i915_private { | |||
1080 | * mchdev_lock in intel_pm.c */ | 1138 | * mchdev_lock in intel_pm.c */ |
1081 | struct intel_ilk_power_mgmt ips; | 1139 | struct intel_ilk_power_mgmt ips; |
1082 | 1140 | ||
1141 | /* Haswell power well */ | ||
1142 | struct i915_power_well power_well; | ||
1143 | |||
1083 | enum no_fbc_reason no_fbc_reason; | 1144 | enum no_fbc_reason no_fbc_reason; |
1084 | 1145 | ||
1085 | struct drm_mm_node *compressed_fb; | 1146 | struct drm_mm_node *compressed_fb; |
@@ -1154,7 +1215,7 @@ struct drm_i915_gem_object { | |||
1154 | struct drm_mm_node *gtt_space; | 1215 | struct drm_mm_node *gtt_space; |
1155 | /** Stolen memory for this object, instead of being backed by shmem. */ | 1216 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1156 | struct drm_mm_node *stolen; | 1217 | struct drm_mm_node *stolen; |
1157 | struct list_head gtt_list; | 1218 | struct list_head global_list; |
1158 | 1219 | ||
1159 | /** This object's place on the active/inactive lists */ | 1220 | /** This object's place on the active/inactive lists */ |
1160 | struct list_head ring_list; | 1221 | struct list_head ring_list; |
@@ -1301,12 +1362,18 @@ struct drm_i915_gem_request { | |||
1301 | /** GEM sequence number associated with this request. */ | 1362 | /** GEM sequence number associated with this request. */ |
1302 | uint32_t seqno; | 1363 | uint32_t seqno; |
1303 | 1364 | ||
1304 | /** Postion in the ringbuffer of the end of the request */ | 1365 | /** Position in the ringbuffer of the start of the request */ |
1366 | u32 head; | ||
1367 | |||
1368 | /** Position in the ringbuffer of the end of the request */ | ||
1305 | u32 tail; | 1369 | u32 tail; |
1306 | 1370 | ||
1307 | /** Context related to this request */ | 1371 | /** Context related to this request */ |
1308 | struct i915_hw_context *ctx; | 1372 | struct i915_hw_context *ctx; |
1309 | 1373 | ||
1374 | /** Batch buffer related to this request if any */ | ||
1375 | struct drm_i915_gem_object *batch_obj; | ||
1376 | |||
1310 | /** Time at which this request was emitted, in jiffies. */ | 1377 | /** Time at which this request was emitted, in jiffies. */ |
1311 | unsigned long emitted_jiffies; | 1378 | unsigned long emitted_jiffies; |
1312 | 1379 | ||
@@ -1324,6 +1391,8 @@ struct drm_i915_file_private { | |||
1324 | struct list_head request_list; | 1391 | struct list_head request_list; |
1325 | } mm; | 1392 | } mm; |
1326 | struct idr context_idr; | 1393 | struct idr context_idr; |
1394 | |||
1395 | struct i915_ctx_hang_stats hang_stats; | ||
1327 | }; | 1396 | }; |
1328 | 1397 | ||
1329 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) | 1398 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
@@ -1660,6 +1729,7 @@ i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |||
1660 | { | 1729 | { |
1661 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | 1730 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
1662 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | 1731 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1732 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | ||
1663 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | 1733 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
1664 | } | 1734 | } |
1665 | } | 1735 | } |
@@ -1692,9 +1762,12 @@ void i915_gem_init_swizzling(struct drm_device *dev); | |||
1692 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | 1762 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
1693 | int __must_check i915_gpu_idle(struct drm_device *dev); | 1763 | int __must_check i915_gpu_idle(struct drm_device *dev); |
1694 | int __must_check i915_gem_idle(struct drm_device *dev); | 1764 | int __must_check i915_gem_idle(struct drm_device *dev); |
1695 | int i915_add_request(struct intel_ring_buffer *ring, | 1765 | int __i915_add_request(struct intel_ring_buffer *ring, |
1696 | struct drm_file *file, | 1766 | struct drm_file *file, |
1697 | u32 *seqno); | 1767 | struct drm_i915_gem_object *batch_obj, |
1768 | u32 *seqno); | ||
1769 | #define i915_add_request(ring, seqno) \ | ||
1770 | __i915_add_request(ring, NULL, NULL, seqno) | ||
1698 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, | 1771 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1699 | uint32_t seqno); | 1772 | uint32_t seqno); |
1700 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); | 1773 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
@@ -1748,6 +1821,10 @@ static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) | |||
1748 | kref_put(&ctx->ref, i915_gem_context_free); | 1821 | kref_put(&ctx->ref, i915_gem_context_free); |
1749 | } | 1822 | } |
1750 | 1823 | ||
1824 | struct i915_ctx_hang_stats * __must_check | ||
1825 | i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring, | ||
1826 | struct drm_file *file, | ||
1827 | u32 id); | ||
1751 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | 1828 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1752 | struct drm_file *file); | 1829 | struct drm_file *file); |
1753 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | 1830 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |