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path: root/drivers/gpu/drm/i915/i915_dma.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 1851ca4087f9..7a26f4dd21ae 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -499,7 +499,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
499 } 499 }
500 500
501 501
502 if (IS_G4X(dev) || IS_IRONLAKE(dev)) { 502 if (IS_G4X(dev) || IS_GEN5(dev)) {
503 BEGIN_LP_RING(2); 503 BEGIN_LP_RING(2);
504 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); 504 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
505 OUT_RING(MI_NOOP); 505 OUT_RING(MI_NOOP);
@@ -1995,7 +1995,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1995 1995
1996 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1996 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1997 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 1997 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1998 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { 1998 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1999 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 1999 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2000 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2000 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2001 } 2001 }
@@ -2019,7 +2019,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2019 2019
2020 if (IS_PINEVIEW(dev)) 2020 if (IS_PINEVIEW(dev))
2021 i915_pineview_get_mem_freq(dev); 2021 i915_pineview_get_mem_freq(dev);
2022 else if (IS_IRONLAKE(dev)) 2022 else if (IS_GEN5(dev))
2023 i915_ironlake_get_mem_freq(dev); 2023 i915_ironlake_get_mem_freq(dev);
2024 2024
2025 /* On the 945G/GM, the chipset reports the MSI capability on the 2025 /* On the 945G/GM, the chipset reports the MSI capability on the