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path: root/drivers/gpu/drm/i915/i915_dma.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 81f1cff56fd5..6dab63bdc4c1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -202,7 +202,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
202 dev_priv->ring.map.flags = 0; 202 dev_priv->ring.map.flags = 0;
203 dev_priv->ring.map.mtrr = 0; 203 dev_priv->ring.map.mtrr = 0;
204 204
205 drm_core_ioremap(&dev_priv->ring.map, dev); 205 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
206 206
207 if (dev_priv->ring.map.handle == NULL) { 207 if (dev_priv->ring.map.handle == NULL) {
208 i915_dma_cleanup(dev); 208 i915_dma_cleanup(dev);
@@ -811,7 +811,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
811 dev_priv->hws_map.flags = 0; 811 dev_priv->hws_map.flags = 0;
812 dev_priv->hws_map.mtrr = 0; 812 dev_priv->hws_map.mtrr = 0;
813 813
814 drm_core_ioremap(&dev_priv->hws_map, dev); 814 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
815 if (dev_priv->hws_map.handle == NULL) { 815 if (dev_priv->hws_map.handle == NULL) {
816 i915_dma_cleanup(dev); 816 i915_dma_cleanup(dev);
817 dev_priv->status_gfx_addr = 0; 817 dev_priv->status_gfx_addr = 0;
@@ -1090,6 +1090,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1090 dev_priv->mm.gtt_mapping = 1090 dev_priv->mm.gtt_mapping =
1091 io_mapping_create_wc(dev->agp->base, 1091 io_mapping_create_wc(dev->agp->base,
1092 dev->agp->agp_info.aper_size * 1024*1024); 1092 dev->agp->agp_info.aper_size * 1024*1024);
1093 if (dev_priv->mm.gtt_mapping == NULL) {
1094 ret = -EIO;
1095 goto out_rmmap;
1096 }
1097
1093 /* Set up a WC MTRR for non-PAT systems. This is more common than 1098 /* Set up a WC MTRR for non-PAT systems. This is more common than
1094 * one would think, because the kernel disables PAT on first 1099 * one would think, because the kernel disables PAT on first
1095 * generation Core chips because WC PAT gets overridden by a UC 1100 * generation Core chips because WC PAT gets overridden by a UC
@@ -1122,7 +1127,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1122 if (!I915_NEED_GFX_HWS(dev)) { 1127 if (!I915_NEED_GFX_HWS(dev)) {
1123 ret = i915_init_phys_hws(dev); 1128 ret = i915_init_phys_hws(dev);
1124 if (ret != 0) 1129 if (ret != 0)
1125 goto out_rmmap; 1130 goto out_iomapfree;
1126 } 1131 }
1127 1132
1128 /* On the 945G/GM, the chipset reports the MSI capability on the 1133 /* On the 945G/GM, the chipset reports the MSI capability on the
@@ -1161,6 +1166,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1161 1166
1162 return 0; 1167 return 0;
1163 1168
1169out_iomapfree:
1170 io_mapping_free(dev_priv->mm.gtt_mapping);
1164out_rmmap: 1171out_rmmap:
1165 iounmap(dev_priv->regs); 1172 iounmap(dev_priv->regs);
1166free_priv: 1173free_priv: