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path: root/drivers/gpu/drm/gma500/psb_intel_reg.h
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Diffstat (limited to 'drivers/gpu/drm/gma500/psb_intel_reg.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_reg.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h
index fcc0af03d685..e89d3a2e8fdc 100644
--- a/drivers/gpu/drm/gma500/psb_intel_reg.h
+++ b/drivers/gpu/drm/gma500/psb_intel_reg.h
@@ -177,6 +177,9 @@
177#define LVDSPP_OFF 0x6120c 177#define LVDSPP_OFF 0x6120c
178#define PP_CYCLE 0x61210 178#define PP_CYCLE 0x61210
179 179
180#define PP_ON_DELAYS 0x61208 /* Cedartrail */
181#define PP_OFF_DELAYS 0x6120c /* Cedartrail */
182
180#define PFIT_CONTROL 0x61230 183#define PFIT_CONTROL 0x61230
181#define PFIT_ENABLE (1 << 31) 184#define PFIT_ENABLE (1 << 31)
182#define PFIT_PIPE_MASK (3 << 29) 185#define PFIT_PIPE_MASK (3 << 29)
@@ -1252,6 +1255,12 @@ No status bits are changed.
1252# define SB_BYTE_ENABLE_SHIFT 4 1255# define SB_BYTE_ENABLE_SHIFT 4
1253# define SB_BUSY (1 << 0) 1256# define SB_BUSY (1 << 0)
1254 1257
1258#define DSPCLK_GATE_D 0x6200
1259# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */
1260# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1261# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
1262
1263#define RAMCLK_GATE_D 0x6210
1255 1264
1256/* 32-bit value read/written from the DPIO reg. */ 1265/* 32-bit value read/written from the DPIO reg. */
1257#define SB_DATA 0x02104 /* cedarview */ 1266#define SB_DATA 0x02104 /* cedarview */