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path: root/drivers/gpu/drm/gma500/oaktrail_hdmi.c
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Diffstat (limited to 'drivers/gpu/drm/gma500/oaktrail_hdmi.c')
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_hdmi.c401
1 files changed, 38 insertions, 363 deletions
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
index 025d30970cc0..f8b367b45f66 100644
--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
@@ -125,59 +125,6 @@ static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = {
125 .nf = { .min = NF_MIN, .max = NF_MAX }, 125 .nf = { .min = NF_MIN, .max = NF_MAX },
126}; 126};
127 127
128static void wait_for_vblank(struct drm_device *dev)
129{
130 /* FIXME: Can we do this as a sleep ? */
131 /* Wait for 20ms, i.e. one cycle at 50hz. */
132 mdelay(20);
133}
134
135static void scu_busy_loop(void *scu_base)
136{
137 u32 status = 0;
138 u32 loop_count = 0;
139
140 status = readl(scu_base + 0x04);
141 while (status & 1) {
142 udelay(1); /* scu processing time is in few u secods */
143 status = readl(scu_base + 0x04);
144 loop_count++;
145 /* break if scu doesn't reset busy bit after huge retry */
146 if (loop_count > 1000) {
147 DRM_DEBUG_KMS("SCU IPC timed out");
148 return;
149 }
150 }
151}
152
153static void oaktrail_hdmi_reset(struct drm_device *dev)
154{
155 void *base;
156 /* FIXME: at least make these defines */
157 unsigned int scu_ipc_mmio = 0xff11c000;
158 int scu_len = 1024;
159
160 base = ioremap((resource_size_t)scu_ipc_mmio, scu_len);
161 if (base == NULL) {
162 DRM_ERROR("failed to map SCU mmio\n");
163 return;
164 }
165
166 /* scu ipc: assert hdmi controller reset */
167 writel(0xff11d118, base + 0x0c);
168 writel(0x7fffffdf, base + 0x80);
169 writel(0x42005, base + 0x0);
170 scu_busy_loop(base);
171
172 /* scu ipc: de-assert hdmi controller reset */
173 writel(0xff11d118, base + 0x0c);
174 writel(0x7fffffff, base + 0x80);
175 writel(0x42005, base + 0x0);
176 scu_busy_loop(base);
177
178 iounmap(base);
179}
180
181static void oaktrail_hdmi_audio_enable(struct drm_device *dev) 128static void oaktrail_hdmi_audio_enable(struct drm_device *dev)
182{ 129{
183 struct drm_psb_private *dev_priv = dev->dev_private; 130 struct drm_psb_private *dev_priv = dev->dev_private;
@@ -208,104 +155,6 @@ static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
208 HDMI_READ(HDMI_HCR); 155 HDMI_READ(HDMI_HCR);
209} 156}
210 157
211void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
212{
213 struct drm_device *dev = crtc->dev;
214 u32 temp;
215
216 switch (mode) {
217 case DRM_MODE_DPMS_OFF:
218 /* Disable VGACNTRL */
219 REG_WRITE(VGACNTRL, 0x80000000);
220
221 /* Disable plane */
222 temp = REG_READ(DSPBCNTR);
223 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
224 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
225 REG_READ(DSPBCNTR);
226 /* Flush the plane changes */
227 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
228 REG_READ(DSPBSURF);
229 }
230
231 /* Disable pipe B */
232 temp = REG_READ(PIPEBCONF);
233 if ((temp & PIPEACONF_ENABLE) != 0) {
234 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
235 REG_READ(PIPEBCONF);
236 }
237
238 /* Disable LNW Pipes, etc */
239 temp = REG_READ(PCH_PIPEBCONF);
240 if ((temp & PIPEACONF_ENABLE) != 0) {
241 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
242 REG_READ(PCH_PIPEBCONF);
243 }
244 /* wait for pipe off */
245 udelay(150);
246 /* Disable dpll */
247 temp = REG_READ(DPLL_CTRL);
248 if ((temp & DPLL_PWRDN) == 0) {
249 REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
250 REG_WRITE(DPLL_STATUS, 0x1);
251 }
252 /* wait for dpll off */
253 udelay(150);
254 break;
255 case DRM_MODE_DPMS_ON:
256 case DRM_MODE_DPMS_STANDBY:
257 case DRM_MODE_DPMS_SUSPEND:
258 /* Enable dpll */
259 temp = REG_READ(DPLL_CTRL);
260 if ((temp & DPLL_PWRDN) != 0) {
261 REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
262 temp = REG_READ(DPLL_CLK_ENABLE);
263 REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
264 REG_READ(DPLL_CLK_ENABLE);
265 }
266 /* wait for dpll warm up */
267 udelay(150);
268
269 /* Enable pipe B */
270 temp = REG_READ(PIPEBCONF);
271 if ((temp & PIPEACONF_ENABLE) == 0) {
272 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
273 REG_READ(PIPEBCONF);
274 }
275
276 /* Enable LNW Pipe B */
277 temp = REG_READ(PCH_PIPEBCONF);
278 if ((temp & PIPEACONF_ENABLE) == 0) {
279 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
280 REG_READ(PCH_PIPEBCONF);
281 }
282 wait_for_vblank(dev);
283
284 /* Enable plane */
285 temp = REG_READ(DSPBCNTR);
286 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
287 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
288 /* Flush the plane changes */
289 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
290 REG_READ(DSPBSURF);
291 }
292 psb_intel_crtc_load_lut(crtc);
293 }
294 /* DSPARB */
295 REG_WRITE(DSPARB, 0x00003fbf);
296 /* FW1 */
297 REG_WRITE(0x70034, 0x3f880a0a);
298 /* FW2 */
299 REG_WRITE(0x70038, 0x0b060808);
300 /* FW4 */
301 REG_WRITE(0x70050, 0x08030404);
302 /* FW5 */
303 REG_WRITE(0x70054, 0x04040404);
304 /* LNC Chicken Bits */
305 REG_WRITE(0x70400, 0x4000);
306}
307
308
309static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode) 158static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode)
310{ 159{
311 static int dpms_mode = -1; 160 static int dpms_mode = -1;
@@ -327,182 +176,6 @@ static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode)
327 HDMI_WRITE(HDMI_VIDEO_REG, temp); 176 HDMI_WRITE(HDMI_VIDEO_REG, temp);
328} 177}
329 178
330static unsigned int htotal_calculate(struct drm_display_mode *mode)
331{
332 u32 htotal, new_crtc_htotal;
333
334 htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16);
335
336 /*
337 * 1024 x 768 new_crtc_htotal = 0x1024;
338 * 1280 x 1024 new_crtc_htotal = 0x0c34;
339 */
340 new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock;
341
342 return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16);
343}
344
345static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc, int target,
346 int refclk, struct oaktrail_hdmi_clock *best_clock)
347{
348 int np_min, np_max, nr_min, nr_max;
349 int np, nr, nf;
350
351 np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10);
352 np_max = oaktrail_hdmi_limit.vco.max / (target * 10);
353 if (np_min < oaktrail_hdmi_limit.np.min)
354 np_min = oaktrail_hdmi_limit.np.min;
355 if (np_max > oaktrail_hdmi_limit.np.max)
356 np_max = oaktrail_hdmi_limit.np.max;
357
358 nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max));
359 nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min));
360 if (nr_min < oaktrail_hdmi_limit.nr.min)
361 nr_min = oaktrail_hdmi_limit.nr.min;
362 if (nr_max > oaktrail_hdmi_limit.nr.max)
363 nr_max = oaktrail_hdmi_limit.nr.max;
364
365 np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max));
366 nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np));
367 nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk);
368 DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf);
369
370 /*
371 * 1024 x 768 np = 1; nr = 0x26; nf = 0x0fd8000;
372 * 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000;
373 */
374 best_clock->np = np;
375 best_clock->nr = nr - 1;
376 best_clock->nf = (nf << 14);
377}
378
379int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc,
380 struct drm_display_mode *mode,
381 struct drm_display_mode *adjusted_mode,
382 int x, int y,
383 struct drm_framebuffer *old_fb)
384{
385 struct drm_device *dev = crtc->dev;
386 struct drm_psb_private *dev_priv = dev->dev_private;
387 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
388 int pipe = 1;
389 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
390 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
391 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
392 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
393 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
394 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
395 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
396 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
397 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
398 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
399 int refclk;
400 struct oaktrail_hdmi_clock clock;
401 u32 dspcntr, pipeconf, dpll, temp;
402 int dspcntr_reg = DSPBCNTR;
403
404 /* Disable the VGA plane that we never use */
405 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
406
407 /* XXX: Disable the panel fitter if it was on our pipe */
408
409 /* Disable dpll if necessary */
410 dpll = REG_READ(DPLL_CTRL);
411 if ((dpll & DPLL_PWRDN) == 0) {
412 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
413 REG_WRITE(DPLL_DIV_CTRL, 0x00000000);
414 REG_WRITE(DPLL_STATUS, 0x1);
415 }
416 udelay(150);
417
418 /* reset controller: FIXME - can we sort out the ioremap mess ? */
419 iounmap(hdmi_dev->regs);
420 oaktrail_hdmi_reset(dev);
421
422 /* program and enable dpll */
423 refclk = 25000;
424 oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock);
425
426 /* Setting DPLL */
427 dpll = REG_READ(DPLL_CTRL);
428 dpll &= ~DPLL_PDIV_MASK;
429 dpll &= ~(DPLL_PWRDN | DPLL_RESET);
430 REG_WRITE(DPLL_CTRL, 0x00000008);
431 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
432 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
433 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
434 REG_WRITE(DPLL_UPDATE, 0x80000000);
435 REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);
436 udelay(150);
437
438 hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
439 if (hdmi_dev->regs == NULL) {
440 DRM_ERROR("failed to do hdmi mmio mapping\n");
441 return -ENOMEM;
442 }
443
444 /* configure HDMI */
445 HDMI_WRITE(0x1004, 0x1fd);
446 HDMI_WRITE(0x2000, 0x1);
447 HDMI_WRITE(0x2008, 0x0);
448 HDMI_WRITE(0x3130, 0x8);
449 HDMI_WRITE(0x101c, 0x1800810);
450
451 temp = htotal_calculate(adjusted_mode);
452 REG_WRITE(htot_reg, temp);
453 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
454 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
455 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
456 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
457 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
458 REG_WRITE(pipesrc_reg,
459 ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
460
461 REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
462 REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
463 REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
464 REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
465 REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
466 REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
467 REG_WRITE(PCH_PIPEBSRC,
468 ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
469
470 temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
471 HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp);
472
473 REG_WRITE(dspsize_reg,
474 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
475 REG_WRITE(dsppos_reg, 0);
476
477 /* Flush the plane changes */
478 {
479 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
480 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
481 }
482
483 /* Set up the display plane register */
484 dspcntr = REG_READ(dspcntr_reg);
485 dspcntr |= DISPPLANE_GAMMA_ENABLE;
486 dspcntr |= DISPPLANE_SEL_PIPE_B;
487 dspcntr |= DISPLAY_PLANE_ENABLE;
488
489 /* setup pipeconf */
490 pipeconf = REG_READ(pipeconf_reg);
491 pipeconf |= PIPEACONF_ENABLE;
492
493 REG_WRITE(pipeconf_reg, pipeconf);
494 REG_READ(pipeconf_reg);
495
496 REG_WRITE(PCH_PIPEBCONF, pipeconf);
497 REG_READ(PCH_PIPEBCONF);
498 wait_for_vblank(dev);
499
500 REG_WRITE(dspcntr_reg, dspcntr);
501 wait_for_vblank(dev);
502
503 return 0;
504}
505
506static int oaktrail_hdmi_mode_valid(struct drm_connector *connector, 179static int oaktrail_hdmi_mode_valid(struct drm_connector *connector,
507 struct drm_display_mode *mode) 180 struct drm_display_mode *mode)
508{ 181{
@@ -692,7 +365,7 @@ failed_connector:
692 365
693static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = { 366static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = {
694 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) }, 367 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) },
695 {} 368 { 0 }
696}; 369};
697 370
698void oaktrail_hdmi_setup(struct drm_device *dev) 371void oaktrail_hdmi_setup(struct drm_device *dev)
@@ -766,6 +439,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
766{ 439{
767 struct drm_psb_private *dev_priv = dev->dev_private; 440 struct drm_psb_private *dev_priv = dev->dev_private;
768 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 441 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
442 struct psb_state *regs = &dev_priv->regs.psb;
769 int i; 443 int i;
770 444
771 /* dpll */ 445 /* dpll */
@@ -776,14 +450,14 @@ void oaktrail_hdmi_save(struct drm_device *dev)
776 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); 450 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
777 451
778 /* pipe B */ 452 /* pipe B */
779 dev_priv->savePIPEBCONF = PSB_RVDC32(PIPEBCONF); 453 regs->savePIPEBCONF = PSB_RVDC32(PIPEBCONF);
780 dev_priv->savePIPEBSRC = PSB_RVDC32(PIPEBSRC); 454 regs->savePIPEBSRC = PSB_RVDC32(PIPEBSRC);
781 dev_priv->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B); 455 regs->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B);
782 dev_priv->saveHBLANK_B = PSB_RVDC32(HBLANK_B); 456 regs->saveHBLANK_B = PSB_RVDC32(HBLANK_B);
783 dev_priv->saveHSYNC_B = PSB_RVDC32(HSYNC_B); 457 regs->saveHSYNC_B = PSB_RVDC32(HSYNC_B);
784 dev_priv->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B); 458 regs->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B);
785 dev_priv->saveVBLANK_B = PSB_RVDC32(VBLANK_B); 459 regs->saveVBLANK_B = PSB_RVDC32(VBLANK_B);
786 dev_priv->saveVSYNC_B = PSB_RVDC32(VSYNC_B); 460 regs->saveVSYNC_B = PSB_RVDC32(VSYNC_B);
787 461
788 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF); 462 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
789 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC); 463 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
@@ -795,21 +469,21 @@ void oaktrail_hdmi_save(struct drm_device *dev)
795 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B); 469 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
796 470
797 /* plane */ 471 /* plane */
798 dev_priv->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR); 472 regs->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR);
799 dev_priv->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE); 473 regs->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE);
800 dev_priv->saveDSPBADDR = PSB_RVDC32(DSPBBASE); 474 regs->saveDSPBADDR = PSB_RVDC32(DSPBBASE);
801 dev_priv->saveDSPBSURF = PSB_RVDC32(DSPBSURF); 475 regs->saveDSPBSURF = PSB_RVDC32(DSPBSURF);
802 dev_priv->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF); 476 regs->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF);
803 dev_priv->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF); 477 regs->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF);
804 478
805 /* cursor B */ 479 /* cursor B */
806 dev_priv->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR); 480 regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
807 dev_priv->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE); 481 regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
808 dev_priv->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS); 482 regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
809 483
810 /* save palette */ 484 /* save palette */
811 for (i = 0; i < 256; i++) 485 for (i = 0; i < 256; i++)
812 dev_priv->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2)); 486 regs->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2));
813} 487}
814 488
815/* restore HDMI register state */ 489/* restore HDMI register state */
@@ -817,6 +491,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
817{ 491{
818 struct drm_psb_private *dev_priv = dev->dev_private; 492 struct drm_psb_private *dev_priv = dev->dev_private;
819 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 493 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
494 struct psb_state *regs = &dev_priv->regs.psb;
820 int i; 495 int i;
821 496
822 /* dpll */ 497 /* dpll */
@@ -828,13 +503,13 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
828 DRM_UDELAY(150); 503 DRM_UDELAY(150);
829 504
830 /* pipe */ 505 /* pipe */
831 PSB_WVDC32(dev_priv->savePIPEBSRC, PIPEBSRC); 506 PSB_WVDC32(regs->savePIPEBSRC, PIPEBSRC);
832 PSB_WVDC32(dev_priv->saveHTOTAL_B, HTOTAL_B); 507 PSB_WVDC32(regs->saveHTOTAL_B, HTOTAL_B);
833 PSB_WVDC32(dev_priv->saveHBLANK_B, HBLANK_B); 508 PSB_WVDC32(regs->saveHBLANK_B, HBLANK_B);
834 PSB_WVDC32(dev_priv->saveHSYNC_B, HSYNC_B); 509 PSB_WVDC32(regs->saveHSYNC_B, HSYNC_B);
835 PSB_WVDC32(dev_priv->saveVTOTAL_B, VTOTAL_B); 510 PSB_WVDC32(regs->saveVTOTAL_B, VTOTAL_B);
836 PSB_WVDC32(dev_priv->saveVBLANK_B, VBLANK_B); 511 PSB_WVDC32(regs->saveVBLANK_B, VBLANK_B);
837 PSB_WVDC32(dev_priv->saveVSYNC_B, VSYNC_B); 512 PSB_WVDC32(regs->saveVSYNC_B, VSYNC_B);
838 513
839 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); 514 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
840 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); 515 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
@@ -844,22 +519,22 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
844 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); 519 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
845 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); 520 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
846 521
847 PSB_WVDC32(dev_priv->savePIPEBCONF, PIPEBCONF); 522 PSB_WVDC32(regs->savePIPEBCONF, PIPEBCONF);
848 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); 523 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
849 524
850 /* plane */ 525 /* plane */
851 PSB_WVDC32(dev_priv->saveDSPBLINOFF, DSPBLINOFF); 526 PSB_WVDC32(regs->saveDSPBLINOFF, DSPBLINOFF);
852 PSB_WVDC32(dev_priv->saveDSPBSTRIDE, DSPBSTRIDE); 527 PSB_WVDC32(regs->saveDSPBSTRIDE, DSPBSTRIDE);
853 PSB_WVDC32(dev_priv->saveDSPBTILEOFF, DSPBTILEOFF); 528 PSB_WVDC32(regs->saveDSPBTILEOFF, DSPBTILEOFF);
854 PSB_WVDC32(dev_priv->saveDSPBCNTR, DSPBCNTR); 529 PSB_WVDC32(regs->saveDSPBCNTR, DSPBCNTR);
855 PSB_WVDC32(dev_priv->saveDSPBSURF, DSPBSURF); 530 PSB_WVDC32(regs->saveDSPBSURF, DSPBSURF);
856 531
857 /* cursor B */ 532 /* cursor B */
858 PSB_WVDC32(dev_priv->saveDSPBCURSOR_CTRL, CURBCNTR); 533 PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
859 PSB_WVDC32(dev_priv->saveDSPBCURSOR_POS, CURBPOS); 534 PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS);
860 PSB_WVDC32(dev_priv->saveDSPBCURSOR_BASE, CURBBASE); 535 PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE);
861 536
862 /* restore palette */ 537 /* restore palette */
863 for (i = 0; i < 256; i++) 538 for (i = 0; i < 256; i++)
864 PSB_WVDC32(dev_priv->save_palette_b[i], PALETTE_B + (i << 2)); 539 PSB_WVDC32(regs->save_palette_b[i], PALETTE_B + (i << 2));
865} 540}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 06:28:24 -0400