1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index 0571ef9b889b..9bacce3ce53c 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -1778,6 +1778,28 @@ static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
         return false;
 }
 
+/* Cedarview display clock gating
+
+   We need this disable dot get correct behaviour while enabling
+   DP/eDP. TODO - investigate if we can turn it back to normality
+   after enabling */
+static void cdv_disable_intel_clock_gating(struct drm_device *dev)
+{
+        u32 reg_value;
+        reg_value = REG_READ(DSPCLK_GATE_D);
+
+        reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
+                        DPUNIT_PIPEA_GATE_DISABLE |
+                        DPCUNIT_CLOCK_GATE_DISABLE |
+                        DPLSUNIT_CLOCK_GATE_DISABLE |
+                        DPOUNIT_CLOCK_GATE_DISABLE |
+                        DPIOUNIT_CLOCK_GATE_DISABLE);   
+
+        REG_WRITE(DSPCLK_GATE_D, reg_value);
+
+        udelay(500);            
+}
+
 void
 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
 {
@@ -1841,6 +1863,8 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev
                         break;
         }
 
+        cdv_disable_intel_clock_gating(dev);
+
         cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
         /* FIXME:fail check */
         cdv_intel_dp_add_properties(connector);