aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/exynos/exynos_hdmi.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_hdmi.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c717
1 files changed, 248 insertions, 469 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2c5f266154ad..6652597586a1 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -108,7 +108,20 @@ struct hdmi_tg_regs {
108 u8 tg_3d[1]; 108 u8 tg_3d[1];
109}; 109};
110 110
111struct hdmi_core_regs { 111struct hdmi_v13_core_regs {
112 u8 h_blank[2];
113 u8 v_blank[3];
114 u8 h_v_line[3];
115 u8 vsync_pol[1];
116 u8 int_pro_mode[1];
117 u8 v_blank_f[3];
118 u8 h_sync_gen[3];
119 u8 v_sync_gen1[3];
120 u8 v_sync_gen2[3];
121 u8 v_sync_gen3[3];
122};
123
124struct hdmi_v14_core_regs {
112 u8 h_blank[2]; 125 u8 h_blank[2];
113 u8 v2_blank[2]; 126 u8 v2_blank[2];
114 u8 v1_blank[2]; 127 u8 v1_blank[2];
@@ -147,11 +160,23 @@ struct hdmi_core_regs {
147 u8 vact_space_6[2]; 160 u8 vact_space_6[2];
148}; 161};
149 162
163struct hdmi_v13_conf {
164 struct hdmi_v13_core_regs core;
165 struct hdmi_tg_regs tg;
166};
167
150struct hdmi_v14_conf { 168struct hdmi_v14_conf {
151 int pixel_clock; 169 struct hdmi_v14_core_regs core;
152 struct hdmi_core_regs core;
153 struct hdmi_tg_regs tg; 170 struct hdmi_tg_regs tg;
171};
172
173struct hdmi_conf_regs {
174 int pixel_clock;
154 int cea_video_id; 175 int cea_video_id;
176 union {
177 struct hdmi_v13_conf v13_conf;
178 struct hdmi_v14_conf v14_conf;
179 } conf;
155}; 180};
156 181
157struct hdmi_context { 182struct hdmi_context {
@@ -169,9 +194,8 @@ struct hdmi_context {
169 struct i2c_client *ddc_port; 194 struct i2c_client *ddc_port;
170 struct i2c_client *hdmiphy_port; 195 struct i2c_client *hdmiphy_port;
171 196
172 /* current hdmiphy conf index */ 197 /* current hdmiphy conf regs */
173 int cur_conf; 198 struct hdmi_conf_regs mode_conf;
174 struct hdmi_v14_conf mode_conf;
175 199
176 struct hdmi_resources res; 200 struct hdmi_resources res;
177 201
@@ -180,292 +204,60 @@ struct hdmi_context {
180 enum hdmi_type type; 204 enum hdmi_type type;
181}; 205};
182 206
183/* HDMI Version 1.3 */ 207struct hdmiphy_config {
184static const u8 hdmiphy_v13_conf27[32] = { 208 int pixel_clock;
185 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 209 u8 conf[32];
186 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
187 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
188 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
189};
190
191static const u8 hdmiphy_v13_conf27_027[32] = {
192 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
193 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
194 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
195 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
196};
197
198static const u8 hdmiphy_v13_conf74_175[32] = {
199 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
200 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
201 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
202 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
203};
204
205static const u8 hdmiphy_v13_conf74_25[32] = {
206 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
207 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
208 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
209 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
210};
211
212static const u8 hdmiphy_v13_conf148_5[32] = {
213 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
214 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
215 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
216 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
217};
218
219struct hdmi_v13_tg_regs {
220 u8 cmd;
221 u8 h_fsz_l;
222 u8 h_fsz_h;
223 u8 hact_st_l;
224 u8 hact_st_h;
225 u8 hact_sz_l;
226 u8 hact_sz_h;
227 u8 v_fsz_l;
228 u8 v_fsz_h;
229 u8 vsync_l;
230 u8 vsync_h;
231 u8 vsync2_l;
232 u8 vsync2_h;
233 u8 vact_st_l;
234 u8 vact_st_h;
235 u8 vact_sz_l;
236 u8 vact_sz_h;
237 u8 field_chg_l;
238 u8 field_chg_h;
239 u8 vact_st2_l;
240 u8 vact_st2_h;
241 u8 vsync_top_hdmi_l;
242 u8 vsync_top_hdmi_h;
243 u8 vsync_bot_hdmi_l;
244 u8 vsync_bot_hdmi_h;
245 u8 field_top_hdmi_l;
246 u8 field_top_hdmi_h;
247 u8 field_bot_hdmi_l;
248 u8 field_bot_hdmi_h;
249};
250
251struct hdmi_v13_core_regs {
252 u8 h_blank[2];
253 u8 v_blank[3];
254 u8 h_v_line[3];
255 u8 vsync_pol[1];
256 u8 int_pro_mode[1];
257 u8 v_blank_f[3];
258 u8 h_sync_gen[3];
259 u8 v_sync_gen1[3];
260 u8 v_sync_gen2[3];
261 u8 v_sync_gen3[3];
262};
263
264struct hdmi_v13_preset_conf {
265 struct hdmi_v13_core_regs core;
266 struct hdmi_v13_tg_regs tg;
267};
268
269struct hdmi_v13_conf {
270 int width;
271 int height;
272 int vrefresh;
273 bool interlace;
274 int cea_video_id;
275 const u8 *hdmiphy_data;
276 const struct hdmi_v13_preset_conf *conf;
277};
278
279static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
280 .core = {
281 .h_blank = {0x8a, 0x00},
282 .v_blank = {0x0d, 0x6a, 0x01},
283 .h_v_line = {0x0d, 0xa2, 0x35},
284 .vsync_pol = {0x01},
285 .int_pro_mode = {0x00},
286 .v_blank_f = {0x00, 0x00, 0x00},
287 .h_sync_gen = {0x0e, 0x30, 0x11},
288 .v_sync_gen1 = {0x0f, 0x90, 0x00},
289 /* other don't care */
290 },
291 .tg = {
292 0x00, /* cmd */
293 0x5a, 0x03, /* h_fsz */
294 0x8a, 0x00, 0xd0, 0x02, /* hact */
295 0x0d, 0x02, /* v_fsz */
296 0x01, 0x00, 0x33, 0x02, /* vsync */
297 0x2d, 0x00, 0xe0, 0x01, /* vact */
298 0x33, 0x02, /* field_chg */
299 0x49, 0x02, /* vact_st2 */
300 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
301 0x01, 0x00, 0x33, 0x02, /* field top/bot */
302 },
303};
304
305static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
306 .core = {
307 .h_blank = {0x72, 0x01},
308 .v_blank = {0xee, 0xf2, 0x00},
309 .h_v_line = {0xee, 0x22, 0x67},
310 .vsync_pol = {0x00},
311 .int_pro_mode = {0x00},
312 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
313 .h_sync_gen = {0x6c, 0x50, 0x02},
314 .v_sync_gen1 = {0x0a, 0x50, 0x00},
315 .v_sync_gen2 = {0x01, 0x10, 0x00},
316 .v_sync_gen3 = {0x01, 0x10, 0x00},
317 /* other don't care */
318 },
319 .tg = {
320 0x00, /* cmd */
321 0x72, 0x06, /* h_fsz */
322 0x71, 0x01, 0x01, 0x05, /* hact */
323 0xee, 0x02, /* v_fsz */
324 0x01, 0x00, 0x33, 0x02, /* vsync */
325 0x1e, 0x00, 0xd0, 0x02, /* vact */
326 0x33, 0x02, /* field_chg */
327 0x49, 0x02, /* vact_st2 */
328 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
329 0x01, 0x00, 0x33, 0x02, /* field top/bot */
330 },
331};
332
333static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
334 .core = {
335 .h_blank = {0xd0, 0x02},
336 .v_blank = {0x32, 0xB2, 0x00},
337 .h_v_line = {0x65, 0x04, 0xa5},
338 .vsync_pol = {0x00},
339 .int_pro_mode = {0x01},
340 .v_blank_f = {0x49, 0x2A, 0x23},
341 .h_sync_gen = {0x0E, 0xEA, 0x08},
342 .v_sync_gen1 = {0x07, 0x20, 0x00},
343 .v_sync_gen2 = {0x39, 0x42, 0x23},
344 .v_sync_gen3 = {0x38, 0x87, 0x73},
345 /* other don't care */
346 },
347 .tg = {
348 0x00, /* cmd */
349 0x50, 0x0A, /* h_fsz */
350 0xCF, 0x02, 0x81, 0x07, /* hact */
351 0x65, 0x04, /* v_fsz */
352 0x01, 0x00, 0x33, 0x02, /* vsync */
353 0x16, 0x00, 0x1c, 0x02, /* vact */
354 0x33, 0x02, /* field_chg */
355 0x49, 0x02, /* vact_st2 */
356 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
357 0x01, 0x00, 0x33, 0x02, /* field top/bot */
358 },
359}; 210};
360 211
361static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = { 212/* list of phy config settings */
362 .core = { 213static const struct hdmiphy_config hdmiphy_v13_configs[] = {
363 .h_blank = {0xd0, 0x02}, 214 {
364 .v_blank = {0x65, 0x6c, 0x01}, 215 .pixel_clock = 27000000,
365 .h_v_line = {0x65, 0x04, 0xa5}, 216 .conf = {
366 .vsync_pol = {0x00}, 217 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
367 .int_pro_mode = {0x00}, 218 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
368 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */ 219 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
369 .h_sync_gen = {0x0e, 0xea, 0x08}, 220 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
370 .v_sync_gen1 = {0x09, 0x40, 0x00}, 221 },
371 .v_sync_gen2 = {0x01, 0x10, 0x00},
372 .v_sync_gen3 = {0x01, 0x10, 0x00},
373 /* other don't care */
374 },
375 .tg = {
376 0x00, /* cmd */
377 0x50, 0x0A, /* h_fsz */
378 0xCF, 0x02, 0x81, 0x07, /* hact */
379 0x65, 0x04, /* v_fsz */
380 0x01, 0x00, 0x33, 0x02, /* vsync */
381 0x2d, 0x00, 0x38, 0x04, /* vact */
382 0x33, 0x02, /* field_chg */
383 0x48, 0x02, /* vact_st2 */
384 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
385 0x01, 0x00, 0x33, 0x02, /* field top/bot */
386 }, 222 },
387}; 223 {
388 224 .pixel_clock = 27027000,
389static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = { 225 .conf = {
390 .core = { 226 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
391 .h_blank = {0x18, 0x01}, 227 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
392 .v_blank = {0x32, 0xB2, 0x00}, 228 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
393 .h_v_line = {0x65, 0x84, 0x89}, 229 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
394 .vsync_pol = {0x00}, 230 },
395 .int_pro_mode = {0x01},
396 .v_blank_f = {0x49, 0x2A, 0x23},
397 .h_sync_gen = {0x56, 0x08, 0x02},
398 .v_sync_gen1 = {0x07, 0x20, 0x00},
399 .v_sync_gen2 = {0x39, 0x42, 0x23},
400 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
401 /* other don't care */
402 }, 231 },
403 .tg = { 232 {
404 0x00, /* cmd */ 233 .pixel_clock = 74176000,
405 0x98, 0x08, /* h_fsz */ 234 .conf = {
406 0x17, 0x01, 0x81, 0x07, /* hact */ 235 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
407 0x65, 0x04, /* v_fsz */ 236 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
408 0x01, 0x00, 0x33, 0x02, /* vsync */ 237 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
409 0x16, 0x00, 0x1c, 0x02, /* vact */ 238 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
410 0x33, 0x02, /* field_chg */ 239 },
411 0x49, 0x02, /* vact_st2 */
412 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
413 0x01, 0x00, 0x33, 0x02, /* field top/bot */
414 }, 240 },
415}; 241 {
416 242 .pixel_clock = 74250000,
417static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = { 243 .conf = {
418 .core = { 244 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
419 .h_blank = {0x18, 0x01}, 245 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
420 .v_blank = {0x65, 0x6c, 0x01}, 246 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
421 .h_v_line = {0x65, 0x84, 0x89}, 247 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
422 .vsync_pol = {0x00}, 248 },
423 .int_pro_mode = {0x00},
424 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
425 .h_sync_gen = {0x56, 0x08, 0x02},
426 .v_sync_gen1 = {0x09, 0x40, 0x00},
427 .v_sync_gen2 = {0x01, 0x10, 0x00},
428 .v_sync_gen3 = {0x01, 0x10, 0x00},
429 /* other don't care */
430 }, 249 },
431 .tg = { 250 {
432 0x00, /* cmd */ 251 .pixel_clock = 148500000,
433 0x98, 0x08, /* h_fsz */ 252 .conf = {
434 0x17, 0x01, 0x81, 0x07, /* hact */ 253 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
435 0x65, 0x04, /* v_fsz */ 254 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
436 0x01, 0x00, 0x33, 0x02, /* vsync */ 255 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
437 0x2d, 0x00, 0x38, 0x04, /* vact */ 256 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
438 0x33, 0x02, /* field_chg */ 257 },
439 0x48, 0x02, /* vact_st2 */
440 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
441 0x01, 0x00, 0x33, 0x02, /* field top/bot */
442 }, 258 },
443}; 259};
444 260
445static const struct hdmi_v13_conf hdmi_v13_confs[] = {
446 { 1280, 720, 60, false, 4, hdmiphy_v13_conf74_25,
447 &hdmi_v13_conf_720p60 },
448 { 1280, 720, 50, false, 19, hdmiphy_v13_conf74_25,
449 &hdmi_v13_conf_720p60 },
450 { 720, 480, 60, false, 3, hdmiphy_v13_conf27_027,
451 &hdmi_v13_conf_480p },
452 { 1920, 1080, 50, true, 20, hdmiphy_v13_conf74_25,
453 &hdmi_v13_conf_1080i50 },
454 { 1920, 1080, 50, false, 31, hdmiphy_v13_conf148_5,
455 &hdmi_v13_conf_1080p50 },
456 { 1920, 1080, 60, true, 5, hdmiphy_v13_conf74_25,
457 &hdmi_v13_conf_1080i60 },
458 { 1920, 1080, 60, false, 16, hdmiphy_v13_conf148_5,
459 &hdmi_v13_conf_1080p60 },
460};
461
462/* HDMI Version 1.4 */
463struct hdmiphy_config {
464 int pixel_clock;
465 u8 conf[32];
466};
467
468/* list of all required phy config settings */
469static const struct hdmiphy_config hdmiphy_v14_configs[] = { 261static const struct hdmiphy_config hdmiphy_v14_configs[] = {
470 { 262 {
471 .pixel_clock = 25200000, 263 .pixel_clock = 25200000,
@@ -873,22 +665,6 @@ static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
873 hdmi_v14_regs_dump(hdata, prefix); 665 hdmi_v14_regs_dump(hdata, prefix);
874} 666}
875 667
876static int hdmi_v13_conf_index(struct drm_display_mode *mode)
877{
878 int i;
879
880 for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
881 if (hdmi_v13_confs[i].width == mode->hdisplay &&
882 hdmi_v13_confs[i].height == mode->vdisplay &&
883 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
884 hdmi_v13_confs[i].interlace ==
885 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
886 true : false))
887 return i;
888
889 return -EINVAL;
890}
891
892static u8 hdmi_chksum(struct hdmi_context *hdata, 668static u8 hdmi_chksum(struct hdmi_context *hdata,
893 u32 start, u8 len, u32 hdr_sum) 669 u32 start, u8 len, u32 hdr_sum)
894{ 670{
@@ -943,11 +719,7 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
943 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio | 719 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
944 AVI_SAME_AS_PIC_ASPECT_RATIO); 720 AVI_SAME_AS_PIC_ASPECT_RATIO);
945 721
946 if (hdata->type == HDMI_TYPE13) 722 vic = hdata->mode_conf.cea_video_id;
947 vic = hdmi_v13_confs[hdata->cur_conf].cea_video_id;
948 else
949 vic = hdata->mode_conf.cea_video_id;
950
951 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic); 723 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
952 724
953 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1), 725 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
@@ -1000,63 +772,34 @@ static struct edid *hdmi_get_edid(void *ctx, struct drm_connector *connector)
1000 return raw_edid; 772 return raw_edid;
1001} 773}
1002 774
1003static int hdmi_v13_check_timing(struct fb_videomode *check_timing) 775static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
1004{ 776{
1005 int i; 777 const struct hdmiphy_config *confs;
1006 778 int count, i;
1007 DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
1008 check_timing->xres, check_timing->yres,
1009 check_timing->refresh, (check_timing->vmode &
1010 FB_VMODE_INTERLACED) ? true : false);
1011
1012 for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
1013 if (hdmi_v13_confs[i].width == check_timing->xres &&
1014 hdmi_v13_confs[i].height == check_timing->yres &&
1015 hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
1016 hdmi_v13_confs[i].interlace ==
1017 ((check_timing->vmode & FB_VMODE_INTERLACED) ?
1018 true : false))
1019 return 0;
1020 779
1021 /* TODO */ 780 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1022
1023 return -EINVAL;
1024}
1025 781
1026static int hdmi_v14_find_phy_conf(int pixel_clock) 782 if (hdata->type == HDMI_TYPE13) {
1027{ 783 confs = hdmiphy_v13_configs;
1028 int i; 784 count = ARRAY_SIZE(hdmiphy_v13_configs);
785 } else if (hdata->type == HDMI_TYPE14) {
786 confs = hdmiphy_v14_configs;
787 count = ARRAY_SIZE(hdmiphy_v14_configs);
788 } else
789 return -EINVAL;
1029 790
1030 for (i = 0; i < ARRAY_SIZE(hdmiphy_v14_configs); i++) { 791 for (i = 0; i < count; i++)
1031 if (hdmiphy_v14_configs[i].pixel_clock == pixel_clock) 792 if (confs[i].pixel_clock == pixel_clock)
1032 return i; 793 return i;
1033 }
1034 794
1035 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock); 795 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1036 return -EINVAL; 796 return -EINVAL;
1037} 797}
1038 798
1039static int hdmi_v14_check_timing(struct fb_videomode *check_timing)
1040{
1041 int i;
1042
1043 DRM_DEBUG_KMS("mode: xres=%d, yres=%d, refresh=%d, clock=%d, intl=%d\n",
1044 check_timing->xres, check_timing->yres,
1045 check_timing->refresh, check_timing->pixclock,
1046 (check_timing->vmode & FB_VMODE_INTERLACED) ?
1047 true : false);
1048
1049 for (i = 0; i < ARRAY_SIZE(hdmiphy_v14_configs); i++)
1050 if (hdmiphy_v14_configs[i].pixel_clock ==
1051 check_timing->pixclock)
1052 return 0;
1053
1054 return -EINVAL;
1055}
1056
1057static int hdmi_check_timing(void *ctx, struct fb_videomode *timing) 799static int hdmi_check_timing(void *ctx, struct fb_videomode *timing)
1058{ 800{
1059 struct hdmi_context *hdata = ctx; 801 struct hdmi_context *hdata = ctx;
802 int ret;
1060 803
1061 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 804 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1062 805
@@ -1064,10 +807,10 @@ static int hdmi_check_timing(void *ctx, struct fb_videomode *timing)
1064 timing->yres, timing->refresh, 807 timing->yres, timing->refresh,
1065 timing->vmode); 808 timing->vmode);
1066 809
1067 if (hdata->type == HDMI_TYPE13) 810 ret = hdmi_find_phy_conf(hdata, timing->pixclock);
1068 return hdmi_v13_check_timing(timing); 811 if (ret < 0)
1069 else 812 return ret;
1070 return hdmi_v14_check_timing(timing); 813 return 0;
1071} 814}
1072 815
1073static void hdmi_set_acr(u32 freq, u8 *acr) 816static void hdmi_set_acr(u32 freq, u8 *acr)
@@ -1301,10 +1044,9 @@ static void hdmi_conf_init(struct hdmi_context *hdata)
1301 1044
1302static void hdmi_v13_timing_apply(struct hdmi_context *hdata) 1045static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1303{ 1046{
1304 const struct hdmi_v13_preset_conf *conf = 1047 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1305 hdmi_v13_confs[hdata->cur_conf].conf; 1048 const struct hdmi_v13_core_regs *core =
1306 const struct hdmi_v13_core_regs *core = &conf->core; 1049 &hdata->mode_conf.conf.v13_conf.core;
1307 const struct hdmi_v13_tg_regs *tg = &conf->tg;
1308 int tries; 1050 int tries;
1309 1051
1310 /* setting core registers */ 1052 /* setting core registers */
@@ -1334,34 +1076,34 @@ static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1334 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]); 1076 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1335 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]); 1077 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1336 /* Timing generator registers */ 1078 /* Timing generator registers */
1337 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l); 1079 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1338 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h); 1080 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1339 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l); 1081 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1340 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h); 1082 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1341 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l); 1083 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1342 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h); 1084 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1343 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l); 1085 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1344 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h); 1086 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1345 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l); 1087 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1346 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h); 1088 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1347 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l); 1089 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1348 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h); 1090 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1349 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l); 1091 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1350 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h); 1092 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1351 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l); 1093 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1352 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h); 1094 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1353 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l); 1095 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1354 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h); 1096 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1355 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l); 1097 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1356 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h); 1098 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1357 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l); 1099 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1358 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h); 1100 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1359 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l); 1101 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1360 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h); 1102 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1361 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l); 1103 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1362 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h); 1104 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1363 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l); 1105 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1364 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h); 1106 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1365 1107
1366 /* waiting for HDMIPHY's PLL to get to steady state */ 1108 /* waiting for HDMIPHY's PLL to get to steady state */
1367 for (tries = 100; tries; --tries) { 1109 for (tries = 100; tries; --tries) {
@@ -1391,8 +1133,9 @@ static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1391 1133
1392static void hdmi_v14_timing_apply(struct hdmi_context *hdata) 1134static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1393{ 1135{
1394 struct hdmi_core_regs *core = &hdata->mode_conf.core; 1136 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1395 struct hdmi_tg_regs *tg = &hdata->mode_conf.tg; 1137 const struct hdmi_v14_core_regs *core =
1138 &hdata->mode_conf.conf.v14_conf.core;
1396 int tries; 1139 int tries;
1397 1140
1398 /* setting core registers */ 1141 /* setting core registers */
@@ -1624,17 +1367,16 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1624 } 1367 }
1625 1368
1626 /* pixel clock */ 1369 /* pixel clock */
1627 if (hdata->type == HDMI_TYPE13) { 1370 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1628 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data; 1371 if (i < 0) {
1629 } else { 1372 DRM_ERROR("failed to find hdmiphy conf\n");
1630 i = hdmi_v14_find_phy_conf(hdata->mode_conf.pixel_clock); 1373 return;
1631 if (i < 0) { 1374 }
1632 DRM_ERROR("failed to find hdmiphy conf\n");
1633 return;
1634 }
1635 1375
1376 if (hdata->type == HDMI_TYPE13)
1377 hdmiphy_data = hdmiphy_v13_configs[i].conf;
1378 else
1636 hdmiphy_data = hdmiphy_v14_configs[i].conf; 1379 hdmiphy_data = hdmiphy_v14_configs[i].conf;
1637 }
1638 1380
1639 memcpy(buffer, hdmiphy_data, 32); 1381 memcpy(buffer, hdmiphy_data, 32);
1640 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); 1382 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1687,75 +1429,121 @@ static void hdmi_conf_apply(struct hdmi_context *hdata)
1687 hdmi_regs_dump(hdata, "start"); 1429 hdmi_regs_dump(hdata, "start");
1688} 1430}
1689 1431
1690static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector, 1432static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1691 const struct drm_display_mode *mode,
1692 struct drm_display_mode *adjusted_mode)
1693{ 1433{
1694 struct drm_display_mode *m; 1434 int i;
1695 struct hdmi_context *hdata = ctx; 1435 BUG_ON(num_bytes > 4);
1696 int index; 1436 for (i = 0; i < num_bytes; i++)
1437 reg_pair[i] = (value >> (8 * i)) & 0xff;
1438}
1697 1439
1698 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 1440static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1441 struct drm_display_mode *m)
1442{
1443 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1444 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1445 unsigned int val;
1699 1446
1700 drm_mode_set_crtcinfo(adjusted_mode, 0); 1447 hdata->mode_conf.cea_video_id =
1448 drm_match_cea_mode((struct drm_display_mode *)m);
1449 hdata->mode_conf.pixel_clock = m->clock * 1000;
1701 1450
1702 if (hdata->type == HDMI_TYPE13) 1451 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1703 index = hdmi_v13_conf_index(adjusted_mode); 1452 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1704 else
1705 index = hdmi_v14_find_phy_conf(adjusted_mode->clock * 1000);
1706 1453
1707 /* just return if user desired mode exists. */ 1454 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1708 if (index >= 0) 1455 hdmi_set_reg(core->vsync_pol, 1, val);
1709 return; 1456
1457 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1458 hdmi_set_reg(core->int_pro_mode, 1, val);
1459
1460 val = (m->hsync_start - m->hdisplay - 2);
1461 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1462 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1463 hdmi_set_reg(core->h_sync_gen, 3, val);
1710 1464
1711 /* 1465 /*
1712 * otherwise, find the most suitable mode among modes and change it 1466 * Quirk requirement for exynos HDMI IP design,
1713 * to adjusted_mode. 1467 * 2 pixels less than the actual calculation for hsync_start
1468 * and end.
1714 */ 1469 */
1715 list_for_each_entry(m, &connector->modes, head) { 1470
1716 if (hdata->type == HDMI_TYPE13) 1471 /* Following values & calculations differ for different type of modes */
1717 index = hdmi_v13_conf_index(m); 1472 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1718 else 1473 /* Interlaced Mode */
1719 index = hdmi_v14_find_phy_conf(m->clock * 1000); 1474 val = ((m->vsync_end - m->vdisplay) / 2);
1720 1475 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1721 if (index >= 0) { 1476 hdmi_set_reg(core->v_sync_gen1, 3, val);
1722 struct drm_mode_object base; 1477
1723 struct list_head head; 1478 val = m->vtotal / 2;
1724 1479 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1725 DRM_INFO("desired mode doesn't exist so\n"); 1480 hdmi_set_reg(core->v_blank, 3, val);
1726 DRM_INFO("use the most suitable mode among modes.\n"); 1481
1727 1482 val = (m->vtotal +
1728 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n", 1483 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1729 m->hdisplay, m->vdisplay, m->vrefresh); 1484 val |= m->vtotal << 11;
1730 1485 hdmi_set_reg(core->v_blank_f, 3, val);
1731 /* preserve display mode header while copying. */ 1486
1732 head = adjusted_mode->head; 1487 val = ((m->vtotal / 2) + 7);
1733 base = adjusted_mode->base; 1488 val |= ((m->vtotal / 2) + 2) << 12;
1734 memcpy(adjusted_mode, m, sizeof(*m)); 1489 hdmi_set_reg(core->v_sync_gen2, 3, val);
1735 adjusted_mode->head = head; 1490
1736 adjusted_mode->base = base; 1491 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1737 break; 1492 val |= ((m->htotal / 2) +
1738 } 1493 (m->hsync_start - m->hdisplay)) << 12;
1494 hdmi_set_reg(core->v_sync_gen3, 3, val);
1495
1496 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1497 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1498
1499 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1500 } else {
1501 /* Progressive Mode */
1502
1503 val = m->vtotal;
1504 val |= (m->vtotal - m->vdisplay) << 11;
1505 hdmi_set_reg(core->v_blank, 3, val);
1506
1507 hdmi_set_reg(core->v_blank_f, 3, 0);
1508
1509 val = (m->vsync_end - m->vdisplay);
1510 val |= ((m->vsync_start - m->vdisplay) << 12);
1511 hdmi_set_reg(core->v_sync_gen1, 3, val);
1512
1513 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1514 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1515 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1516 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1517 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1739 } 1518 }
1740}
1741 1519
1742static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value) 1520 /* Timing generator registers */
1743{ 1521 hdmi_set_reg(tg->cmd, 1, 0x0);
1744 int i; 1522 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1745 BUG_ON(num_bytes > 4); 1523 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1746 for (i = 0; i < num_bytes; i++) 1524 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1747 reg_pair[i] = (value >> (8 * i)) & 0xff; 1525 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1526 hdmi_set_reg(tg->vsync, 2, 0x1);
1527 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1528 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1529 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1530 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1531 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1532 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1533 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1748} 1534}
1749 1535
1750static void hdmi_v14_mode_set(struct hdmi_context *hdata, 1536static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1751 struct drm_display_mode *m) 1537 struct drm_display_mode *m)
1752{ 1538{
1753 struct hdmi_core_regs *core = &hdata->mode_conf.core; 1539 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1754 struct hdmi_tg_regs *tg = &hdata->mode_conf.tg; 1540 struct hdmi_v14_core_regs *core =
1755 1541 &hdata->mode_conf.conf.v14_conf.core;
1756 hdata->mode_conf.cea_video_id = drm_match_cea_mode(m);
1757 1542
1543 hdata->mode_conf.cea_video_id =
1544 drm_match_cea_mode((struct drm_display_mode *)m);
1758 hdata->mode_conf.pixel_clock = m->clock * 1000; 1545 hdata->mode_conf.pixel_clock = m->clock * 1000;
1546
1759 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay); 1547 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1760 hdmi_set_reg(core->v_line, 2, m->vtotal); 1548 hdmi_set_reg(core->v_line, 2, m->vtotal);
1761 hdmi_set_reg(core->h_line, 2, m->htotal); 1549 hdmi_set_reg(core->h_line, 2, m->htotal);
@@ -1852,25 +1640,22 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1852 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ 1640 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1853 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ 1641 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1854 hdmi_set_reg(tg->tg_3d, 1, 0x0); 1642 hdmi_set_reg(tg->tg_3d, 1, 0x0);
1855
1856} 1643}
1857 1644
1858static void hdmi_mode_set(void *ctx, void *mode) 1645static void hdmi_mode_set(void *ctx, void *mode)
1859{ 1646{
1860 struct hdmi_context *hdata = ctx; 1647 struct hdmi_context *hdata = ctx;
1861 int conf_idx; 1648 struct drm_display_mode *m = mode;
1862 1649
1863 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); 1650 DRM_DEBUG_KMS("[%s]: xres=%d, yres=%d, refresh=%d, intl=%s\n",
1651 __func__, m->hdisplay, m->vdisplay,
1652 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1653 "INTERLACED" : "PROGERESSIVE");
1864 1654
1865 if (hdata->type == HDMI_TYPE13) { 1655 if (hdata->type == HDMI_TYPE13)
1866 conf_idx = hdmi_v13_conf_index(mode); 1656 hdmi_v13_mode_set(hdata, mode);
1867 if (conf_idx >= 0) 1657 else
1868 hdata->cur_conf = conf_idx;
1869 else
1870 DRM_DEBUG_KMS("not supported mode\n");
1871 } else {
1872 hdmi_v14_mode_set(hdata, mode); 1658 hdmi_v14_mode_set(hdata, mode);
1873 }
1874} 1659}
1875 1660
1876static void hdmi_get_max_resol(void *ctx, unsigned int *width, 1661static void hdmi_get_max_resol(void *ctx, unsigned int *width,
@@ -1983,7 +1768,6 @@ static struct exynos_hdmi_ops hdmi_ops = {
1983 .check_timing = hdmi_check_timing, 1768 .check_timing = hdmi_check_timing,
1984 1769
1985 /* manager */ 1770 /* manager */
1986 .mode_fixup = hdmi_mode_fixup,
1987 .mode_set = hdmi_mode_set, 1771 .mode_set = hdmi_mode_set,
1988 .get_max_resol = hdmi_get_max_resol, 1772 .get_max_resol = hdmi_get_max_resol,
1989 .commit = hdmi_commit, 1773 .commit = hdmi_commit,
@@ -2023,27 +1807,27 @@ static int hdmi_resources_init(struct hdmi_context *hdata)
2023 1807
2024 /* get clocks, power */ 1808 /* get clocks, power */
2025 res->hdmi = devm_clk_get(dev, "hdmi"); 1809 res->hdmi = devm_clk_get(dev, "hdmi");
2026 if (IS_ERR_OR_NULL(res->hdmi)) { 1810 if (IS_ERR(res->hdmi)) {
2027 DRM_ERROR("failed to get clock 'hdmi'\n"); 1811 DRM_ERROR("failed to get clock 'hdmi'\n");
2028 goto fail; 1812 goto fail;
2029 } 1813 }
2030 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); 1814 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
2031 if (IS_ERR_OR_NULL(res->sclk_hdmi)) { 1815 if (IS_ERR(res->sclk_hdmi)) {
2032 DRM_ERROR("failed to get clock 'sclk_hdmi'\n"); 1816 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2033 goto fail; 1817 goto fail;
2034 } 1818 }
2035 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel"); 1819 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
2036 if (IS_ERR_OR_NULL(res->sclk_pixel)) { 1820 if (IS_ERR(res->sclk_pixel)) {
2037 DRM_ERROR("failed to get clock 'sclk_pixel'\n"); 1821 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2038 goto fail; 1822 goto fail;
2039 } 1823 }
2040 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy"); 1824 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
2041 if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) { 1825 if (IS_ERR(res->sclk_hdmiphy)) {
2042 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n"); 1826 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2043 goto fail; 1827 goto fail;
2044 } 1828 }
2045 res->hdmiphy = devm_clk_get(dev, "hdmiphy"); 1829 res->hdmiphy = devm_clk_get(dev, "hdmiphy");
2046 if (IS_ERR_OR_NULL(res->hdmiphy)) { 1830 if (IS_ERR(res->hdmiphy)) {
2047 DRM_ERROR("failed to get clock 'hdmiphy'\n"); 1831 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2048 goto fail; 1832 goto fail;
2049 } 1833 }
@@ -2221,11 +2005,6 @@ static int hdmi_probe(struct platform_device *pdev)
2221 } 2005 }
2222 2006
2223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2224 if (!res) {
2225 DRM_ERROR("failed to find registers\n");
2226 return -ENOENT;
2227 }
2228
2229 hdata->regs = devm_ioremap_resource(&pdev->dev, res); 2008 hdata->regs = devm_ioremap_resource(&pdev->dev, res);
2230 if (IS_ERR(hdata->regs)) 2009 if (IS_ERR(hdata->regs))
2231 return PTR_ERR(hdata->regs); 2010 return PTR_ERR(hdata->regs);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 07:41:03 -0500