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path: root/drivers/gpu/drm/exynos/exynos_drm_plane.c
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Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_plane.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_plane.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index bdcf770aa22e..c277a3a445f5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -22,6 +22,10 @@ struct exynos_plane {
22 bool enabled; 22 bool enabled;
23}; 23};
24 24
25static const uint32_t formats[] = {
26 DRM_FORMAT_XRGB8888,
27};
28
25static int 29static int
26exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 30exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
27 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 31 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
@@ -115,9 +119,9 @@ int exynos_plane_init(struct drm_device *dev, unsigned int nr)
115 119
116 exynos_plane->overlay.zpos = DEFAULT_ZPOS; 120 exynos_plane->overlay.zpos = DEFAULT_ZPOS;
117 121
118 /* TODO: format */
119 return drm_plane_init(dev, &exynos_plane->base, possible_crtcs, 122 return drm_plane_init(dev, &exynos_plane->base, possible_crtcs,
120 &exynos_plane_funcs, NULL, 0, false); 123 &exynos_plane_funcs, formats, ARRAY_SIZE(formats),
124 false);
121} 125}
122 126
123int exynos_plane_set_zpos_ioctl(struct drm_device *dev, void *data, 127int exynos_plane_set_zpos_ioctl(struct drm_device *dev, void *data,