diff options
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_fimc.c')
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_fimc.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index d40b7fb3349e..409775f1efa1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c | |||
@@ -290,25 +290,18 @@ static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) | |||
290 | fimc_write(cfg, EXYNOS_CIGCTRL); | 290 | fimc_write(cfg, EXYNOS_CIGCTRL); |
291 | } | 291 | } |
292 | 292 | ||
293 | static void fimc_handle_irq(struct fimc_context *ctx, bool enable, | 293 | static void fimc_mask_irq(struct fimc_context *ctx, bool enable) |
294 | bool overflow, bool level) | ||
295 | { | 294 | { |
296 | u32 cfg; | 295 | u32 cfg; |
297 | 296 | ||
298 | DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", | 297 | DRM_DEBUG_KMS("enable[%d]\n", enable); |
299 | enable, overflow, level); | ||
300 | 298 | ||
301 | cfg = fimc_read(EXYNOS_CIGCTRL); | 299 | cfg = fimc_read(EXYNOS_CIGCTRL); |
302 | if (enable) { | 300 | if (enable) { |
303 | cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL); | 301 | cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN; |
304 | cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE; | 302 | cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL; |
305 | if (overflow) | ||
306 | cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN; | ||
307 | if (level) | ||
308 | cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL; | ||
309 | } else | 303 | } else |
310 | cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE); | 304 | cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE; |
311 | |||
312 | fimc_write(cfg, EXYNOS_CIGCTRL); | 305 | fimc_write(cfg, EXYNOS_CIGCTRL); |
313 | } | 306 | } |
314 | 307 | ||
@@ -1180,12 +1173,12 @@ static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, | |||
1180 | /* interrupt enable */ | 1173 | /* interrupt enable */ |
1181 | if (buf_type == IPP_BUF_ENQUEUE && | 1174 | if (buf_type == IPP_BUF_ENQUEUE && |
1182 | fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START) | 1175 | fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START) |
1183 | fimc_handle_irq(ctx, true, false, true); | 1176 | fimc_mask_irq(ctx, true); |
1184 | 1177 | ||
1185 | /* interrupt disable */ | 1178 | /* interrupt disable */ |
1186 | if (buf_type == IPP_BUF_DEQUEUE && | 1179 | if (buf_type == IPP_BUF_DEQUEUE && |
1187 | fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP) | 1180 | fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP) |
1188 | fimc_handle_irq(ctx, false, false, true); | 1181 | fimc_mask_irq(ctx, false); |
1189 | 1182 | ||
1190 | err_unlock: | 1183 | err_unlock: |
1191 | mutex_unlock(&ctx->lock); | 1184 | mutex_unlock(&ctx->lock); |
@@ -1520,7 +1513,7 @@ static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) | |||
1520 | 1513 | ||
1521 | property = &c_node->property; | 1514 | property = &c_node->property; |
1522 | 1515 | ||
1523 | fimc_handle_irq(ctx, true, false, true); | 1516 | fimc_mask_irq(ctx, true); |
1524 | 1517 | ||
1525 | for_each_ipp_ops(i) { | 1518 | for_each_ipp_ops(i) { |
1526 | config = &property->config[i]; | 1519 | config = &property->config[i]; |
@@ -1639,7 +1632,7 @@ static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) | |||
1639 | break; | 1632 | break; |
1640 | } | 1633 | } |
1641 | 1634 | ||
1642 | fimc_handle_irq(ctx, false, false, true); | 1635 | fimc_mask_irq(ctx, false); |
1643 | 1636 | ||
1644 | /* reset sequence */ | 1637 | /* reset sequence */ |
1645 | fimc_write(0x0, EXYNOS_CIFCNTSEQ); | 1638 | fimc_write(0x0, EXYNOS_CIFCNTSEQ); |