aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpio
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/Kconfig724
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/devres.c107
-rw-r--r--drivers/gpio/gpio-adp5588.c8
-rw-r--r--drivers/gpio/gpio-altera.c374
-rw-r--r--drivers/gpio/gpio-arizona.c3
-rw-r--r--drivers/gpio/gpio-crystalcove.c7
-rw-r--r--drivers/gpio/gpio-da9052.c2
-rw-r--r--drivers/gpio/gpio-da9055.c2
-rw-r--r--drivers/gpio/gpio-f7188x.c47
-rw-r--r--drivers/gpio/gpio-ich.c6
-rw-r--r--drivers/gpio/gpio-kempld.c2
-rw-r--r--drivers/gpio/gpio-loongson.c115
-rw-r--r--drivers/gpio/gpio-max7300.c4
-rw-r--r--drivers/gpio/gpio-max732x.c134
-rw-r--r--drivers/gpio/gpio-mb86s7x.c5
-rw-r--r--drivers/gpio/gpio-mc33880.c2
-rw-r--r--drivers/gpio/gpio-mcp23s08.c9
-rw-r--r--drivers/gpio/gpio-mvebu.c24
-rw-r--r--drivers/gpio/gpio-omap.c131
-rw-r--r--drivers/gpio/gpio-pcf857x.c134
-rw-r--r--drivers/gpio/gpio-pxa.c3
-rw-r--r--drivers/gpio/gpio-rcar.c63
-rw-r--r--drivers/gpio/gpio-tb10x.c2
-rw-r--r--drivers/gpio/gpio-vf610.c16
-rw-r--r--drivers/gpio/gpio-xgene-sb.c2
-rw-r--r--drivers/gpio/gpiolib-acpi.c86
-rw-r--r--drivers/gpio/gpiolib-of.c111
-rw-r--r--drivers/gpio/gpiolib.c299
-rw-r--r--drivers/gpio/gpiolib.h13
30 files changed, 1740 insertions, 697 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index dc1aaa83a347..38d875d0e4c8 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -90,27 +90,11 @@ config GPIO_GENERIC
90 90
91# put drivers in the right section, in alphabetical order 91# put drivers in the right section, in alphabetical order
92 92
93config GPIO_DA9052 93# This symbol is selected by both I2C and SPI expanders
94 tristate "Dialog DA9052 GPIO"
95 depends on PMIC_DA9052
96 help
97 Say yes here to enable the GPIO driver for the DA9052 chip.
98
99config GPIO_DA9055
100 tristate "Dialog Semiconductor DA9055 GPIO"
101 depends on MFD_DA9055
102 help
103 Say yes here to enable the GPIO driver for the DA9055 chip.
104
105 The Dialog DA9055 PMIC chip has 3 GPIO pins that can be
106 be controller by this driver.
107
108 If driver is built as a module it will be called gpio-da9055.
109
110config GPIO_MAX730X 94config GPIO_MAX730X
111 tristate 95 tristate
112 96
113comment "Memory mapped GPIO drivers:" 97menu "Memory mapped GPIO drivers"
114 98
115config GPIO_74XX_MMIO 99config GPIO_74XX_MMIO
116 tristate "GPIO driver for 74xx-ICs with MMIO access" 100 tristate "GPIO driver for 74xx-ICs with MMIO access"
@@ -126,6 +110,22 @@ config GPIO_74XX_MMIO
126 8 bits: 74244 (Input), 74273 (Output) 110 8 bits: 74244 (Input), 74273 (Output)
127 16 bits: 741624 (Input), 7416374 (Output) 111 16 bits: 741624 (Input), 7416374 (Output)
128 112
113config GPIO_ALTERA
114 tristate "Altera GPIO"
115 depends on OF_GPIO
116 select GPIO_GENERIC
117 select GPIOLIB_IRQCHIP
118 help
119 Say Y or M here to build support for the Altera PIO device.
120
121 If driver is built as a module it will be called gpio-altera.
122
123config GPIO_BCM_KONA
124 bool "Broadcom Kona GPIO"
125 depends on OF_GPIO && (ARCH_BCM_MOBILE || COMPILE_TEST)
126 help
127 Turn on GPIO support for Broadcom "Kona" chips.
128
129config GPIO_CLPS711X 129config GPIO_CLPS711X
130 tristate "CLPS711X GPIO support" 130 tristate "CLPS711X GPIO support"
131 depends on ARCH_CLPS711X || COMPILE_TEST 131 depends on ARCH_CLPS711X || COMPILE_TEST
@@ -140,28 +140,14 @@ config GPIO_DAVINCI
140 help 140 help
141 Say yes here to enable GPIO support for TI Davinci/Keystone SoCs. 141 Say yes here to enable GPIO support for TI Davinci/Keystone SoCs.
142 142
143config GPIO_GENERIC_PLATFORM
144 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
145 select GPIO_GENERIC
146 help
147 Say yes here to support basic platform_device memory-mapped GPIO controllers.
148
149config GPIO_DWAPB 143config GPIO_DWAPB
150 tristate "Synopsys DesignWare APB GPIO driver" 144 tristate "Synopsys DesignWare APB GPIO driver"
151 depends on ARM
152 depends on OF_GPIO
153 select GPIO_GENERIC 145 select GPIO_GENERIC
154 select GENERIC_IRQ_CHIP 146 select GENERIC_IRQ_CHIP
155 help 147 help
156 Say Y or M here to build support for the Synopsys DesignWare APB 148 Say Y or M here to build support for the Synopsys DesignWare APB
157 GPIO block. 149 GPIO block.
158 150
159config GPIO_IT8761E
160 tristate "IT8761E GPIO support"
161 depends on X86 # unconditional access to IO space.
162 help
163 Say yes here to support GPIO functionality of IT8761E super I/O chip.
164
165config GPIO_EM 151config GPIO_EM
166 tristate "Emma Mobile GPIO" 152 tristate "Emma Mobile GPIO"
167 depends on ARM && OF_GPIO 153 depends on ARM && OF_GPIO
@@ -173,36 +159,99 @@ config GPIO_EP93XX
173 depends on ARCH_EP93XX 159 depends on ARCH_EP93XX
174 select GPIO_GENERIC 160 select GPIO_GENERIC
175 161
176config GPIO_ZEVIO
177 bool "LSI ZEVIO SoC memory mapped GPIOs"
178 depends on ARM && OF_GPIO
179 help
180 Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
181
182config GPIO_MM_LANTIQ
183 bool "Lantiq Memory mapped GPIOs"
184 depends on LANTIQ && SOC_XWAY
185 help
186 This enables support for memory mapped GPIOs on the External Bus Unit
187 (EBU) found on Lantiq SoCs. The gpios are output only as they are
188 created by attaching a 16bit latch to the bus.
189
190config GPIO_F7188X 162config GPIO_F7188X
191 tristate "F71882FG and F71889F GPIO support" 163 tristate "F71869, F71869A, F71882FG and F71889F GPIO support"
192 depends on X86 164 depends on X86
193 help 165 help
194 This option enables support for GPIOs found on Fintek Super-I/O 166 This option enables support for GPIOs found on Fintek Super-I/O
195 chips F71882FG and F71889F. 167 chips F71869, F71869A, F71882FG and F71889F.
196 168
197 To compile this driver as a module, choose M here: the module will 169 To compile this driver as a module, choose M here: the module will
198 be called f7188x-gpio. 170 be called f7188x-gpio.
199 171
172config GPIO_GE_FPGA
173 bool "GE FPGA based GPIO"
174 depends on GE_FPGA
175 select GPIO_GENERIC
176 help
177 Support for common GPIO functionality provided on some GE Single Board
178 Computers.
179
180 This driver provides basic support (configure as input or output, read
181 and write pin state) for GPIO implemented in a number of GE single
182 board computers.
183
184config GPIO_GENERIC_PLATFORM
185 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
186 select GPIO_GENERIC
187 help
188 Say yes here to support basic platform_device memory-mapped GPIO controllers.
189
190config GPIO_GRGPIO
191 tristate "Aeroflex Gaisler GRGPIO support"
192 depends on OF
193 select GPIO_GENERIC
194 select IRQ_DOMAIN
195 help
196 Select this to support Aeroflex Gaisler GRGPIO cores from the GRLIB
197 VHDL IP core library.
198
199config GPIO_ICH
200 tristate "Intel ICH GPIO"
201 depends on PCI && X86
202 select MFD_CORE
203 select LPC_ICH
204 help
205 Say yes here to support the GPIO functionality of a number of Intel
206 ICH-based chipsets. Currently supported devices: ICH6, ICH7, ICH8
207 ICH9, ICH10, Series 5/3400 (eg Ibex Peak), Series 6/C200 (eg
208 Cougar Point), NM10 (Tiger Point), and 3100 (Whitmore Lake).
209
210 If unsure, say N.
211
212config GPIO_IOP
213 tristate "Intel IOP GPIO"
214 depends on ARM && (ARCH_IOP32X || ARCH_IOP33X)
215 help
216 Say yes here to support the GPIO functionality of a number of Intel
217 IOP32X or IOP33X.
218
219 If unsure, say N.
220
221config GPIO_IT8761E
222 tristate "IT8761E GPIO support"
223 depends on X86 # unconditional access to IO space.
224 help
225 Say yes here to support GPIO functionality of IT8761E super I/O chip.
226
227config GPIO_LOONGSON
228 bool "Loongson-2/3 GPIO support"
229 depends on CPU_LOONGSON2 || CPU_LOONGSON3
230 help
231 driver for GPIO functionality on Loongson-2F/3A/3B processors.
232
233config GPIO_LYNXPOINT
234 tristate "Intel Lynxpoint GPIO support"
235 depends on ACPI && X86
236 select GPIOLIB_IRQCHIP
237 help
238 driver for GPIO functionality on Intel Lynxpoint PCH chipset
239 Requires ACPI device enumeration code to set up a platform device.
240
200config GPIO_MB86S7X 241config GPIO_MB86S7X
201 bool "GPIO support for Fujitsu MB86S7x Platforms" 242 bool "GPIO support for Fujitsu MB86S7x Platforms"
202 depends on ARCH_MB86S7X 243 depends on ARCH_MB86S7X
203 help 244 help
204 Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs. 245 Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs.
205 246
247config GPIO_MM_LANTIQ
248 bool "Lantiq Memory mapped GPIOs"
249 depends on LANTIQ && SOC_XWAY
250 help
251 This enables support for memory mapped GPIOs on the External Bus Unit
252 (EBU) found on Lantiq SoCs. The gpios are output only as they are
253 created by attaching a 16bit latch to the bus.
254
206config GPIO_MOXART 255config GPIO_MOXART
207 bool "MOXART GPIO support" 256 bool "MOXART GPIO support"
208 depends on ARCH_MOXART 257 depends on ARCH_MOXART
@@ -303,6 +352,33 @@ config GPIO_SAMSUNG
303 Legacy GPIO support. Use only for platforms without support for 352 Legacy GPIO support. Use only for platforms without support for
304 pinctrl. 353 pinctrl.
305 354
355config GPIO_SCH
356 tristate "Intel SCH/TunnelCreek/Centerton/Quark X1000 GPIO"
357 depends on PCI && X86
358 select MFD_CORE
359 select LPC_SCH
360 help
361 Say yes here to support GPIO interface on Intel Poulsbo SCH,
362 Intel Tunnel Creek processor, Intel Centerton processor or
363 Intel Quark X1000 SoC.
364
365 The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
366 powered by the core power rail and are turned off during sleep
367 modes (S3 and higher). The remaining four GPIOs are powered by
368 the Intel SCH suspend power supply. These GPIOs remain
369 active during S3. The suspend powered GPIOs can be used to wake the
370 system from the Suspend-to-RAM state.
371
372 The Intel Tunnel Creek processor has 5 GPIOs powered by the
373 core power rail and 9 from suspend power supply.
374
375 The Intel Centerton processor has a total of 30 GPIO pins.
376 Twenty-one are powered by the core power rail and 9 from the
377 suspend power supply.
378
379 The Intel Quark X1000 SoC has 2 GPIOs powered by the core
380 power well and 6 from the suspend power well.
381
306config GPIO_SCH311X 382config GPIO_SCH311X
307 tristate "SMSC SCH311x SuperI/O GPIO" 383 tristate "SMSC SCH311x SuperI/O GPIO"
308 help 384 help
@@ -327,12 +403,27 @@ config GPIO_STA2X11
327 Say yes here to support the STA2x11/ConneXt GPIO device. 403 Say yes here to support the STA2x11/ConneXt GPIO device.
328 The GPIO module has 128 GPIO pins with alternate functions. 404 The GPIO module has 128 GPIO pins with alternate functions.
329 405
406config GPIO_STP_XWAY
407 bool "XWAY STP GPIOs"
408 depends on SOC_XWAY
409 help
410 This enables support for the Serial To Parallel (STP) unit found on
411 XWAY SoC. The STP allows the SoC to drive a shift registers cascade,
412 that can be up to 24 bit. This peripheral is aimed at driving leds.
413 Some of the gpios/leds can be auto updated by the soc with dsl and
414 phy status.
415
330config GPIO_SYSCON 416config GPIO_SYSCON
331 tristate "GPIO based on SYSCON" 417 tristate "GPIO based on SYSCON"
332 depends on MFD_SYSCON && OF 418 depends on MFD_SYSCON && OF
333 help 419 help
334 Say yes here to support GPIO functionality though SYSCON driver. 420 Say yes here to support GPIO functionality though SYSCON driver.
335 421
422config GPIO_TB10X
423 bool
424 select GENERIC_IRQ_CHIP
425 select OF_GPIO
426
336config GPIO_TS5500 427config GPIO_TS5500
337 tristate "TS-5500 DIO blocks and compatibles" 428 tristate "TS-5500 DIO blocks and compatibles"
338 depends on TS5500 || COMPILE_TEST 429 depends on TS5500 || COMPILE_TEST
@@ -364,6 +455,24 @@ config GPIO_VF610
364 help 455 help
365 Say yes here to support Vybrid vf610 GPIOs. 456 Say yes here to support Vybrid vf610 GPIOs.
366 457
458config GPIO_VR41XX
459 tristate "NEC VR4100 series General-purpose I/O Uint support"
460 depends on CPU_VR41XX
461 help
462 Say yes here to support the NEC VR4100 series General-purpose I/O Uint
463
464config GPIO_VX855
465 tristate "VIA VX855/VX875 GPIO"
466 depends on PCI
467 select MFD_CORE
468 select MFD_VX855
469 help
470 Support access to the VX855/VX875 GPIO lines through the gpio library.
471
472 This driver provides common support for accessing the device,
473 additional drivers must be enabled in order to use the
474 functionality of the device.
475
367config GPIO_XGENE 476config GPIO_XGENE
368 bool "APM X-Gene GPIO controller support" 477 bool "APM X-Gene GPIO controller support"
369 depends on ARM64 && OF_GPIO 478 depends on ARM64 && OF_GPIO
@@ -387,13 +496,6 @@ config GPIO_XILINX
387 help 496 help
388 Say yes here to support the Xilinx FPGA GPIO device 497 Say yes here to support the Xilinx FPGA GPIO device
389 498
390config GPIO_ZYNQ
391 tristate "Xilinx Zynq GPIO support"
392 depends on ARCH_ZYNQ
393 select GPIOLIB_IRQCHIP
394 help
395 Say yes here to support Xilinx Zynq GPIO controller.
396
397config GPIO_XTENSA 499config GPIO_XTENSA
398 bool "Xtensa GPIO32 support" 500 bool "Xtensa GPIO32 support"
399 depends on XTENSA 501 depends on XTENSA
@@ -403,135 +505,49 @@ config GPIO_XTENSA
403 Say yes here to support the Xtensa internal GPIO32 IMPWIRE (input) 505 Say yes here to support the Xtensa internal GPIO32 IMPWIRE (input)
404 and EXPSTATE (output) ports 506 and EXPSTATE (output) ports
405 507
406config GPIO_VR41XX 508config GPIO_ZEVIO
407 tristate "NEC VR4100 series General-purpose I/O Uint support" 509 bool "LSI ZEVIO SoC memory mapped GPIOs"
408 depends on CPU_VR41XX 510 depends on ARM && OF_GPIO
409 help
410 Say yes here to support the NEC VR4100 series General-purpose I/O Uint
411
412config GPIO_SCH
413 tristate "Intel SCH/TunnelCreek/Centerton/Quark X1000 GPIO"
414 depends on PCI && X86
415 select MFD_CORE
416 select LPC_SCH
417 help
418 Say yes here to support GPIO interface on Intel Poulsbo SCH,
419 Intel Tunnel Creek processor, Intel Centerton processor or
420 Intel Quark X1000 SoC.
421
422 The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
423 powered by the core power rail and are turned off during sleep
424 modes (S3 and higher). The remaining four GPIOs are powered by
425 the Intel SCH suspend power supply. These GPIOs remain
426 active during S3. The suspend powered GPIOs can be used to wake the
427 system from the Suspend-to-RAM state.
428
429 The Intel Tunnel Creek processor has 5 GPIOs powered by the
430 core power rail and 9 from suspend power supply.
431
432 The Intel Centerton processor has a total of 30 GPIO pins.
433 Twenty-one are powered by the core power rail and 9 from the
434 suspend power supply.
435
436 The Intel Quark X1000 SoC has 2 GPIOs powered by the core
437 power well and 6 from the suspend power well.
438
439config GPIO_ICH
440 tristate "Intel ICH GPIO"
441 depends on PCI && X86
442 select MFD_CORE
443 select LPC_ICH
444 help
445 Say yes here to support the GPIO functionality of a number of Intel
446 ICH-based chipsets. Currently supported devices: ICH6, ICH7, ICH8
447 ICH9, ICH10, Series 5/3400 (eg Ibex Peak), Series 6/C200 (eg
448 Cougar Point), NM10 (Tiger Point), and 3100 (Whitmore Lake).
449
450 If unsure, say N.
451
452config GPIO_IOP
453 tristate "Intel IOP GPIO"
454 depends on ARM && (ARCH_IOP32X || ARCH_IOP33X)
455 help
456 Say yes here to support the GPIO functionality of a number of Intel
457 IOP32X or IOP33X.
458
459 If unsure, say N.
460
461config GPIO_VX855
462 tristate "VIA VX855/VX875 GPIO"
463 depends on PCI
464 select MFD_CORE
465 select MFD_VX855
466 help
467 Support access to the VX855/VX875 GPIO lines through the gpio library.
468
469 This driver provides common support for accessing the device,
470 additional drivers must be enabled in order to use the
471 functionality of the device.
472
473config GPIO_GE_FPGA
474 bool "GE FPGA based GPIO"
475 depends on GE_FPGA
476 select GPIO_GENERIC
477 help 511 help
478 Support for common GPIO functionality provided on some GE Single Board 512 Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
479 Computers.
480
481 This driver provides basic support (configure as input or output, read
482 and write pin state) for GPIO implemented in a number of GE single
483 board computers.
484 513
485config GPIO_LYNXPOINT 514config GPIO_ZYNQ
486 tristate "Intel Lynxpoint GPIO support" 515 tristate "Xilinx Zynq GPIO support"
487 depends on ACPI && X86 516 depends on ARCH_ZYNQ
488 select GPIOLIB_IRQCHIP 517 select GPIOLIB_IRQCHIP
489 help 518 help
490 driver for GPIO functionality on Intel Lynxpoint PCH chipset 519 Say yes here to support Xilinx Zynq GPIO controller.
491 Requires ACPI device enumeration code to set up a platform device.
492
493config GPIO_GRGPIO
494 tristate "Aeroflex Gaisler GRGPIO support"
495 depends on OF
496 select GPIO_GENERIC
497 select IRQ_DOMAIN
498 help
499 Select this to support Aeroflex Gaisler GRGPIO cores from the GRLIB
500 VHDL IP core library.
501 520
502config GPIO_TB10X 521endmenu
503 bool
504 select GENERIC_IRQ_CHIP
505 select OF_GPIO
506 522
507comment "I2C GPIO expanders:" 523menu "I2C GPIO expanders"
524 depends on I2C
508 525
509config GPIO_ARIZONA 526config GPIO_ADP5588
510 tristate "Wolfson Microelectronics Arizona class devices" 527 tristate "ADP5588 I2C GPIO expander"
511 depends on MFD_ARIZONA 528 depends on I2C
512 help 529 help
513 Support for GPIOs on Wolfson Arizona class devices. 530 This option enables support for 18 GPIOs found
531 on Analog Devices ADP5588 GPIO Expanders.
514 532
515config GPIO_CRYSTAL_COVE 533config GPIO_ADP5588_IRQ
516 tristate "GPIO support for Crystal Cove PMIC" 534 bool "Interrupt controller support for ADP5588"
517 depends on INTEL_SOC_PMIC 535 depends on GPIO_ADP5588=y
518 select GPIOLIB_IRQCHIP
519 help 536 help
520 Support for GPIO pins on Crystal Cove PMIC. 537 Say yes here to enable the adp5588 to be used as an interrupt
521 538 controller. It requires the driver to be built in the kernel.
522 Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC
523 inside.
524
525 This driver can also be built as a module. If so, the module will be
526 called gpio-crystalcove.
527 539
528config GPIO_LP3943 540config GPIO_ADNP
529 tristate "TI/National Semiconductor LP3943 GPIO expander" 541 tristate "Avionic Design N-bit GPIO expander"
530 depends on MFD_LP3943 542 depends on I2C && OF_GPIO
543 select GPIOLIB_IRQCHIP
531 help 544 help
532 GPIO driver for LP3943 MFD. 545 This option enables support for N GPIOs found on Avionic Design
533 LP3943 can be used as a GPIO expander which provides up to 16 GPIOs. 546 I2C GPIO expanders. The register space will be extended by powers
534 Open drain outputs are required for this usage. 547 of two, so the controller will need to accommodate for that. For
548 example: if a controller provides 48 pins, 6 registers will be
549 enough to represent all pins, but the driver will assume a
550 register layout for 64 pins (8 registers).
535 551
536config GPIO_MAX7300 552config GPIO_MAX7300
537 tristate "Maxim MAX7300 GPIO expander" 553 tristate "Maxim MAX7300 GPIO expander"
@@ -543,7 +559,6 @@ config GPIO_MAX7300
543config GPIO_MAX732X 559config GPIO_MAX732X
544 tristate "MAX7319, MAX7320-7327 I2C Port Expanders" 560 tristate "MAX7319, MAX7320-7327 I2C Port Expanders"
545 depends on I2C 561 depends on I2C
546 select IRQ_DOMAIN
547 help 562 help
548 Say yes here to support the MAX7319, MAX7320-7327 series of I2C 563 Say yes here to support the MAX7319, MAX7320-7327 series of I2C
549 Port Expanders. Each IO port on these chips has a fixed role of 564 Port Expanders. Each IO port on these chips has a fixed role of
@@ -563,6 +578,7 @@ config GPIO_MAX732X
563config GPIO_MAX732X_IRQ 578config GPIO_MAX732X_IRQ
564 bool "Interrupt controller support for MAX732x" 579 bool "Interrupt controller support for MAX732x"
565 depends on GPIO_MAX732X=y 580 depends on GPIO_MAX732X=y
581 select GPIOLIB_IRQCHIP
566 help 582 help
567 Say yes here to enable the max732x to be used as an interrupt 583 Say yes here to enable the max732x to be used as an interrupt
568 controller. It requires the driver to be built in the kernel. 584 controller. It requires the driver to be built in the kernel.
@@ -604,6 +620,7 @@ config GPIO_PCA953X_IRQ
604config GPIO_PCF857X 620config GPIO_PCF857X
605 tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders" 621 tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders"
606 depends on I2C 622 depends on I2C
623 select GPIOLIB_IRQCHIP
607 select IRQ_DOMAIN 624 select IRQ_DOMAIN
608 help 625 help
609 Say yes here to provide access to most "quasi-bidirectional" I2C 626 Say yes here to provide access to most "quasi-bidirectional" I2C
@@ -626,15 +643,6 @@ config GPIO_PCF857X
626 This driver provides an in-kernel interface to those GPIOs using 643 This driver provides an in-kernel interface to those GPIOs using
627 platform-neutral GPIO calls. 644 platform-neutral GPIO calls.
628 645
629config GPIO_RC5T583
630 bool "RICOH RC5T583 GPIO"
631 depends on MFD_RC5T583
632 help
633 Select this option to enable GPIO driver for the Ricoh RC5T583
634 chip family.
635 This driver provides the support for driving/reading the gpio pins
636 of RC5T583 device through standard gpio library.
637
638config GPIO_SX150X 646config GPIO_SX150X
639 bool "Semtech SX150x I2C GPIO expander" 647 bool "Semtech SX150x I2C GPIO expander"
640 depends on I2C=y 648 depends on I2C=y
@@ -647,6 +655,124 @@ config GPIO_SX150X
647 8 bits: sx1508q 655 8 bits: sx1508q
648 16 bits: sx1509q 656 16 bits: sx1509q
649 657
658endmenu
659
660menu "MFD GPIO expanders"
661
662config GPIO_ADP5520
663 tristate "GPIO Support for ADP5520 PMIC"
664 depends on PMIC_ADP5520
665 help
666 This option enables support for on-chip GPIO found
667 on Analog Devices ADP5520 PMICs.
668
669config GPIO_ARIZONA
670 tristate "Wolfson Microelectronics Arizona class devices"
671 depends on MFD_ARIZONA
672 help
673 Support for GPIOs on Wolfson Arizona class devices.
674
675config GPIO_CRYSTAL_COVE
676 tristate "GPIO support for Crystal Cove PMIC"
677 depends on INTEL_SOC_PMIC
678 select GPIOLIB_IRQCHIP
679 help
680 Support for GPIO pins on Crystal Cove PMIC.
681
682 Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC
683 inside.
684
685 This driver can also be built as a module. If so, the module will be
686 called gpio-crystalcove.
687
688config GPIO_CS5535
689 tristate "AMD CS5535/CS5536 GPIO support"
690 depends on MFD_CS5535
691 help
692 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
693 can be used for quite a number of things. The CS5535/6 is found on
694 AMD Geode and Lemote Yeeloong devices.
695
696 If unsure, say N.
697
698config GPIO_DA9052
699 tristate "Dialog DA9052 GPIO"
700 depends on PMIC_DA9052
701 help
702 Say yes here to enable the GPIO driver for the DA9052 chip.
703
704config GPIO_DA9055
705 tristate "Dialog Semiconductor DA9055 GPIO"
706 depends on MFD_DA9055
707 help
708 Say yes here to enable the GPIO driver for the DA9055 chip.
709
710 The Dialog DA9055 PMIC chip has 3 GPIO pins that can be
711 be controller by this driver.
712
713 If driver is built as a module it will be called gpio-da9055.
714
715config GPIO_DLN2
716 tristate "Diolan DLN2 GPIO support"
717 depends on MFD_DLN2
718 select GPIOLIB_IRQCHIP
719
720 help
721 Select this option to enable GPIO driver for the Diolan DLN2
722 board.
723
724 This driver can also be built as a module. If so, the module
725 will be called gpio-dln2.
726
727config GPIO_JANZ_TTL
728 tristate "Janz VMOD-TTL Digital IO Module"
729 depends on MFD_JANZ_CMODIO
730 help
731 This enables support for the Janz VMOD-TTL Digital IO module.
732 This driver provides support for driving the pins in output
733 mode only. Input mode is not supported.
734
735config GPIO_KEMPLD
736 tristate "Kontron ETX / COMexpress GPIO"
737 depends on MFD_KEMPLD
738 help
739 This enables support for the PLD GPIO interface on some Kontron ETX
740 and COMexpress (ETXexpress) modules.
741
742 This driver can also be built as a module. If so, the module will be
743 called gpio-kempld.
744
745config GPIO_LP3943
746 tristate "TI/National Semiconductor LP3943 GPIO expander"
747 depends on MFD_LP3943
748 help
749 GPIO driver for LP3943 MFD.
750 LP3943 can be used as a GPIO expander which provides up to 16 GPIOs.
751 Open drain outputs are required for this usage.
752
753config GPIO_MSIC
754 bool "Intel MSIC mixed signal gpio support"
755 depends on MFD_INTEL_MSIC
756 help
757 Enable support for GPIO on intel MSIC controllers found in
758 intel MID devices
759
760config GPIO_PALMAS
761 bool "TI PALMAS series PMICs GPIO"
762 depends on MFD_PALMAS
763 help
764 Select this option to enable GPIO driver for the TI PALMAS
765 series chip family.
766
767config GPIO_RC5T583
768 bool "RICOH RC5T583 GPIO"
769 depends on MFD_RC5T583
770 help
771 Select this option to enable GPIO driver for the Ricoh RC5T583
772 chip family.
773 This driver provides the support for driving/reading the gpio pins
774 of RC5T583 device through standard gpio library.
775
650config GPIO_STMPE 776config GPIO_STMPE
651 bool "STMPE GPIOs" 777 bool "STMPE GPIOs"
652 depends on MFD_STMPE 778 depends on MFD_STMPE
@@ -656,16 +782,6 @@ config GPIO_STMPE
656 This enables support for the GPIOs found on the STMPE I/O 782 This enables support for the GPIOs found on the STMPE I/O
657 Expanders. 783 Expanders.
658 784
659config GPIO_STP_XWAY
660 bool "XWAY STP GPIOs"
661 depends on SOC_XWAY
662 help
663 This enables support for the Serial To Parallel (STP) unit found on
664 XWAY SoC. The STP allows the SoC to drive a shift registers cascade,
665 that can be up to 24 bit. This peripheral is aimed at driving leds.
666 Some of the gpios/leds can be auto updated by the soc with dsl and
667 phy status.
668
669config GPIO_TC3589X 785config GPIO_TC3589X
670 bool "TC3589X GPIOs" 786 bool "TC3589X GPIOs"
671 depends on MFD_TC3589X 787 depends on MFD_TC3589X
@@ -675,6 +791,26 @@ config GPIO_TC3589X
675 This enables support for the GPIOs found on the TC3589X 791 This enables support for the GPIOs found on the TC3589X
676 I/O Expander. 792 I/O Expander.
677 793
794config GPIO_TIMBERDALE
795 bool "Support for timberdale GPIO IP"
796 depends on MFD_TIMBERDALE
797 ---help---
798 Add support for the GPIO IP in the timberdale FPGA.
799
800config GPIO_TPS6586X
801 bool "TPS6586X GPIO"
802 depends on MFD_TPS6586X
803 help
804 Select this option to enable GPIO driver for the TPS6586X
805 chip family.
806
807config GPIO_TPS65910
808 bool "TPS65910 GPIO"
809 depends on MFD_TPS65910
810 help
811 Select this option to enable GPIO driver for the TPS65910
812 chip family.
813
678config GPIO_TPS65912 814config GPIO_TPS65912
679 tristate "TI TPS65912 GPIO" 815 tristate "TI TPS65912 GPIO"
680 depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI) 816 depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI)
@@ -695,6 +831,13 @@ config GPIO_TWL6040
695 Say yes here to access the GPO signals of twl6040 831 Say yes here to access the GPO signals of twl6040
696 audio chip from Texas Instruments. 832 audio chip from Texas Instruments.
697 833
834config GPIO_UCB1400
835 tristate "Philips UCB1400 GPIO"
836 depends on UCB1400_CORE
837 help
838 This enables support for the Philips UCB1400 GPIO pins.
839 The UCB1400 is an AC97 audio codec.
840
698config GPIO_WM831X 841config GPIO_WM831X
699 tristate "WM831x GPIOs" 842 tristate "WM831x GPIOs"
700 depends on MFD_WM831X 843 depends on MFD_WM831X
@@ -716,50 +859,22 @@ config GPIO_WM8994
716 Say yes here to access the GPIO signals of WM8994 audio hub 859 Say yes here to access the GPIO signals of WM8994 audio hub
717 CODECs from Wolfson Microelectronics. 860 CODECs from Wolfson Microelectronics.
718 861
719config GPIO_ADP5520 862endmenu
720 tristate "GPIO Support for ADP5520 PMIC"
721 depends on PMIC_ADP5520
722 help
723 This option enables support for on-chip GPIO found
724 on Analog Devices ADP5520 PMICs.
725 863
726config GPIO_ADP5588 864menu "PCI GPIO expanders"
727 tristate "ADP5588 I2C GPIO expander" 865 depends on PCI
728 depends on I2C
729 help
730 This option enables support for 18 GPIOs found
731 on Analog Devices ADP5588 GPIO Expanders.
732
733config GPIO_ADP5588_IRQ
734 bool "Interrupt controller support for ADP5588"
735 depends on GPIO_ADP5588=y
736 help
737 Say yes here to enable the adp5588 to be used as an interrupt
738 controller. It requires the driver to be built in the kernel.
739 866
740config GPIO_ADNP 867config GPIO_AMD8111
741 tristate "Avionic Design N-bit GPIO expander" 868 tristate "AMD 8111 GPIO driver"
742 depends on I2C && OF_GPIO 869 depends on PCI
743 select GPIOLIB_IRQCHIP
744 help 870 help
745 This option enables support for N GPIOs found on Avionic Design 871 The AMD 8111 south bridge contains 32 GPIO pins which can be used.
746 I2C GPIO expanders. The register space will be extended by powers
747 of two, so the controller will need to accommodate for that. For
748 example: if a controller provides 48 pins, 6 registers will be
749 enough to represent all pins, but the driver will assume a
750 register layout for 64 pins (8 registers).
751
752comment "PCI GPIO expanders:"
753 872
754config GPIO_CS5535 873 Note, that usually system firmware/ACPI handles GPIO pins on their
755 tristate "AMD CS5535/CS5536 GPIO support" 874 own and users might easily break their systems with uncarefull usage
756 depends on MFD_CS5535 875 of this driver!
757 help
758 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
759 can be used for quite a number of things. The CS5535/6 is found on
760 AMD Geode and Lemote Yeeloong devices.
761 876
762 If unsure, say N. 877 If unsure, say N
763 878
764config GPIO_BT8XX 879config GPIO_BT8XX
765 tristate "BT8XX GPIO abuser" 880 tristate "BT8XX GPIO abuser"
@@ -777,18 +892,6 @@ config GPIO_BT8XX
777 892
778 If unsure, say N. 893 If unsure, say N.
779 894
780config GPIO_AMD8111
781 tristate "AMD 8111 GPIO driver"
782 depends on PCI
783 help
784 The AMD 8111 south bridge contains 32 GPIO pins which can be used.
785
786 Note, that usually system firmware/ACPI handles GPIO pins on their
787 own and users might easily break their systems with uncarefull usage
788 of this driver!
789
790 If unsure, say N
791
792config GPIO_INTEL_MID 895config GPIO_INTEL_MID
793 bool "Intel Mid GPIO support" 896 bool "Intel Mid GPIO support"
794 depends on PCI && X86 897 depends on PCI && X86
@@ -796,6 +899,16 @@ config GPIO_INTEL_MID
796 help 899 help
797 Say Y here to support Intel Mid GPIO. 900 Say Y here to support Intel Mid GPIO.
798 901
902config GPIO_ML_IOH
903 tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"
904 depends on PCI
905 select GENERIC_IRQ_CHIP
906 help
907 ML7213 is companion chip for Intel Atom E6xx series.
908 This driver can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/Output
909 Hub) which is for IVI(In-Vehicle Infotainment) use.
910 This driver can access the IOH's GPIO device.
911
799config GPIO_PCH 912config GPIO_PCH
800 tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7223/ML7831) GPIO" 913 tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7223/ML7831) GPIO"
801 depends on PCI && (X86_32 || COMPILE_TEST) 914 depends on PCI && (X86_32 || COMPILE_TEST)
@@ -812,15 +925,14 @@ config GPIO_PCH
812 ML7223/ML7831 is companion chip for Intel Atom E6xx series. 925 ML7223/ML7831 is companion chip for Intel Atom E6xx series.
813 ML7223/ML7831 is completely compatible for Intel EG20T PCH. 926 ML7223/ML7831 is completely compatible for Intel EG20T PCH.
814 927
815config GPIO_ML_IOH 928config GPIO_RDC321X
816 tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" 929 tristate "RDC R-321x GPIO support"
817 depends on PCI 930 depends on PCI
818 select GENERIC_IRQ_CHIP 931 select MFD_CORE
932 select MFD_RDC321X
819 help 933 help
820 ML7213 is companion chip for Intel Atom E6xx series. 934 Support for the RDC R321x SoC GPIOs over southbridge
821 This driver can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/Output 935 PCI configuration space.
822 Hub) which is for IVI(In-Vehicle Infotainment) use.
823 This driver can access the IOH's GPIO device.
824 936
825config GPIO_SODAVILLE 937config GPIO_SODAVILLE
826 bool "Intel Sodaville GPIO support" 938 bool "Intel Sodaville GPIO support"
@@ -830,22 +942,18 @@ config GPIO_SODAVILLE
830 help 942 help
831 Say Y here to support Intel Sodaville GPIO. 943 Say Y here to support Intel Sodaville GPIO.
832 944
833config GPIO_TIMBERDALE 945endmenu
834 bool "Support for timberdale GPIO IP"
835 depends on MFD_TIMBERDALE
836 ---help---
837 Add support for the GPIO IP in the timberdale FPGA.
838 946
839config GPIO_RDC321X 947menu "SPI GPIO expanders"
840 tristate "RDC R-321x GPIO support" 948 depends on SPI_MASTER
841 depends on PCI
842 select MFD_CORE
843 select MFD_RDC321X
844 help
845 Support for the RDC R321x SoC GPIOs over southbridge
846 PCI configuration space.
847 949
848comment "SPI GPIO expanders:" 950config GPIO_74X164
951 tristate "74x164 serial-in/parallel-out 8-bits shift register"
952 depends on SPI_MASTER && OF
953 help
954 Driver for 74x164 compatible serial-in/parallel-out 8-outputs
955 shift registers. This driver can be used to provide access
956 to more gpio outputs.
849 957
850config GPIO_MAX7301 958config GPIO_MAX7301
851 tristate "Maxim MAX7301 GPIO expander" 959 tristate "Maxim MAX7301 GPIO expander"
@@ -870,80 +978,10 @@ config GPIO_MC33880
870 SPI driver for Freescale MC33880 high-side/low-side switch. 978 SPI driver for Freescale MC33880 high-side/low-side switch.
871 This provides GPIO interface supporting inputs and outputs. 979 This provides GPIO interface supporting inputs and outputs.
872 980
873config GPIO_74X164 981endmenu
874 tristate "74x164 serial-in/parallel-out 8-bits shift register"
875 depends on SPI_MASTER && OF
876 help
877 Driver for 74x164 compatible serial-in/parallel-out 8-outputs
878 shift registers. This driver can be used to provide access
879 to more gpio outputs.
880
881comment "AC97 GPIO expanders:"
882
883config GPIO_UCB1400
884 tristate "Philips UCB1400 GPIO"
885 depends on UCB1400_CORE
886 help
887 This enables support for the Philips UCB1400 GPIO pins.
888 The UCB1400 is an AC97 audio codec.
889
890comment "LPC GPIO expanders:"
891
892config GPIO_KEMPLD
893 tristate "Kontron ETX / COMexpress GPIO"
894 depends on MFD_KEMPLD
895 help
896 This enables support for the PLD GPIO interface on some Kontron ETX
897 and COMexpress (ETXexpress) modules.
898
899 This driver can also be built as a module. If so, the module will be
900 called gpio-kempld.
901
902comment "MODULbus GPIO expanders:"
903
904config GPIO_JANZ_TTL
905 tristate "Janz VMOD-TTL Digital IO Module"
906 depends on MFD_JANZ_CMODIO
907 help
908 This enables support for the Janz VMOD-TTL Digital IO module.
909 This driver provides support for driving the pins in output
910 mode only. Input mode is not supported.
911
912config GPIO_PALMAS
913 bool "TI PALMAS series PMICs GPIO"
914 depends on MFD_PALMAS
915 help
916 Select this option to enable GPIO driver for the TI PALMAS
917 series chip family.
918
919config GPIO_TPS6586X
920 bool "TPS6586X GPIO"
921 depends on MFD_TPS6586X
922 help
923 Select this option to enable GPIO driver for the TPS6586X
924 chip family.
925 982
926config GPIO_TPS65910 983menu "USB GPIO expanders"
927 bool "TPS65910 GPIO" 984 depends on USB
928 depends on MFD_TPS65910
929 help
930 Select this option to enable GPIO driver for the TPS65910
931 chip family.
932
933config GPIO_MSIC
934 bool "Intel MSIC mixed signal gpio support"
935 depends on MFD_INTEL_MSIC
936 help
937 Enable support for GPIO on intel MSIC controllers found in
938 intel MID devices
939
940config GPIO_BCM_KONA
941 bool "Broadcom Kona GPIO"
942 depends on OF_GPIO && (ARCH_BCM_MOBILE || COMPILE_TEST)
943 help
944 Turn on GPIO support for Broadcom "Kona" chips.
945
946comment "USB GPIO expanders:"
947 985
948config GPIO_VIPERBOARD 986config GPIO_VIPERBOARD
949 tristate "Viperboard GPIO a & b support" 987 tristate "Viperboard GPIO a & b support"
@@ -956,16 +994,6 @@ config GPIO_VIPERBOARD
956 River Tech's viperboard.h for detailed meaning 994 River Tech's viperboard.h for detailed meaning
957 of the module parameters. 995 of the module parameters.
958 996
959config GPIO_DLN2 997endmenu
960 tristate "Diolan DLN2 GPIO support"
961 depends on MFD_DLN2
962 select GPIOLIB_IRQCHIP
963
964 help
965 Select this option to enable GPIO driver for the Diolan DLN2
966 board.
967
968 This driver can also be built as a module. If so, the module
969 will be called gpio-dln2.
970 998
971endif 999endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index bdda6a94d2cd..07b816b9b630 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o
17obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o 17obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
18obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o 18obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
19obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o 19obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
20obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
20obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o 21obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
21obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o 22obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
22obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o 23obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
@@ -41,6 +42,7 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
41obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o 42obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
42obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o 43obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o
43obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o 44obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o
45obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o
44obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o 46obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
45obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o 47obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
46obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o 48obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
diff --git a/drivers/gpio/devres.c b/drivers/gpio/devres.c
index 13dbd3dfc33a..07ba82317ece 100644
--- a/drivers/gpio/devres.c
+++ b/drivers/gpio/devres.c
@@ -35,6 +35,20 @@ static int devm_gpiod_match(struct device *dev, void *res, void *data)
35 return *this == *gpio; 35 return *this == *gpio;
36} 36}
37 37
38static void devm_gpiod_release_array(struct device *dev, void *res)
39{
40 struct gpio_descs **descs = res;
41
42 gpiod_put_array(*descs);
43}
44
45static int devm_gpiod_match_array(struct device *dev, void *res, void *data)
46{
47 struct gpio_descs **this = res, **gpios = data;
48
49 return *this == *gpios;
50}
51
38/** 52/**
39 * devm_gpiod_get - Resource-managed gpiod_get() 53 * devm_gpiod_get - Resource-managed gpiod_get()
40 * @dev: GPIO consumer 54 * @dev: GPIO consumer
@@ -111,23 +125,39 @@ EXPORT_SYMBOL(__devm_gpiod_get_index);
111/** 125/**
112 * devm_get_gpiod_from_child - get a GPIO descriptor from a device's child node 126 * devm_get_gpiod_from_child - get a GPIO descriptor from a device's child node
113 * @dev: GPIO consumer 127 * @dev: GPIO consumer
128 * @con_id: function within the GPIO consumer
114 * @child: firmware node (child of @dev) 129 * @child: firmware node (child of @dev)
115 * 130 *
116 * GPIO descriptors returned from this function are automatically disposed on 131 * GPIO descriptors returned from this function are automatically disposed on
117 * driver detach. 132 * driver detach.
118 */ 133 */
119struct gpio_desc *devm_get_gpiod_from_child(struct device *dev, 134struct gpio_desc *devm_get_gpiod_from_child(struct device *dev,
135 const char *con_id,
120 struct fwnode_handle *child) 136 struct fwnode_handle *child)
121{ 137{
138 static const char * const suffixes[] = { "gpios", "gpio" };
139 char prop_name[32]; /* 32 is max size of property name */
122 struct gpio_desc **dr; 140 struct gpio_desc **dr;
123 struct gpio_desc *desc; 141 struct gpio_desc *desc;
142 unsigned int i;
124 143
125 dr = devres_alloc(devm_gpiod_release, sizeof(struct gpio_desc *), 144 dr = devres_alloc(devm_gpiod_release, sizeof(struct gpio_desc *),
126 GFP_KERNEL); 145 GFP_KERNEL);
127 if (!dr) 146 if (!dr)
128 return ERR_PTR(-ENOMEM); 147 return ERR_PTR(-ENOMEM);
129 148
130 desc = fwnode_get_named_gpiod(child, "gpios"); 149 for (i = 0; i < ARRAY_SIZE(suffixes); i++) {
150 if (con_id)
151 snprintf(prop_name, sizeof(prop_name), "%s-%s",
152 con_id, suffixes[i]);
153 else
154 snprintf(prop_name, sizeof(prop_name), "%s",
155 suffixes[i]);
156
157 desc = fwnode_get_named_gpiod(child, prop_name);
158 if (!IS_ERR(desc) || (PTR_ERR(desc) == -EPROBE_DEFER))
159 break;
160 }
131 if (IS_ERR(desc)) { 161 if (IS_ERR(desc)) {
132 devres_free(dr); 162 devres_free(dr);
133 return desc; 163 return desc;
@@ -170,6 +200,66 @@ struct gpio_desc *__must_check __devm_gpiod_get_index_optional(struct device *de
170EXPORT_SYMBOL(__devm_gpiod_get_index_optional); 200EXPORT_SYMBOL(__devm_gpiod_get_index_optional);
171 201
172/** 202/**
203 * devm_gpiod_get_array - Resource-managed gpiod_get_array()
204 * @dev: GPIO consumer
205 * @con_id: function within the GPIO consumer
206 * @flags: optional GPIO initialization flags
207 *
208 * Managed gpiod_get_array(). GPIO descriptors returned from this function are
209 * automatically disposed on driver detach. See gpiod_get_array() for detailed
210 * information about behavior and return values.
211 */
212struct gpio_descs *__must_check devm_gpiod_get_array(struct device *dev,
213 const char *con_id,
214 enum gpiod_flags flags)
215{
216 struct gpio_descs **dr;
217 struct gpio_descs *descs;
218
219 dr = devres_alloc(devm_gpiod_release_array,
220 sizeof(struct gpio_descs *), GFP_KERNEL);
221 if (!dr)
222 return ERR_PTR(-ENOMEM);
223
224 descs = gpiod_get_array(dev, con_id, flags);
225 if (IS_ERR(descs)) {
226 devres_free(dr);
227 return descs;
228 }
229
230 *dr = descs;
231 devres_add(dev, dr);
232
233 return descs;
234}
235EXPORT_SYMBOL(devm_gpiod_get_array);
236
237/**
238 * devm_gpiod_get_array_optional - Resource-managed gpiod_get_array_optional()
239 * @dev: GPIO consumer
240 * @con_id: function within the GPIO consumer
241 * @flags: optional GPIO initialization flags
242 *
243 * Managed gpiod_get_array_optional(). GPIO descriptors returned from this
244 * function are automatically disposed on driver detach.
245 * See gpiod_get_array_optional() for detailed information about behavior and
246 * return values.
247 */
248struct gpio_descs *__must_check
249devm_gpiod_get_array_optional(struct device *dev, const char *con_id,
250 enum gpiod_flags flags)
251{
252 struct gpio_descs *descs;
253
254 descs = devm_gpiod_get_array(dev, con_id, flags);
255 if (IS_ERR(descs) && (PTR_ERR(descs) == -ENOENT))
256 return NULL;
257
258 return descs;
259}
260EXPORT_SYMBOL(devm_gpiod_get_array_optional);
261
262/**
173 * devm_gpiod_put - Resource-managed gpiod_put() 263 * devm_gpiod_put - Resource-managed gpiod_put()
174 * @desc: GPIO descriptor to dispose of 264 * @desc: GPIO descriptor to dispose of
175 * 265 *
@@ -184,6 +274,21 @@ void devm_gpiod_put(struct device *dev, struct gpio_desc *desc)
184} 274}
185EXPORT_SYMBOL(devm_gpiod_put); 275EXPORT_SYMBOL(devm_gpiod_put);
186 276
277/**
278 * devm_gpiod_put_array - Resource-managed gpiod_put_array()
279 * @descs: GPIO descriptor array to dispose of
280 *
281 * Dispose of an array of GPIO descriptors obtained with devm_gpiod_get_array().
282 * Normally this function will not be called as the GPIOs will be disposed of
283 * by the resource management code.
284 */
285void devm_gpiod_put_array(struct device *dev, struct gpio_descs *descs)
286{
287 WARN_ON(devres_release(dev, devm_gpiod_release_array,
288 devm_gpiod_match_array, &descs));
289}
290EXPORT_SYMBOL(devm_gpiod_put_array);
291
187 292
188 293
189 294
diff --git a/drivers/gpio/gpio-adp5588.c b/drivers/gpio/gpio-adp5588.c
index 3beed6ea8c65..d3fe6a6776da 100644
--- a/drivers/gpio/gpio-adp5588.c
+++ b/drivers/gpio/gpio-adp5588.c
@@ -367,7 +367,7 @@ static int adp5588_gpio_probe(struct i2c_client *client,
367 struct gpio_chip *gc; 367 struct gpio_chip *gc;
368 int ret, i, revid; 368 int ret, i, revid;
369 369
370 if (pdata == NULL) { 370 if (!pdata) {
371 dev_err(&client->dev, "missing platform data\n"); 371 dev_err(&client->dev, "missing platform data\n");
372 return -ENODEV; 372 return -ENODEV;
373 } 373 }
@@ -378,8 +378,8 @@ static int adp5588_gpio_probe(struct i2c_client *client,
378 return -EIO; 378 return -EIO;
379 } 379 }
380 380
381 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 381 dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
382 if (dev == NULL) 382 if (!dev)
383 return -ENOMEM; 383 return -ENOMEM;
384 384
385 dev->client = client; 385 dev->client = client;
@@ -446,7 +446,6 @@ static int adp5588_gpio_probe(struct i2c_client *client,
446err_irq: 446err_irq:
447 adp5588_irq_teardown(dev); 447 adp5588_irq_teardown(dev);
448err: 448err:
449 kfree(dev);
450 return ret; 449 return ret;
451} 450}
452 451
@@ -472,7 +471,6 @@ static int adp5588_gpio_remove(struct i2c_client *client)
472 471
473 gpiochip_remove(&dev->gpio_chip); 472 gpiochip_remove(&dev->gpio_chip);
474 473
475 kfree(dev);
476 return 0; 474 return 0;
477} 475}
478 476
diff --git a/drivers/gpio/gpio-altera.c b/drivers/gpio/gpio-altera.c
new file mode 100644
index 000000000000..449fb46cb8a0
--- /dev/null
+++ b/drivers/gpio/gpio-altera.c
@@ -0,0 +1,374 @@
1/*
2 * Copyright (C) 2013 Altera Corporation
3 * Based on gpio-mpc8xxx.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/io.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22
23#define ALTERA_GPIO_MAX_NGPIO 32
24#define ALTERA_GPIO_DATA 0x0
25#define ALTERA_GPIO_DIR 0x4
26#define ALTERA_GPIO_IRQ_MASK 0x8
27#define ALTERA_GPIO_EDGE_CAP 0xc
28
29/**
30* struct altera_gpio_chip
31* @mmchip : memory mapped chip structure.
32* @gpio_lock : synchronization lock so that new irq/set/get requests
33 will be blocked until the current one completes.
34* @interrupt_trigger : specifies the hardware configured IRQ trigger type
35 (rising, falling, both, high)
36* @mapped_irq : kernel mapped irq number.
37*/
38struct altera_gpio_chip {
39 struct of_mm_gpio_chip mmchip;
40 spinlock_t gpio_lock;
41 int interrupt_trigger;
42 int mapped_irq;
43};
44
45static void altera_gpio_irq_unmask(struct irq_data *d)
46{
47 struct altera_gpio_chip *altera_gc;
48 struct of_mm_gpio_chip *mm_gc;
49 unsigned long flags;
50 u32 intmask;
51
52 altera_gc = irq_data_get_irq_chip_data(d);
53 mm_gc = &altera_gc->mmchip;
54
55 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
56 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
57 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
58 intmask |= BIT(irqd_to_hwirq(d));
59 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
60 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
61}
62
63static void altera_gpio_irq_mask(struct irq_data *d)
64{
65 struct altera_gpio_chip *altera_gc;
66 struct of_mm_gpio_chip *mm_gc;
67 unsigned long flags;
68 u32 intmask;
69
70 altera_gc = irq_data_get_irq_chip_data(d);
71 mm_gc = &altera_gc->mmchip;
72
73 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
74 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
75 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
76 intmask &= ~BIT(irqd_to_hwirq(d));
77 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
78 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
79}
80
81/**
82 * This controller's IRQ type is synthesized in hardware, so this function
83 * just checks if the requested set_type matches the synthesized IRQ type
84 */
85static int altera_gpio_irq_set_type(struct irq_data *d,
86 unsigned int type)
87{
88 struct altera_gpio_chip *altera_gc;
89
90 altera_gc = irq_data_get_irq_chip_data(d);
91
92 if (type == IRQ_TYPE_NONE)
93 return 0;
94 if (type == IRQ_TYPE_LEVEL_HIGH &&
95 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
96 return 0;
97 if (type == IRQ_TYPE_EDGE_RISING &&
98 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)
99 return 0;
100 if (type == IRQ_TYPE_EDGE_FALLING &&
101 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
102 return 0;
103 if (type == IRQ_TYPE_EDGE_BOTH &&
104 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
105 return 0;
106
107 return -EINVAL;
108}
109
110static unsigned int altera_gpio_irq_startup(struct irq_data *d) {
111 altera_gpio_irq_unmask(d);
112
113 return 0;
114}
115
116static struct irq_chip altera_irq_chip = {
117 .name = "altera-gpio",
118 .irq_mask = altera_gpio_irq_mask,
119 .irq_unmask = altera_gpio_irq_unmask,
120 .irq_set_type = altera_gpio_irq_set_type,
121 .irq_startup = altera_gpio_irq_startup,
122 .irq_shutdown = altera_gpio_irq_mask,
123};
124
125static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
126{
127 struct of_mm_gpio_chip *mm_gc;
128
129 mm_gc = to_of_mm_gpio_chip(gc);
130
131 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
132}
133
134static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
135{
136 struct of_mm_gpio_chip *mm_gc;
137 struct altera_gpio_chip *chip;
138 unsigned long flags;
139 unsigned int data_reg;
140
141 mm_gc = to_of_mm_gpio_chip(gc);
142 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
143
144 spin_lock_irqsave(&chip->gpio_lock, flags);
145 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
146 if (value)
147 data_reg |= BIT(offset);
148 else
149 data_reg &= ~BIT(offset);
150 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
151 spin_unlock_irqrestore(&chip->gpio_lock, flags);
152}
153
154static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
155{
156 struct of_mm_gpio_chip *mm_gc;
157 struct altera_gpio_chip *chip;
158 unsigned long flags;
159 unsigned int gpio_ddr;
160
161 mm_gc = to_of_mm_gpio_chip(gc);
162 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
163
164 spin_lock_irqsave(&chip->gpio_lock, flags);
165 /* Set pin as input, assumes software controlled IP */
166 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
167 gpio_ddr &= ~BIT(offset);
168 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
169 spin_unlock_irqrestore(&chip->gpio_lock, flags);
170
171 return 0;
172}
173
174static int altera_gpio_direction_output(struct gpio_chip *gc,
175 unsigned offset, int value)
176{
177 struct of_mm_gpio_chip *mm_gc;
178 struct altera_gpio_chip *chip;
179 unsigned long flags;
180 unsigned int data_reg, gpio_ddr;
181
182 mm_gc = to_of_mm_gpio_chip(gc);
183 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
184
185 spin_lock_irqsave(&chip->gpio_lock, flags);
186 /* Sets the GPIO value */
187 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
188 if (value)
189 data_reg |= BIT(offset);
190 else
191 data_reg &= ~BIT(offset);
192 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
193
194 /* Set pin as output, assumes software controlled IP */
195 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
196 gpio_ddr |= BIT(offset);
197 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
198 spin_unlock_irqrestore(&chip->gpio_lock, flags);
199
200 return 0;
201}
202
203static void altera_gpio_irq_edge_handler(unsigned int irq,
204 struct irq_desc *desc)
205{
206 struct altera_gpio_chip *altera_gc;
207 struct irq_chip *chip;
208 struct of_mm_gpio_chip *mm_gc;
209 struct irq_domain *irqdomain;
210 unsigned long status;
211 int i;
212
213 altera_gc = irq_desc_get_handler_data(desc);
214 chip = irq_desc_get_chip(desc);
215 mm_gc = &altera_gc->mmchip;
216 irqdomain = altera_gc->mmchip.gc.irqdomain;
217
218 chained_irq_enter(chip, desc);
219
220 while ((status =
221 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
222 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
223 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
224 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
225 generic_handle_irq(irq_find_mapping(irqdomain, i));
226 }
227 }
228
229 chained_irq_exit(chip, desc);
230}
231
232
233static void altera_gpio_irq_leveL_high_handler(unsigned int irq,
234 struct irq_desc *desc)
235{
236 struct altera_gpio_chip *altera_gc;
237 struct irq_chip *chip;
238 struct of_mm_gpio_chip *mm_gc;
239 struct irq_domain *irqdomain;
240 unsigned long status;
241 int i;
242
243 altera_gc = irq_desc_get_handler_data(desc);
244 chip = irq_desc_get_chip(desc);
245 mm_gc = &altera_gc->mmchip;
246 irqdomain = altera_gc->mmchip.gc.irqdomain;
247
248 chained_irq_enter(chip, desc);
249
250 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
251 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
252
253 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
254 generic_handle_irq(irq_find_mapping(irqdomain, i));
255 }
256 chained_irq_exit(chip, desc);
257}
258
259static int altera_gpio_probe(struct platform_device *pdev)
260{
261 struct device_node *node = pdev->dev.of_node;
262 int reg, ret;
263 struct altera_gpio_chip *altera_gc;
264
265 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
266 if (!altera_gc)
267 return -ENOMEM;
268
269 spin_lock_init(&altera_gc->gpio_lock);
270
271 if (of_property_read_u32(node, "altr,ngpio", &reg))
272 /* By default assume maximum ngpio */
273 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
274 else
275 altera_gc->mmchip.gc.ngpio = reg;
276
277 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
278 dev_warn(&pdev->dev,
279 "ngpio is greater than %d, defaulting to %d\n",
280 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
281 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
282 }
283
284 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
285 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
286 altera_gc->mmchip.gc.get = altera_gpio_get;
287 altera_gc->mmchip.gc.set = altera_gpio_set;
288 altera_gc->mmchip.gc.owner = THIS_MODULE;
289 altera_gc->mmchip.gc.dev = &pdev->dev;
290
291 ret = of_mm_gpiochip_add(node, &altera_gc->mmchip);
292 if (ret) {
293 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
294 return ret;
295 }
296
297 platform_set_drvdata(pdev, altera_gc);
298
299 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
300
301 if (altera_gc->mapped_irq < 0)
302 goto skip_irq;
303
304 if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
305 ret = -EINVAL;
306 dev_err(&pdev->dev,
307 "altr,interrupt-type value not set in device tree\n");
308 goto teardown;
309 }
310 altera_gc->interrupt_trigger = reg;
311
312 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
313 handle_simple_irq, IRQ_TYPE_NONE);
314
315 if (ret) {
316 dev_info(&pdev->dev, "could not add irqchip\n");
317 return ret;
318 }
319
320 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
321 &altera_irq_chip,
322 altera_gc->mapped_irq,
323 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
324 altera_gpio_irq_leveL_high_handler :
325 altera_gpio_irq_edge_handler);
326
327skip_irq:
328 return 0;
329teardown:
330 pr_err("%s: registration failed with status %d\n",
331 node->full_name, ret);
332
333 return ret;
334}
335
336static int altera_gpio_remove(struct platform_device *pdev)
337{
338 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
339
340 gpiochip_remove(&altera_gc->mmchip.gc);
341
342 return -EIO;
343}
344
345static const struct of_device_id altera_gpio_of_match[] = {
346 { .compatible = "altr,pio-1.0", },
347 {},
348};
349MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
350
351static struct platform_driver altera_gpio_driver = {
352 .driver = {
353 .name = "altera_gpio",
354 .of_match_table = of_match_ptr(altera_gpio_of_match),
355 },
356 .probe = altera_gpio_probe,
357 .remove = altera_gpio_remove,
358};
359
360static int __init altera_gpio_init(void)
361{
362 return platform_driver_register(&altera_gpio_driver);
363}
364subsys_initcall(altera_gpio_init);
365
366static void __exit altera_gpio_exit(void)
367{
368 platform_driver_unregister(&altera_gpio_driver);
369}
370module_exit(altera_gpio_exit);
371
372MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
373MODULE_DESCRIPTION("Altera GPIO driver");
374MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-arizona.c b/drivers/gpio/gpio-arizona.c
index 9665d0aa4ebb..052fbc8fdaaa 100644
--- a/drivers/gpio/gpio-arizona.c
+++ b/drivers/gpio/gpio-arizona.c
@@ -103,7 +103,7 @@ static int arizona_gpio_probe(struct platform_device *pdev)
103 103
104 arizona_gpio = devm_kzalloc(&pdev->dev, sizeof(*arizona_gpio), 104 arizona_gpio = devm_kzalloc(&pdev->dev, sizeof(*arizona_gpio),
105 GFP_KERNEL); 105 GFP_KERNEL);
106 if (arizona_gpio == NULL) 106 if (!arizona_gpio)
107 return -ENOMEM; 107 return -ENOMEM;
108 108
109 arizona_gpio->arizona = arizona; 109 arizona_gpio->arizona = arizona;
@@ -156,7 +156,6 @@ static int arizona_gpio_remove(struct platform_device *pdev)
156 156
157static struct platform_driver arizona_gpio_driver = { 157static struct platform_driver arizona_gpio_driver = {
158 .driver.name = "arizona-gpio", 158 .driver.name = "arizona-gpio",
159 .driver.owner = THIS_MODULE,
160 .probe = arizona_gpio_probe, 159 .probe = arizona_gpio_probe,
161 .remove = arizona_gpio_remove, 160 .remove = arizona_gpio_remove,
162}; 161};
diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c
index 3d9e08f7e823..91a7ffe83135 100644
--- a/drivers/gpio/gpio-crystalcove.c
+++ b/drivers/gpio/gpio-crystalcove.c
@@ -24,7 +24,7 @@
24#include <linux/mfd/intel_soc_pmic.h> 24#include <linux/mfd/intel_soc_pmic.h>
25 25
26#define CRYSTALCOVE_GPIO_NUM 16 26#define CRYSTALCOVE_GPIO_NUM 16
27#define CRYSTALCOVE_VGPIO_NUM 94 27#define CRYSTALCOVE_VGPIO_NUM 95
28 28
29#define UPDATE_IRQ_TYPE BIT(0) 29#define UPDATE_IRQ_TYPE BIT(0)
30#define UPDATE_IRQ_MASK BIT(1) 30#define UPDATE_IRQ_MASK BIT(1)
@@ -39,6 +39,7 @@
39#define GPIO0P0CTLI 0x33 39#define GPIO0P0CTLI 0x33
40#define GPIO1P0CTLO 0x3b 40#define GPIO1P0CTLO 0x3b
41#define GPIO1P0CTLI 0x43 41#define GPIO1P0CTLI 0x43
42#define GPIOPANELCTL 0x52
42 43
43#define CTLI_INTCNT_DIS (0) 44#define CTLI_INTCNT_DIS (0)
44#define CTLI_INTCNT_NE (1 << 1) 45#define CTLI_INTCNT_NE (1 << 1)
@@ -93,6 +94,10 @@ static inline int to_reg(int gpio, enum ctrl_register reg_type)
93{ 94{
94 int reg; 95 int reg;
95 96
97 if (gpio == 94) {
98 return GPIOPANELCTL;
99 }
100
96 if (reg_type == CTRL_IN) { 101 if (reg_type == CTRL_IN) {
97 if (gpio < 8) 102 if (gpio < 8)
98 reg = GPIO0P0CTLI; 103 reg = GPIO0P0CTLI;
diff --git a/drivers/gpio/gpio-da9052.c b/drivers/gpio/gpio-da9052.c
index 389a4d2a4926..2e9578ec0ca1 100644
--- a/drivers/gpio/gpio-da9052.c
+++ b/drivers/gpio/gpio-da9052.c
@@ -212,7 +212,7 @@ static int da9052_gpio_probe(struct platform_device *pdev)
212 int ret; 212 int ret;
213 213
214 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 214 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
215 if (gpio == NULL) 215 if (!gpio)
216 return -ENOMEM; 216 return -ENOMEM;
217 217
218 gpio->da9052 = dev_get_drvdata(pdev->dev.parent); 218 gpio->da9052 = dev_get_drvdata(pdev->dev.parent);
diff --git a/drivers/gpio/gpio-da9055.c b/drivers/gpio/gpio-da9055.c
index b8d757036887..7227e6ed3cb9 100644
--- a/drivers/gpio/gpio-da9055.c
+++ b/drivers/gpio/gpio-da9055.c
@@ -146,7 +146,7 @@ static int da9055_gpio_probe(struct platform_device *pdev)
146 int ret; 146 int ret;
147 147
148 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 148 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
149 if (gpio == NULL) 149 if (!gpio)
150 return -ENOMEM; 150 return -ENOMEM;
151 151
152 gpio->da9055 = dev_get_drvdata(pdev->dev.parent); 152 gpio->da9055 = dev_get_drvdata(pdev->dev.parent);
diff --git a/drivers/gpio/gpio-f7188x.c b/drivers/gpio/gpio-f7188x.c
index 1be291ac6319..dbda8433c4f7 100644
--- a/drivers/gpio/gpio-f7188x.c
+++ b/drivers/gpio/gpio-f7188x.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * GPIO driver for Fintek Super-I/O F71882 and F71889 2 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882 and F71889
3 * 3 *
4 * Copyright (C) 2010-2013 LaCie 4 * Copyright (C) 2010-2013 LaCie
5 * 5 *
@@ -32,12 +32,16 @@
32#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ 32#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
33 33
34#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */ 34#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
35#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
36#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
35#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */ 37#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
36#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */ 38#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
37 39
38enum chips { f71882fg, f71889f }; 40enum chips { f71869, f71869a, f71882fg, f71889f };
39 41
40static const char * const f7188x_names[] = { 42static const char * const f7188x_names[] = {
43 "f71869",
44 "f71869a",
41 "f71882fg", 45 "f71882fg",
42 "f71889f", 46 "f71889f",
43}; 47};
@@ -146,6 +150,27 @@ static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
146/* Output mode register (0:open drain 1:push-pull). */ 150/* Output mode register (0:open drain 1:push-pull). */
147#define gpio_out_mode(base) (base + 3) 151#define gpio_out_mode(base) (base + 3)
148 152
153static struct f7188x_gpio_bank f71869_gpio_bank[] = {
154 F7188X_GPIO_BANK(0, 6, 0xF0),
155 F7188X_GPIO_BANK(10, 8, 0xE0),
156 F7188X_GPIO_BANK(20, 8, 0xD0),
157 F7188X_GPIO_BANK(30, 8, 0xC0),
158 F7188X_GPIO_BANK(40, 8, 0xB0),
159 F7188X_GPIO_BANK(50, 5, 0xA0),
160 F7188X_GPIO_BANK(60, 6, 0x90),
161};
162
163static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
164 F7188X_GPIO_BANK(0, 6, 0xF0),
165 F7188X_GPIO_BANK(10, 8, 0xE0),
166 F7188X_GPIO_BANK(20, 8, 0xD0),
167 F7188X_GPIO_BANK(30, 8, 0xC0),
168 F7188X_GPIO_BANK(40, 8, 0xB0),
169 F7188X_GPIO_BANK(50, 5, 0xA0),
170 F7188X_GPIO_BANK(60, 8, 0x90),
171 F7188X_GPIO_BANK(70, 8, 0x80),
172};
173
149static struct f7188x_gpio_bank f71882_gpio_bank[] = { 174static struct f7188x_gpio_bank f71882_gpio_bank[] = {
150 F7188X_GPIO_BANK(0 , 8, 0xF0), 175 F7188X_GPIO_BANK(0 , 8, 0xF0),
151 F7188X_GPIO_BANK(10, 8, 0xE0), 176 F7188X_GPIO_BANK(10, 8, 0xE0),
@@ -281,6 +306,14 @@ static int f7188x_gpio_probe(struct platform_device *pdev)
281 return -ENOMEM; 306 return -ENOMEM;
282 307
283 switch (sio->type) { 308 switch (sio->type) {
309 case f71869:
310 data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
311 data->bank = f71869_gpio_bank;
312 break;
313 case f71869a:
314 data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
315 data->bank = f71869a_gpio_bank;
316 break;
284 case f71882fg: 317 case f71882fg:
285 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank); 318 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
286 data->bank = f71882_gpio_bank; 319 data->bank = f71882_gpio_bank;
@@ -354,6 +387,12 @@ static int __init f7188x_find(int addr, struct f7188x_sio *sio)
354 387
355 devid = superio_inw(addr, SIO_DEVID); 388 devid = superio_inw(addr, SIO_DEVID);
356 switch (devid) { 389 switch (devid) {
390 case SIO_F71869_ID:
391 sio->type = f71869;
392 break;
393 case SIO_F71869A_ID:
394 sio->type = f71869a;
395 break;
357 case SIO_F71882_ID: 396 case SIO_F71882_ID:
358 sio->type = f71882fg; 397 sio->type = f71882fg;
359 break; 398 break;
@@ -410,7 +449,7 @@ err:
410} 449}
411 450
412/* 451/*
413 * Try to match a supported Fintech device by reading the (hard-wired) 452 * Try to match a supported Fintek device by reading the (hard-wired)
414 * configuration I/O ports. If available, then register both the platform 453 * configuration I/O ports. If available, then register both the platform
415 * device and driver to support the GPIOs. 454 * device and driver to support the GPIOs.
416 */ 455 */
@@ -450,6 +489,6 @@ static void __exit f7188x_gpio_exit(void)
450} 489}
451module_exit(f7188x_gpio_exit); 490module_exit(f7188x_gpio_exit);
452 491
453MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71882FG and F71889F"); 492MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG and F71889F");
454MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>"); 493MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
455MODULE_LICENSE("GPL"); 494MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index 7818cd1453ae..4ba7ed502131 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -173,6 +173,11 @@ static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
173 return !!(ichx_priv.use_gpio & (1 << (nr / 32))); 173 return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
174} 174}
175 175
176static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
177{
178 return ichx_read_bit(GPIO_IO_SEL, nr) ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
179}
180
176static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 181static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
177{ 182{
178 /* 183 /*
@@ -286,6 +291,7 @@ static void ichx_gpiolib_setup(struct gpio_chip *chip)
286 ichx_priv.desc->get : ichx_gpio_get; 291 ichx_priv.desc->get : ichx_gpio_get;
287 292
288 chip->set = ichx_gpio_set; 293 chip->set = ichx_gpio_set;
294 chip->get_direction = ichx_gpio_get_direction;
289 chip->direction_input = ichx_gpio_direction_input; 295 chip->direction_input = ichx_gpio_direction_input;
290 chip->direction_output = ichx_gpio_direction_output; 296 chip->direction_output = ichx_gpio_direction_output;
291 chip->base = modparam_gpiobase; 297 chip->base = modparam_gpiobase;
diff --git a/drivers/gpio/gpio-kempld.c b/drivers/gpio/gpio-kempld.c
index 443518f63f15..6b8115f34208 100644
--- a/drivers/gpio/gpio-kempld.c
+++ b/drivers/gpio/gpio-kempld.c
@@ -156,7 +156,7 @@ static int kempld_gpio_probe(struct platform_device *pdev)
156 } 156 }
157 157
158 gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL); 158 gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
159 if (gpio == NULL) 159 if (!gpio)
160 return -ENOMEM; 160 return -ENOMEM;
161 161
162 gpio->pld = pld; 162 gpio->pld = pld;
diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c
new file mode 100644
index 000000000000..ccc65a1aea88
--- /dev/null
+++ b/drivers/gpio/gpio-loongson.c
@@ -0,0 +1,115 @@
1/*
2 * Loongson-2F/3A/3B GPIO Support
3 *
4 * Copyright (c) 2008 Richard Liu, STMicroelectronics <richard.liu@st.com>
5 * Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com>
6 * Copyright (c) 2013 Hongbing Hu <huhb@lemote.com>
7 * Copyright (c) 2014 Huacai Chen <chenhc@lemote.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/spinlock.h>
19#include <linux/err.h>
20#include <asm/types.h>
21#include <loongson.h>
22#include <linux/gpio.h>
23
24#define STLS2F_N_GPIO 4
25#define STLS3A_N_GPIO 16
26
27#ifdef CONFIG_CPU_LOONGSON3
28#define LOONGSON_N_GPIO STLS3A_N_GPIO
29#else
30#define LOONGSON_N_GPIO STLS2F_N_GPIO
31#endif
32
33#define LOONGSON_GPIO_IN_OFFSET 16
34
35static DEFINE_SPINLOCK(gpio_lock);
36
37static int loongson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
38{
39 u32 temp;
40 u32 mask;
41
42 spin_lock(&gpio_lock);
43 mask = 1 << gpio;
44 temp = LOONGSON_GPIOIE;
45 temp |= mask;
46 LOONGSON_GPIOIE = temp;
47 spin_unlock(&gpio_lock);
48
49 return 0;
50}
51
52static int loongson_gpio_direction_output(struct gpio_chip *chip,
53 unsigned gpio, int level)
54{
55 u32 temp;
56 u32 mask;
57
58 gpio_set_value(gpio, level);
59 spin_lock(&gpio_lock);
60 mask = 1 << gpio;
61 temp = LOONGSON_GPIOIE;
62 temp &= (~mask);
63 LOONGSON_GPIOIE = temp;
64 spin_unlock(&gpio_lock);
65
66 return 0;
67}
68
69static int loongson_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
70{
71 u32 val;
72 u32 mask;
73
74 mask = 1 << (gpio + LOONGSON_GPIO_IN_OFFSET);
75 spin_lock(&gpio_lock);
76 val = LOONGSON_GPIODATA;
77 spin_unlock(&gpio_lock);
78
79 return (val & mask) != 0;
80}
81
82static void loongson_gpio_set_value(struct gpio_chip *chip,
83 unsigned gpio, int value)
84{
85 u32 val;
86 u32 mask;
87
88 mask = 1 << gpio;
89
90 spin_lock(&gpio_lock);
91 val = LOONGSON_GPIODATA;
92 if (value)
93 val |= mask;
94 else
95 val &= (~mask);
96 LOONGSON_GPIODATA = val;
97 spin_unlock(&gpio_lock);
98}
99
100static struct gpio_chip loongson_chip = {
101 .label = "Loongson-gpio-chip",
102 .direction_input = loongson_gpio_direction_input,
103 .get = loongson_gpio_get_value,
104 .direction_output = loongson_gpio_direction_output,
105 .set = loongson_gpio_set_value,
106 .base = 0,
107 .ngpio = LOONGSON_N_GPIO,
108 .can_sleep = false,
109};
110
111static int __init loongson_gpio_setup(void)
112{
113 return gpiochip_add(&loongson_chip);
114}
115postcore_initcall(loongson_gpio_setup);
diff --git a/drivers/gpio/gpio-max7300.c b/drivers/gpio/gpio-max7300.c
index 40ab6dfb6021..0cc2c279ab5c 100644
--- a/drivers/gpio/gpio-max7300.c
+++ b/drivers/gpio/gpio-max7300.c
@@ -35,7 +35,6 @@ static int max7300_probe(struct i2c_client *client,
35 const struct i2c_device_id *id) 35 const struct i2c_device_id *id)
36{ 36{
37 struct max7301 *ts; 37 struct max7301 *ts;
38 int ret;
39 38
40 if (!i2c_check_functionality(client->adapter, 39 if (!i2c_check_functionality(client->adapter,
41 I2C_FUNC_SMBUS_BYTE_DATA)) 40 I2C_FUNC_SMBUS_BYTE_DATA))
@@ -49,8 +48,7 @@ static int max7300_probe(struct i2c_client *client,
49 ts->write = max7300_i2c_write; 48 ts->write = max7300_i2c_write;
50 ts->dev = &client->dev; 49 ts->dev = &client->dev;
51 50
52 ret = __max730x_probe(ts); 51 return __max730x_probe(ts);
53 return ret;
54} 52}
55 53
56static int max7300_remove(struct i2c_client *client) 54static int max7300_remove(struct i2c_client *client)
diff --git a/drivers/gpio/gpio-max732x.c b/drivers/gpio/gpio-max732x.c
index a095b2393fe9..0fa4543c5e02 100644
--- a/drivers/gpio/gpio-max732x.c
+++ b/drivers/gpio/gpio-max732x.c
@@ -4,6 +4,7 @@
4 * Copyright (C) 2007 Marvell International Ltd. 4 * Copyright (C) 2007 Marvell International Ltd.
5 * Copyright (C) 2008 Jack Ren <jack.ren@marvell.com> 5 * Copyright (C) 2008 Jack Ren <jack.ren@marvell.com>
6 * Copyright (C) 2008 Eric Miao <eric.miao@marvell.com> 6 * Copyright (C) 2008 Eric Miao <eric.miao@marvell.com>
7 * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org>
7 * 8 *
8 * Derived from drivers/gpio/pca953x.c 9 * Derived from drivers/gpio/pca953x.c
9 * 10 *
@@ -16,10 +17,8 @@
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/slab.h> 18#include <linux/slab.h>
18#include <linux/string.h> 19#include <linux/string.h>
19#include <linux/gpio.h> 20#include <linux/gpio/driver.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/i2c.h> 22#include <linux/i2c.h>
24#include <linux/i2c/max732x.h> 23#include <linux/i2c/max732x.h>
25#include <linux/of.h> 24#include <linux/of.h>
@@ -150,9 +149,7 @@ struct max732x_chip {
150 uint8_t reg_out[2]; 149 uint8_t reg_out[2];
151 150
152#ifdef CONFIG_GPIO_MAX732X_IRQ 151#ifdef CONFIG_GPIO_MAX732X_IRQ
153 struct irq_domain *irq_domain;
154 struct mutex irq_lock; 152 struct mutex irq_lock;
155 int irq_base;
156 uint8_t irq_mask; 153 uint8_t irq_mask;
157 uint8_t irq_mask_cur; 154 uint8_t irq_mask_cur;
158 uint8_t irq_trig_raise; 155 uint8_t irq_trig_raise;
@@ -356,35 +353,26 @@ static void max732x_irq_update_mask(struct max732x_chip *chip)
356 mutex_unlock(&chip->lock); 353 mutex_unlock(&chip->lock);
357} 354}
358 355
359static int max732x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
360{
361 struct max732x_chip *chip = to_max732x(gc);
362
363 if (chip->irq_domain) {
364 return irq_create_mapping(chip->irq_domain,
365 chip->irq_base + off);
366 } else {
367 return -ENXIO;
368 }
369}
370
371static void max732x_irq_mask(struct irq_data *d) 356static void max732x_irq_mask(struct irq_data *d)
372{ 357{
373 struct max732x_chip *chip = irq_data_get_irq_chip_data(d); 358 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
359 struct max732x_chip *chip = to_max732x(gc);
374 360
375 chip->irq_mask_cur &= ~(1 << d->hwirq); 361 chip->irq_mask_cur &= ~(1 << d->hwirq);
376} 362}
377 363
378static void max732x_irq_unmask(struct irq_data *d) 364static void max732x_irq_unmask(struct irq_data *d)
379{ 365{
380 struct max732x_chip *chip = irq_data_get_irq_chip_data(d); 366 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
367 struct max732x_chip *chip = to_max732x(gc);
381 368
382 chip->irq_mask_cur |= 1 << d->hwirq; 369 chip->irq_mask_cur |= 1 << d->hwirq;
383} 370}
384 371
385static void max732x_irq_bus_lock(struct irq_data *d) 372static void max732x_irq_bus_lock(struct irq_data *d)
386{ 373{
387 struct max732x_chip *chip = irq_data_get_irq_chip_data(d); 374 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
375 struct max732x_chip *chip = to_max732x(gc);
388 376
389 mutex_lock(&chip->irq_lock); 377 mutex_lock(&chip->irq_lock);
390 chip->irq_mask_cur = chip->irq_mask; 378 chip->irq_mask_cur = chip->irq_mask;
@@ -392,7 +380,8 @@ static void max732x_irq_bus_lock(struct irq_data *d)
392 380
393static void max732x_irq_bus_sync_unlock(struct irq_data *d) 381static void max732x_irq_bus_sync_unlock(struct irq_data *d)
394{ 382{
395 struct max732x_chip *chip = irq_data_get_irq_chip_data(d); 383 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
384 struct max732x_chip *chip = to_max732x(gc);
396 uint16_t new_irqs; 385 uint16_t new_irqs;
397 uint16_t level; 386 uint16_t level;
398 387
@@ -410,7 +399,8 @@ static void max732x_irq_bus_sync_unlock(struct irq_data *d)
410 399
411static int max732x_irq_set_type(struct irq_data *d, unsigned int type) 400static int max732x_irq_set_type(struct irq_data *d, unsigned int type)
412{ 401{
413 struct max732x_chip *chip = irq_data_get_irq_chip_data(d); 402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403 struct max732x_chip *chip = to_max732x(gc);
414 uint16_t off = d->hwirq; 404 uint16_t off = d->hwirq;
415 uint16_t mask = 1 << off; 405 uint16_t mask = 1 << off;
416 406
@@ -492,7 +482,8 @@ static irqreturn_t max732x_irq_handler(int irq, void *devid)
492 482
493 do { 483 do {
494 level = __ffs(pending); 484 level = __ffs(pending);
495 handle_nested_irq(irq_find_mapping(chip->irq_domain, level)); 485 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
486 level));
496 487
497 pending &= ~(1 << level); 488 pending &= ~(1 << level);
498 } while (pending); 489 } while (pending);
@@ -500,86 +491,50 @@ static irqreturn_t max732x_irq_handler(int irq, void *devid)
500 return IRQ_HANDLED; 491 return IRQ_HANDLED;
501} 492}
502 493
503static int max732x_irq_map(struct irq_domain *h, unsigned int virq,
504 irq_hw_number_t hw)
505{
506 struct max732x_chip *chip = h->host_data;
507
508 if (!(chip->dir_input & (1 << hw))) {
509 dev_err(&chip->client->dev,
510 "Attempt to map output line as IRQ line: %lu\n",
511 hw);
512 return -EPERM;
513 }
514
515 irq_set_chip_data(virq, chip);
516 irq_set_chip_and_handler(virq, &max732x_irq_chip,
517 handle_edge_irq);
518 irq_set_nested_thread(virq, 1);
519#ifdef CONFIG_ARM
520 /* ARM needs us to explicitly flag the IRQ as valid
521 * and will set them noprobe when we do so. */
522 set_irq_flags(virq, IRQF_VALID);
523#else
524 irq_set_noprobe(virq);
525#endif
526
527 return 0;
528}
529
530static struct irq_domain_ops max732x_irq_domain_ops = {
531 .map = max732x_irq_map,
532 .xlate = irq_domain_xlate_twocell,
533};
534
535static void max732x_irq_teardown(struct max732x_chip *chip)
536{
537 if (chip->client->irq && chip->irq_domain)
538 irq_domain_remove(chip->irq_domain);
539}
540
541static int max732x_irq_setup(struct max732x_chip *chip, 494static int max732x_irq_setup(struct max732x_chip *chip,
542 const struct i2c_device_id *id) 495 const struct i2c_device_id *id)
543{ 496{
544 struct i2c_client *client = chip->client; 497 struct i2c_client *client = chip->client;
545 struct max732x_platform_data *pdata = dev_get_platdata(&client->dev); 498 struct max732x_platform_data *pdata = dev_get_platdata(&client->dev);
546 int has_irq = max732x_features[id->driver_data] >> 32; 499 int has_irq = max732x_features[id->driver_data] >> 32;
500 int irq_base = 0;
547 int ret; 501 int ret;
548 502
549 if (((pdata && pdata->irq_base) || client->irq) 503 if (((pdata && pdata->irq_base) || client->irq)
550 && has_irq != INT_NONE) { 504 && has_irq != INT_NONE) {
551 if (pdata) 505 if (pdata)
552 chip->irq_base = pdata->irq_base; 506 irq_base = pdata->irq_base;
553 chip->irq_features = has_irq; 507 chip->irq_features = has_irq;
554 mutex_init(&chip->irq_lock); 508 mutex_init(&chip->irq_lock);
555 509
556 chip->irq_domain = irq_domain_add_simple(client->dev.of_node, 510 ret = devm_request_threaded_irq(&client->dev,
557 chip->gpio_chip.ngpio, chip->irq_base, 511 client->irq,
558 &max732x_irq_domain_ops, chip); 512 NULL,
559 if (!chip->irq_domain) { 513 max732x_irq_handler,
560 dev_err(&client->dev, "Failed to create IRQ domain\n"); 514 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
561 return -ENOMEM; 515 dev_name(&client->dev), chip);
562 }
563
564 ret = request_threaded_irq(client->irq,
565 NULL,
566 max732x_irq_handler,
567 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
568 dev_name(&client->dev), chip);
569 if (ret) { 516 if (ret) {
570 dev_err(&client->dev, "failed to request irq %d\n", 517 dev_err(&client->dev, "failed to request irq %d\n",
571 client->irq); 518 client->irq);
572 goto out_failed; 519 return ret;
573 } 520 }
574 521 ret = gpiochip_irqchip_add(&chip->gpio_chip,
575 chip->gpio_chip.to_irq = max732x_gpio_to_irq; 522 &max732x_irq_chip,
523 irq_base,
524 handle_edge_irq,
525 IRQ_TYPE_NONE);
526 if (ret) {
527 dev_err(&client->dev,
528 "could not connect irqchip to gpiochip\n");
529 return ret;
530 }
531 gpiochip_set_chained_irqchip(&chip->gpio_chip,
532 &max732x_irq_chip,
533 client->irq,
534 NULL);
576 } 535 }
577 536
578 return 0; 537 return 0;
579
580out_failed:
581 max732x_irq_teardown(chip);
582 return ret;
583} 538}
584 539
585#else /* CONFIG_GPIO_MAX732X_IRQ */ 540#else /* CONFIG_GPIO_MAX732X_IRQ */
@@ -595,10 +550,6 @@ static int max732x_irq_setup(struct max732x_chip *chip,
595 550
596 return 0; 551 return 0;
597} 552}
598
599static void max732x_irq_teardown(struct max732x_chip *chip)
600{
601}
602#endif 553#endif
603 554
604static int max732x_setup_gpio(struct max732x_chip *chip, 555static int max732x_setup_gpio(struct max732x_chip *chip,
@@ -730,13 +681,15 @@ static int max732x_probe(struct i2c_client *client,
730 if (nr_port > 8) 681 if (nr_port > 8)
731 max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]); 682 max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]);
732 683
733 ret = max732x_irq_setup(chip, id); 684 ret = gpiochip_add(&chip->gpio_chip);
734 if (ret) 685 if (ret)
735 goto out_failed; 686 goto out_failed;
736 687
737 ret = gpiochip_add(&chip->gpio_chip); 688 ret = max732x_irq_setup(chip, id);
738 if (ret) 689 if (ret) {
690 gpiochip_remove(&chip->gpio_chip);
739 goto out_failed; 691 goto out_failed;
692 }
740 693
741 if (pdata && pdata->setup) { 694 if (pdata && pdata->setup) {
742 ret = pdata->setup(client, chip->gpio_chip.base, 695 ret = pdata->setup(client, chip->gpio_chip.base,
@@ -751,7 +704,6 @@ static int max732x_probe(struct i2c_client *client,
751out_failed: 704out_failed:
752 if (chip->client_dummy) 705 if (chip->client_dummy)
753 i2c_unregister_device(chip->client_dummy); 706 i2c_unregister_device(chip->client_dummy);
754 max732x_irq_teardown(chip);
755 return ret; 707 return ret;
756} 708}
757 709
@@ -774,8 +726,6 @@ static int max732x_remove(struct i2c_client *client)
774 726
775 gpiochip_remove(&chip->gpio_chip); 727 gpiochip_remove(&chip->gpio_chip);
776 728
777 max732x_irq_teardown(chip);
778
779 /* unregister any dummy i2c_client */ 729 /* unregister any dummy i2c_client */
780 if (chip->client_dummy) 730 if (chip->client_dummy)
781 i2c_unregister_device(chip->client_dummy); 731 i2c_unregister_device(chip->client_dummy);
diff --git a/drivers/gpio/gpio-mb86s7x.c b/drivers/gpio/gpio-mb86s7x.c
index 21b1ce5abdfe..ee93c0ab0a59 100644
--- a/drivers/gpio/gpio-mb86s7x.c
+++ b/drivers/gpio/gpio-mb86s7x.c
@@ -58,6 +58,11 @@ static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
58 spin_lock_irqsave(&gchip->lock, flags); 58 spin_lock_irqsave(&gchip->lock, flags);
59 59
60 val = readl(gchip->base + PFR(gpio)); 60 val = readl(gchip->base + PFR(gpio));
61 if (!(val & OFFSET(gpio))) {
62 spin_unlock_irqrestore(&gchip->lock, flags);
63 return -EINVAL;
64 }
65
61 val &= ~OFFSET(gpio); 66 val &= ~OFFSET(gpio);
62 writel(val, gchip->base + PFR(gpio)); 67 writel(val, gchip->base + PFR(gpio));
63 68
diff --git a/drivers/gpio/gpio-mc33880.c b/drivers/gpio/gpio-mc33880.c
index 4e3e160e5db2..a431604c9e67 100644
--- a/drivers/gpio/gpio-mc33880.c
+++ b/drivers/gpio/gpio-mc33880.c
@@ -151,7 +151,7 @@ static int mc33880_remove(struct spi_device *spi)
151 struct mc33880 *mc; 151 struct mc33880 *mc;
152 152
153 mc = spi_get_drvdata(spi); 153 mc = spi_get_drvdata(spi);
154 if (mc == NULL) 154 if (!mc)
155 return -ENODEV; 155 return -ENODEV;
156 156
157 gpiochip_remove(&mc->chip); 157 gpiochip_remove(&mc->chip);
diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index eea5d7e578c9..2fc7ff852d16 100644
--- a/drivers/gpio/gpio-mcp23s08.c
+++ b/drivers/gpio/gpio-mcp23s08.c
@@ -949,10 +949,12 @@ static int mcp23s08_probe(struct spi_device *spi)
949 if (!chips) 949 if (!chips)
950 return -ENODEV; 950 return -ENODEV;
951 951
952 data = kzalloc(sizeof(*data) + chips * sizeof(struct mcp23s08), 952 data = devm_kzalloc(&spi->dev,
953 GFP_KERNEL); 953 sizeof(*data) + chips * sizeof(struct mcp23s08),
954 GFP_KERNEL);
954 if (!data) 955 if (!data)
955 return -ENOMEM; 956 return -ENOMEM;
957
956 spi_set_drvdata(spi, data); 958 spi_set_drvdata(spi, data);
957 959
958 spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0); 960 spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
@@ -989,7 +991,6 @@ fail:
989 continue; 991 continue;
990 gpiochip_remove(&data->mcp[addr]->chip); 992 gpiochip_remove(&data->mcp[addr]->chip);
991 } 993 }
992 kfree(data);
993 return status; 994 return status;
994} 995}
995 996
@@ -1007,7 +1008,7 @@ static int mcp23s08_remove(struct spi_device *spi)
1007 mcp23s08_irq_teardown(data->mcp[addr]); 1008 mcp23s08_irq_teardown(data->mcp[addr]);
1008 gpiochip_remove(&data->mcp[addr]->chip); 1009 gpiochip_remove(&data->mcp[addr]->chip);
1009 } 1010 }
1010 kfree(data); 1011
1011 return 0; 1012 return 0;
1012} 1013}
1013 1014
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index d0bc123c7975..1a54205860f5 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -320,11 +320,13 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
320{ 320{
321 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 321 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
322 struct mvebu_gpio_chip *mvchip = gc->private; 322 struct mvebu_gpio_chip *mvchip = gc->private;
323 struct irq_chip_type *ct = irq_data_get_chip_type(d);
323 u32 mask = 1 << (d->irq - gc->irq_base); 324 u32 mask = 1 << (d->irq - gc->irq_base);
324 325
325 irq_gc_lock(gc); 326 irq_gc_lock(gc);
326 gc->mask_cache &= ~mask; 327 ct->mask_cache_priv &= ~mask;
327 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 328
329 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
328 irq_gc_unlock(gc); 330 irq_gc_unlock(gc);
329} 331}
330 332
@@ -332,11 +334,13 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
332{ 334{
333 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 335 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
334 struct mvebu_gpio_chip *mvchip = gc->private; 336 struct mvebu_gpio_chip *mvchip = gc->private;
337 struct irq_chip_type *ct = irq_data_get_chip_type(d);
338
335 u32 mask = 1 << (d->irq - gc->irq_base); 339 u32 mask = 1 << (d->irq - gc->irq_base);
336 340
337 irq_gc_lock(gc); 341 irq_gc_lock(gc);
338 gc->mask_cache |= mask; 342 ct->mask_cache_priv |= mask;
339 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 343 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
340 irq_gc_unlock(gc); 344 irq_gc_unlock(gc);
341} 345}
342 346
@@ -344,11 +348,13 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d)
344{ 348{
345 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 349 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
346 struct mvebu_gpio_chip *mvchip = gc->private; 350 struct mvebu_gpio_chip *mvchip = gc->private;
351 struct irq_chip_type *ct = irq_data_get_chip_type(d);
352
347 u32 mask = 1 << (d->irq - gc->irq_base); 353 u32 mask = 1 << (d->irq - gc->irq_base);
348 354
349 irq_gc_lock(gc); 355 irq_gc_lock(gc);
350 gc->mask_cache &= ~mask; 356 ct->mask_cache_priv &= ~mask;
351 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 357 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
352 irq_gc_unlock(gc); 358 irq_gc_unlock(gc);
353} 359}
354 360
@@ -356,11 +362,13 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
356{ 362{
357 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 363 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
358 struct mvebu_gpio_chip *mvchip = gc->private; 364 struct mvebu_gpio_chip *mvchip = gc->private;
365 struct irq_chip_type *ct = irq_data_get_chip_type(d);
366
359 u32 mask = 1 << (d->irq - gc->irq_base); 367 u32 mask = 1 << (d->irq - gc->irq_base);
360 368
361 irq_gc_lock(gc); 369 irq_gc_lock(gc);
362 gc->mask_cache |= mask; 370 ct->mask_cache_priv |= mask;
363 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 371 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
364 irq_gc_unlock(gc); 372 irq_gc_unlock(gc);
365} 373}
366 374
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f476ae2eb0b3..cd1d5bf48f36 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -75,14 +75,12 @@ struct gpio_bank {
75 int power_mode; 75 int power_mode;
76 bool workaround_enabled; 76 bool workaround_enabled;
77 77
78 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); 78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
79 int (*get_context_loss_count)(struct device *dev); 79 int (*get_context_loss_count)(struct device *dev);
80 80
81 struct omap_gpio_reg_offs *regs; 81 struct omap_gpio_reg_offs *regs;
82}; 82};
83 83
84#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85#define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio)))
86#define GPIO_MOD_CTRL_BIT BIT(0) 84#define GPIO_MOD_CTRL_BIT BIT(0)
87 85
88#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) 86#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
@@ -90,11 +88,6 @@ struct gpio_bank {
90 88
91static void omap_gpio_unmask_irq(struct irq_data *d); 89static void omap_gpio_unmask_irq(struct irq_data *d);
92 90
93static int omap_irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
94{
95 return bank->chip.base + gpio_irq;
96}
97
98static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) 91static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
99{ 92{
100 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 93 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
@@ -119,11 +112,11 @@ static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
119 112
120 113
121/* set data out value using dedicate set/clear register */ 114/* set data out value using dedicate set/clear register */
122static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, 115static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
123 int enable) 116 int enable)
124{ 117{
125 void __iomem *reg = bank->base; 118 void __iomem *reg = bank->base;
126 u32 l = GPIO_BIT(bank, gpio); 119 u32 l = BIT(offset);
127 120
128 if (enable) { 121 if (enable) {
129 reg += bank->regs->set_dataout; 122 reg += bank->regs->set_dataout;
@@ -137,11 +130,11 @@ static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, int gpio,
137} 130}
138 131
139/* set data out value using mask register */ 132/* set data out value using mask register */
140static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, 133static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
141 int enable) 134 int enable)
142{ 135{
143 void __iomem *reg = bank->base + bank->regs->dataout; 136 void __iomem *reg = bank->base + bank->regs->dataout;
144 u32 gpio_bit = GPIO_BIT(bank, gpio); 137 u32 gpio_bit = BIT(offset);
145 u32 l; 138 u32 l;
146 139
147 l = readl_relaxed(reg); 140 l = readl_relaxed(reg);
@@ -208,13 +201,13 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
208/** 201/**
209 * omap2_set_gpio_debounce - low level gpio debounce time 202 * omap2_set_gpio_debounce - low level gpio debounce time
210 * @bank: the gpio bank we're acting upon 203 * @bank: the gpio bank we're acting upon
211 * @gpio: the gpio number on this @gpio 204 * @offset: the gpio number on this @bank
212 * @debounce: debounce time to use 205 * @debounce: debounce time to use
213 * 206 *
214 * OMAP's debounce time is in 31us steps so we need 207 * OMAP's debounce time is in 31us steps so we need
215 * to convert and round up to the closest unit. 208 * to convert and round up to the closest unit.
216 */ 209 */
217static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, 210static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
218 unsigned debounce) 211 unsigned debounce)
219{ 212{
220 void __iomem *reg; 213 void __iomem *reg;
@@ -231,7 +224,7 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
231 else 224 else
232 debounce = (debounce / 0x1f) - 1; 225 debounce = (debounce / 0x1f) - 1;
233 226
234 l = GPIO_BIT(bank, gpio); 227 l = BIT(offset);
235 228
236 clk_prepare_enable(bank->dbck); 229 clk_prepare_enable(bank->dbck);
237 reg = bank->base + bank->regs->debounce; 230 reg = bank->base + bank->regs->debounce;
@@ -266,16 +259,16 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
266/** 259/**
267 * omap_clear_gpio_debounce - clear debounce settings for a gpio 260 * omap_clear_gpio_debounce - clear debounce settings for a gpio
268 * @bank: the gpio bank we're acting upon 261 * @bank: the gpio bank we're acting upon
269 * @gpio: the gpio number on this @gpio 262 * @offset: the gpio number on this @bank
270 * 263 *
271 * If a gpio is using debounce, then clear the debounce enable bit and if 264 * If a gpio is using debounce, then clear the debounce enable bit and if
272 * this is the only gpio in this bank using debounce, then clear the debounce 265 * this is the only gpio in this bank using debounce, then clear the debounce
273 * time too. The debounce clock will also be disabled when calling this function 266 * time too. The debounce clock will also be disabled when calling this function
274 * if this is the only gpio in the bank using debounce. 267 * if this is the only gpio in the bank using debounce.
275 */ 268 */
276static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) 269static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
277{ 270{
278 u32 gpio_bit = GPIO_BIT(bank, gpio); 271 u32 gpio_bit = BIT(offset);
279 272
280 if (!bank->dbck_flag) 273 if (!bank->dbck_flag)
281 return; 274 return;
@@ -472,42 +465,32 @@ static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
472 } 465 }
473} 466}
474 467
475static int omap_gpio_is_input(struct gpio_bank *bank, int mask) 468static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
476{ 469{
477 void __iomem *reg = bank->base + bank->regs->direction; 470 void __iomem *reg = bank->base + bank->regs->direction;
478 471
479 return readl_relaxed(reg) & mask; 472 return readl_relaxed(reg) & BIT(offset);
480} 473}
481 474
482static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned gpio, 475static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
483 unsigned offset)
484{ 476{
485 if (!LINE_USED(bank->mod_usage, offset)) { 477 if (!LINE_USED(bank->mod_usage, offset)) {
486 omap_enable_gpio_module(bank, offset); 478 omap_enable_gpio_module(bank, offset);
487 omap_set_gpio_direction(bank, offset, 1); 479 omap_set_gpio_direction(bank, offset, 1);
488 } 480 }
489 bank->irq_usage |= BIT(GPIO_INDEX(bank, gpio)); 481 bank->irq_usage |= BIT(offset);
490} 482}
491 483
492static int omap_gpio_irq_type(struct irq_data *d, unsigned type) 484static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
493{ 485{
494 struct gpio_bank *bank = omap_irq_data_get_bank(d); 486 struct gpio_bank *bank = omap_irq_data_get_bank(d);
495 unsigned gpio = 0;
496 int retval; 487 int retval;
497 unsigned long flags; 488 unsigned long flags;
498 unsigned offset; 489 unsigned offset = d->hwirq;
499 490
500 if (!BANK_USED(bank)) 491 if (!BANK_USED(bank))
501 pm_runtime_get_sync(bank->dev); 492 pm_runtime_get_sync(bank->dev);
502 493
503#ifdef CONFIG_ARCH_OMAP1
504 if (d->irq > IH_MPUIO_BASE)
505 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
506#endif
507
508 if (!gpio)
509 gpio = omap_irq_to_gpio(bank, d->hwirq);
510
511 if (type & ~IRQ_TYPE_SENSE_MASK) 494 if (type & ~IRQ_TYPE_SENSE_MASK)
512 return -EINVAL; 495 return -EINVAL;
513 496
@@ -516,10 +499,9 @@ static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
516 return -EINVAL; 499 return -EINVAL;
517 500
518 spin_lock_irqsave(&bank->lock, flags); 501 spin_lock_irqsave(&bank->lock, flags);
519 offset = GPIO_INDEX(bank, gpio);
520 retval = omap_set_gpio_triggering(bank, offset, type); 502 retval = omap_set_gpio_triggering(bank, offset, type);
521 omap_gpio_init_irq(bank, gpio, offset); 503 omap_gpio_init_irq(bank, offset);
522 if (!omap_gpio_is_input(bank, BIT(offset))) { 504 if (!omap_gpio_is_input(bank, offset)) {
523 spin_unlock_irqrestore(&bank->lock, flags); 505 spin_unlock_irqrestore(&bank->lock, flags);
524 return -EINVAL; 506 return -EINVAL;
525 } 507 }
@@ -550,9 +532,10 @@ static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
550 readl_relaxed(reg); 532 readl_relaxed(reg);
551} 533}
552 534
553static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 535static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
536 unsigned offset)
554{ 537{
555 omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 538 omap_clear_gpio_irqbank(bank, BIT(offset));
556} 539}
557 540
558static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) 541static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
@@ -613,13 +596,13 @@ static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
613 writel_relaxed(l, reg); 596 writel_relaxed(l, reg);
614} 597}
615 598
616static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio, 599static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
617 int enable) 600 unsigned offset, int enable)
618{ 601{
619 if (enable) 602 if (enable)
620 omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 603 omap_enable_gpio_irqbank(bank, BIT(offset));
621 else 604 else
622 omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 605 omap_disable_gpio_irqbank(bank, BIT(offset));
623} 606}
624 607
625/* 608/*
@@ -630,14 +613,16 @@ static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio,
630 * enabled. When system is suspended, only selected GPIO interrupts need 613 * enabled. When system is suspended, only selected GPIO interrupts need
631 * to have wake-up enabled. 614 * to have wake-up enabled.
632 */ 615 */
633static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 616static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
617 int enable)
634{ 618{
635 u32 gpio_bit = GPIO_BIT(bank, gpio); 619 u32 gpio_bit = BIT(offset);
636 unsigned long flags; 620 unsigned long flags;
637 621
638 if (bank->non_wakeup_gpios & gpio_bit) { 622 if (bank->non_wakeup_gpios & gpio_bit) {
639 dev_err(bank->dev, 623 dev_err(bank->dev,
640 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); 624 "Unable to modify wakeup on non-wakeup GPIO%d\n",
625 offset);
641 return -EINVAL; 626 return -EINVAL;
642 } 627 }
643 628
@@ -653,22 +638,22 @@ static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
653 return 0; 638 return 0;
654} 639}
655 640
656static void omap_reset_gpio(struct gpio_bank *bank, int gpio) 641static void omap_reset_gpio(struct gpio_bank *bank, unsigned offset)
657{ 642{
658 omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); 643 omap_set_gpio_direction(bank, offset, 1);
659 omap_set_gpio_irqenable(bank, gpio, 0); 644 omap_set_gpio_irqenable(bank, offset, 0);
660 omap_clear_gpio_irqstatus(bank, gpio); 645 omap_clear_gpio_irqstatus(bank, offset);
661 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); 646 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
662 omap_clear_gpio_debounce(bank, gpio); 647 omap_clear_gpio_debounce(bank, offset);
663} 648}
664 649
665/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 650/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
666static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) 651static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
667{ 652{
668 struct gpio_bank *bank = omap_irq_data_get_bank(d); 653 struct gpio_bank *bank = omap_irq_data_get_bank(d);
669 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); 654 unsigned offset = d->hwirq;
670 655
671 return omap_set_gpio_wakeup(bank, gpio, enable); 656 return omap_set_gpio_wakeup(bank, offset, enable);
672} 657}
673 658
674static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 659static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -706,7 +691,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
706 spin_lock_irqsave(&bank->lock, flags); 691 spin_lock_irqsave(&bank->lock, flags);
707 bank->mod_usage &= ~(BIT(offset)); 692 bank->mod_usage &= ~(BIT(offset));
708 omap_disable_gpio_module(bank, offset); 693 omap_disable_gpio_module(bank, offset);
709 omap_reset_gpio(bank, bank->chip.base + offset); 694 omap_reset_gpio(bank, offset);
710 spin_unlock_irqrestore(&bank->lock, flags); 695 spin_unlock_irqrestore(&bank->lock, flags);
711 696
712 /* 697 /*
@@ -803,15 +788,14 @@ exit:
803static unsigned int omap_gpio_irq_startup(struct irq_data *d) 788static unsigned int omap_gpio_irq_startup(struct irq_data *d)
804{ 789{
805 struct gpio_bank *bank = omap_irq_data_get_bank(d); 790 struct gpio_bank *bank = omap_irq_data_get_bank(d);
806 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
807 unsigned long flags; 791 unsigned long flags;
808 unsigned offset = GPIO_INDEX(bank, gpio); 792 unsigned offset = d->hwirq;
809 793
810 if (!BANK_USED(bank)) 794 if (!BANK_USED(bank))
811 pm_runtime_get_sync(bank->dev); 795 pm_runtime_get_sync(bank->dev);
812 796
813 spin_lock_irqsave(&bank->lock, flags); 797 spin_lock_irqsave(&bank->lock, flags);
814 omap_gpio_init_irq(bank, gpio, offset); 798 omap_gpio_init_irq(bank, offset);
815 spin_unlock_irqrestore(&bank->lock, flags); 799 spin_unlock_irqrestore(&bank->lock, flags);
816 omap_gpio_unmask_irq(d); 800 omap_gpio_unmask_irq(d);
817 801
@@ -821,15 +805,13 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
821static void omap_gpio_irq_shutdown(struct irq_data *d) 805static void omap_gpio_irq_shutdown(struct irq_data *d)
822{ 806{
823 struct gpio_bank *bank = omap_irq_data_get_bank(d); 807 struct gpio_bank *bank = omap_irq_data_get_bank(d);
824 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq);
825 unsigned long flags; 808 unsigned long flags;
826 unsigned offset = GPIO_INDEX(bank, gpio); 809 unsigned offset = d->hwirq;
827 810
828 spin_lock_irqsave(&bank->lock, flags); 811 spin_lock_irqsave(&bank->lock, flags);
829 gpiochip_unlock_as_irq(&bank->chip, offset);
830 bank->irq_usage &= ~(BIT(offset)); 812 bank->irq_usage &= ~(BIT(offset));
831 omap_disable_gpio_module(bank, offset); 813 omap_disable_gpio_module(bank, offset);
832 omap_reset_gpio(bank, gpio); 814 omap_reset_gpio(bank, offset);
833 spin_unlock_irqrestore(&bank->lock, flags); 815 spin_unlock_irqrestore(&bank->lock, flags);
834 816
835 /* 817 /*
@@ -843,43 +825,42 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
843static void omap_gpio_ack_irq(struct irq_data *d) 825static void omap_gpio_ack_irq(struct irq_data *d)
844{ 826{
845 struct gpio_bank *bank = omap_irq_data_get_bank(d); 827 struct gpio_bank *bank = omap_irq_data_get_bank(d);
846 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); 828 unsigned offset = d->hwirq;
847 829
848 omap_clear_gpio_irqstatus(bank, gpio); 830 omap_clear_gpio_irqstatus(bank, offset);
849} 831}
850 832
851static void omap_gpio_mask_irq(struct irq_data *d) 833static void omap_gpio_mask_irq(struct irq_data *d)
852{ 834{
853 struct gpio_bank *bank = omap_irq_data_get_bank(d); 835 struct gpio_bank *bank = omap_irq_data_get_bank(d);
854 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); 836 unsigned offset = d->hwirq;
855 unsigned long flags; 837 unsigned long flags;
856 838
857 spin_lock_irqsave(&bank->lock, flags); 839 spin_lock_irqsave(&bank->lock, flags);
858 omap_set_gpio_irqenable(bank, gpio, 0); 840 omap_set_gpio_irqenable(bank, offset, 0);
859 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); 841 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
860 spin_unlock_irqrestore(&bank->lock, flags); 842 spin_unlock_irqrestore(&bank->lock, flags);
861} 843}
862 844
863static void omap_gpio_unmask_irq(struct irq_data *d) 845static void omap_gpio_unmask_irq(struct irq_data *d)
864{ 846{
865 struct gpio_bank *bank = omap_irq_data_get_bank(d); 847 struct gpio_bank *bank = omap_irq_data_get_bank(d);
866 unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); 848 unsigned offset = d->hwirq;
867 unsigned int irq_mask = GPIO_BIT(bank, gpio);
868 u32 trigger = irqd_get_trigger_type(d); 849 u32 trigger = irqd_get_trigger_type(d);
869 unsigned long flags; 850 unsigned long flags;
870 851
871 spin_lock_irqsave(&bank->lock, flags); 852 spin_lock_irqsave(&bank->lock, flags);
872 if (trigger) 853 if (trigger)
873 omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); 854 omap_set_gpio_triggering(bank, offset, trigger);
874 855
875 /* For level-triggered GPIOs, the clearing must be done after 856 /* For level-triggered GPIOs, the clearing must be done after
876 * the HW source is cleared, thus after the handler has run */ 857 * the HW source is cleared, thus after the handler has run */
877 if (bank->level_mask & irq_mask) { 858 if (bank->level_mask & BIT(offset)) {
878 omap_set_gpio_irqenable(bank, gpio, 0); 859 omap_set_gpio_irqenable(bank, offset, 0);
879 omap_clear_gpio_irqstatus(bank, gpio); 860 omap_clear_gpio_irqstatus(bank, offset);
880 } 861 }
881 862
882 omap_set_gpio_irqenable(bank, gpio, 1); 863 omap_set_gpio_irqenable(bank, offset, 1);
883 spin_unlock_irqrestore(&bank->lock, flags); 864 spin_unlock_irqrestore(&bank->lock, flags);
884} 865}
885 866
@@ -977,12 +958,10 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
977static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) 958static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
978{ 959{
979 struct gpio_bank *bank; 960 struct gpio_bank *bank;
980 u32 mask;
981 961
982 bank = container_of(chip, struct gpio_bank, chip); 962 bank = container_of(chip, struct gpio_bank, chip);
983 mask = (BIT(offset));
984 963
985 if (omap_gpio_is_input(bank, mask)) 964 if (omap_gpio_is_input(bank, offset))
986 return omap_get_gpio_datain(bank, offset); 965 return omap_get_gpio_datain(bank, offset);
987 else 966 else
988 return omap_get_gpio_dataout(bank, offset); 967 return omap_get_gpio_dataout(bank, offset);
diff --git a/drivers/gpio/gpio-pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index 236708ad0a5b..945f0cda8529 100644
--- a/drivers/gpio/gpio-pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -88,11 +88,9 @@ struct pcf857x {
88 struct gpio_chip chip; 88 struct gpio_chip chip;
89 struct i2c_client *client; 89 struct i2c_client *client;
90 struct mutex lock; /* protect 'out' */ 90 struct mutex lock; /* protect 'out' */
91 struct irq_domain *irq_domain; /* for irq demux */
92 spinlock_t slock; /* protect irq demux */ 91 spinlock_t slock; /* protect irq demux */
93 unsigned out; /* software latch */ 92 unsigned out; /* software latch */
94 unsigned status; /* current status */ 93 unsigned status; /* current status */
95 unsigned irq_mapped; /* mapped gpio irqs */
96 94
97 int (*write)(struct i2c_client *client, unsigned data); 95 int (*write)(struct i2c_client *client, unsigned data);
98 int (*read)(struct i2c_client *client); 96 int (*read)(struct i2c_client *client);
@@ -182,18 +180,6 @@ static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
182 180
183/*-------------------------------------------------------------------------*/ 181/*-------------------------------------------------------------------------*/
184 182
185static int pcf857x_to_irq(struct gpio_chip *chip, unsigned offset)
186{
187 struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
188 int ret;
189
190 ret = irq_create_mapping(gpio->irq_domain, offset);
191 if (ret > 0)
192 gpio->irq_mapped |= (1 << offset);
193
194 return ret;
195}
196
197static irqreturn_t pcf857x_irq(int irq, void *data) 183static irqreturn_t pcf857x_irq(int irq, void *data)
198{ 184{
199 struct pcf857x *gpio = data; 185 struct pcf857x *gpio = data;
@@ -208,9 +194,9 @@ static irqreturn_t pcf857x_irq(int irq, void *data)
208 * interrupt source, just to avoid bad irqs 194 * interrupt source, just to avoid bad irqs
209 */ 195 */
210 196
211 change = ((gpio->status ^ status) & gpio->irq_mapped); 197 change = (gpio->status ^ status);
212 for_each_set_bit(i, &change, gpio->chip.ngpio) 198 for_each_set_bit(i, &change, gpio->chip.ngpio)
213 generic_handle_irq(irq_find_mapping(gpio->irq_domain, i)); 199 handle_nested_irq(irq_find_mapping(gpio->chip.irqdomain, i));
214 gpio->status = status; 200 gpio->status = status;
215 201
216 spin_unlock_irqrestore(&gpio->slock, flags); 202 spin_unlock_irqrestore(&gpio->slock, flags);
@@ -218,66 +204,36 @@ static irqreturn_t pcf857x_irq(int irq, void *data)
218 return IRQ_HANDLED; 204 return IRQ_HANDLED;
219} 205}
220 206
221static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int irq, 207/*
222 irq_hw_number_t hw) 208 * NOP functions
223{ 209 */
224 struct pcf857x *gpio = domain->host_data; 210static void noop(struct irq_data *data) { }
225
226 irq_set_chip_and_handler(irq,
227 &dummy_irq_chip,
228 handle_level_irq);
229#ifdef CONFIG_ARM
230 set_irq_flags(irq, IRQF_VALID);
231#else
232 irq_set_noprobe(irq);
233#endif
234 gpio->irq_mapped |= (1 << hw);
235
236 return 0;
237}
238
239static struct irq_domain_ops pcf857x_irq_domain_ops = {
240 .map = pcf857x_irq_domain_map,
241};
242 211
243static void pcf857x_irq_domain_cleanup(struct pcf857x *gpio) 212static unsigned int noop_ret(struct irq_data *data)
244{ 213{
245 if (gpio->irq_domain) 214 return 0;
246 irq_domain_remove(gpio->irq_domain);
247
248} 215}
249 216
250static int pcf857x_irq_domain_init(struct pcf857x *gpio, 217static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
251 struct i2c_client *client)
252{ 218{
253 int status; 219 struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
254
255 gpio->irq_domain = irq_domain_add_linear(client->dev.of_node,
256 gpio->chip.ngpio,
257 &pcf857x_irq_domain_ops,
258 gpio);
259 if (!gpio->irq_domain)
260 goto fail;
261
262 /* enable real irq */
263 status = devm_request_threaded_irq(&client->dev, client->irq,
264 NULL, pcf857x_irq, IRQF_ONESHOT |
265 IRQF_TRIGGER_FALLING | IRQF_SHARED,
266 dev_name(&client->dev), gpio);
267
268 if (status)
269 goto fail;
270
271 /* enable gpio_to_irq() */
272 gpio->chip.to_irq = pcf857x_to_irq;
273 220
221 irq_set_irq_wake(gpio->client->irq, on);
274 return 0; 222 return 0;
275
276fail:
277 pcf857x_irq_domain_cleanup(gpio);
278 return -EINVAL;
279} 223}
280 224
225static struct irq_chip pcf857x_irq_chip = {
226 .name = "pcf857x",
227 .irq_startup = noop_ret,
228 .irq_shutdown = noop,
229 .irq_enable = noop,
230 .irq_disable = noop,
231 .irq_ack = noop,
232 .irq_mask = noop,
233 .irq_unmask = noop,
234 .irq_set_wake = pcf857x_irq_set_wake,
235};
236
281/*-------------------------------------------------------------------------*/ 237/*-------------------------------------------------------------------------*/
282 238
283static int pcf857x_probe(struct i2c_client *client, 239static int pcf857x_probe(struct i2c_client *client,
@@ -314,15 +270,6 @@ static int pcf857x_probe(struct i2c_client *client,
314 gpio->chip.direction_output = pcf857x_output; 270 gpio->chip.direction_output = pcf857x_output;
315 gpio->chip.ngpio = id->driver_data; 271 gpio->chip.ngpio = id->driver_data;
316 272
317 /* enable gpio_to_irq() if platform has settings */
318 if (client->irq) {
319 status = pcf857x_irq_domain_init(gpio, client);
320 if (status < 0) {
321 dev_err(&client->dev, "irq_domain init failed\n");
322 goto fail_irq_domain;
323 }
324 }
325
326 /* NOTE: the OnSemi jlc1562b is also largely compatible with 273 /* NOTE: the OnSemi jlc1562b is also largely compatible with
327 * these parts, notably for output. It has a low-resolution 274 * these parts, notably for output. It has a low-resolution
328 * DAC instead of pin change IRQs; and its inputs can be the 275 * DAC instead of pin change IRQs; and its inputs can be the
@@ -398,6 +345,27 @@ static int pcf857x_probe(struct i2c_client *client,
398 if (status < 0) 345 if (status < 0)
399 goto fail; 346 goto fail;
400 347
348 /* Enable irqchip if we have an interrupt */
349 if (client->irq) {
350 status = gpiochip_irqchip_add(&gpio->chip, &pcf857x_irq_chip,
351 0, handle_level_irq,
352 IRQ_TYPE_NONE);
353 if (status) {
354 dev_err(&client->dev, "cannot add irqchip\n");
355 goto fail_irq;
356 }
357
358 status = devm_request_threaded_irq(&client->dev, client->irq,
359 NULL, pcf857x_irq, IRQF_ONESHOT |
360 IRQF_TRIGGER_FALLING | IRQF_SHARED,
361 dev_name(&client->dev), gpio);
362 if (status)
363 goto fail_irq;
364
365 gpiochip_set_chained_irqchip(&gpio->chip, &pcf857x_irq_chip,
366 client->irq, NULL);
367 }
368
401 /* Let platform code set up the GPIOs and their users. 369 /* Let platform code set up the GPIOs and their users.
402 * Now is the first time anyone could use them. 370 * Now is the first time anyone could use them.
403 */ 371 */
@@ -413,13 +381,12 @@ static int pcf857x_probe(struct i2c_client *client,
413 381
414 return 0; 382 return 0;
415 383
416fail: 384fail_irq:
417 if (client->irq) 385 gpiochip_remove(&gpio->chip);
418 pcf857x_irq_domain_cleanup(gpio);
419 386
420fail_irq_domain: 387fail:
421 dev_dbg(&client->dev, "probe error %d for '%s'\n", 388 dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
422 status, client->name); 389 client->name);
423 390
424 return status; 391 return status;
425} 392}
@@ -441,9 +408,6 @@ static int pcf857x_remove(struct i2c_client *client)
441 } 408 }
442 } 409 }
443 410
444 if (client->irq)
445 pcf857x_irq_domain_cleanup(gpio);
446
447 gpiochip_remove(&gpio->chip); 411 gpiochip_remove(&gpio->chip);
448 return status; 412 return status;
449} 413}
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 2fdb04b6f101..cdbbcf0faf9d 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -59,8 +59,7 @@
59#define GAFR_OFFSET 0x54 59#define GAFR_OFFSET 0x54
60#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 60#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
61 61
62#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : ((n) > 5 ? 0x200 : 0x100) \ 62#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
63 + (((n) % 3) << 2))
64 63
65int pxa_last_gpio; 64int pxa_last_gpio;
66static int irq_base; 65static int irq_base;
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index c49522efa7b3..fd3977465948 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -14,6 +14,7 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/clk.h>
17#include <linux/err.h> 18#include <linux/err.h>
18#include <linux/gpio.h> 19#include <linux/gpio.h>
19#include <linux/init.h> 20#include <linux/init.h>
@@ -37,20 +38,22 @@ struct gpio_rcar_priv {
37 struct platform_device *pdev; 38 struct platform_device *pdev;
38 struct gpio_chip gpio_chip; 39 struct gpio_chip gpio_chip;
39 struct irq_chip irq_chip; 40 struct irq_chip irq_chip;
41 unsigned int irq_parent;
42 struct clk *clk;
40}; 43};
41 44
42#define IOINTSEL 0x00 45#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
43#define INOUTSEL 0x04 46#define INOUTSEL 0x04 /* General Input/Output Switching Register */
44#define OUTDT 0x08 47#define OUTDT 0x08 /* General Output Register */
45#define INDT 0x0c 48#define INDT 0x0c /* General Input Register */
46#define INTDT 0x10 49#define INTDT 0x10 /* Interrupt Display Register */
47#define INTCLR 0x14 50#define INTCLR 0x14 /* Interrupt Clear Register */
48#define INTMSK 0x18 51#define INTMSK 0x18 /* Interrupt Mask Register */
49#define MSKCLR 0x1c 52#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
50#define POSNEG 0x20 53#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
51#define EDGLEVEL 0x24 54#define EDGLEVEL 0x24 /* Edge/level Select Register */
52#define FILONOFF 0x28 55#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
53#define BOTHEDGE 0x4c 56#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
54 57
55#define RCAR_MAX_GPIO_PER_BANK 32 58#define RCAR_MAX_GPIO_PER_BANK 32
56 59
@@ -169,6 +172,25 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
169 return 0; 172 return 0;
170} 173}
171 174
175static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
176{
177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
178 struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv,
179 gpio_chip);
180
181 irq_set_irq_wake(p->irq_parent, on);
182
183 if (!p->clk)
184 return 0;
185
186 if (on)
187 clk_enable(p->clk);
188 else
189 clk_disable(p->clk);
190
191 return 0;
192}
193
172static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 194static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
173{ 195{
174 struct gpio_rcar_priv *p = dev_id; 196 struct gpio_rcar_priv *p = dev_id;
@@ -367,6 +389,12 @@ static int gpio_rcar_probe(struct platform_device *pdev)
367 389
368 platform_set_drvdata(pdev, p); 390 platform_set_drvdata(pdev, p);
369 391
392 p->clk = devm_clk_get(dev, NULL);
393 if (IS_ERR(p->clk)) {
394 dev_warn(dev, "unable to get clock\n");
395 p->clk = NULL;
396 }
397
370 pm_runtime_enable(dev); 398 pm_runtime_enable(dev);
371 pm_runtime_get_sync(dev); 399 pm_runtime_get_sync(dev);
372 400
@@ -404,8 +432,8 @@ static int gpio_rcar_probe(struct platform_device *pdev)
404 irq_chip->irq_mask = gpio_rcar_irq_disable; 432 irq_chip->irq_mask = gpio_rcar_irq_disable;
405 irq_chip->irq_unmask = gpio_rcar_irq_enable; 433 irq_chip->irq_unmask = gpio_rcar_irq_enable;
406 irq_chip->irq_set_type = gpio_rcar_irq_set_type; 434 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
407 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED 435 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
408 | IRQCHIP_MASK_ON_SUSPEND; 436 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
409 437
410 ret = gpiochip_add(gpio_chip); 438 ret = gpiochip_add(gpio_chip);
411 if (ret) { 439 if (ret) {
@@ -413,13 +441,14 @@ static int gpio_rcar_probe(struct platform_device *pdev)
413 goto err0; 441 goto err0;
414 } 442 }
415 443
416 ret = gpiochip_irqchip_add(&p->gpio_chip, irq_chip, p->config.irq_base, 444 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, p->config.irq_base,
417 handle_level_irq, IRQ_TYPE_NONE); 445 handle_level_irq, IRQ_TYPE_NONE);
418 if (ret) { 446 if (ret) {
419 dev_err(dev, "cannot add irqchip\n"); 447 dev_err(dev, "cannot add irqchip\n");
420 goto err1; 448 goto err1;
421 } 449 }
422 450
451 p->irq_parent = irq->start;
423 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, 452 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
424 IRQF_SHARED, name, p)) { 453 IRQF_SHARED, name, p)) {
425 dev_err(dev, "failed to request IRQ\n"); 454 dev_err(dev, "failed to request IRQ\n");
@@ -431,7 +460,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
431 460
432 /* warn in case of mismatch if irq base is specified */ 461 /* warn in case of mismatch if irq base is specified */
433 if (p->config.irq_base) { 462 if (p->config.irq_base) {
434 ret = irq_find_mapping(p->gpio_chip.irqdomain, 0); 463 ret = irq_find_mapping(gpio_chip->irqdomain, 0);
435 if (p->config.irq_base != ret) 464 if (p->config.irq_base != ret)
436 dev_warn(dev, "irq base mismatch (%u/%u)\n", 465 dev_warn(dev, "irq base mismatch (%u/%u)\n",
437 p->config.irq_base, ret); 466 p->config.irq_base, ret);
@@ -447,7 +476,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
447 return 0; 476 return 0;
448 477
449err1: 478err1:
450 gpiochip_remove(&p->gpio_chip); 479 gpiochip_remove(gpio_chip);
451err0: 480err0:
452 pm_runtime_put(dev); 481 pm_runtime_put(dev);
453 pm_runtime_disable(dev); 482 pm_runtime_disable(dev);
diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
index 62ab9f4b2cd3..46b89614aa91 100644
--- a/drivers/gpio/gpio-tb10x.c
+++ b/drivers/gpio/gpio-tb10x.c
@@ -283,7 +283,7 @@ fail_ioremap:
283 return ret; 283 return ret;
284} 284}
285 285
286static int __exit tb10x_gpio_remove(struct platform_device *pdev) 286static int tb10x_gpio_remove(struct platform_device *pdev)
287{ 287{
288 struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev); 288 struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
289 289
diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index 971c73964ef1..7bd9f209ffa8 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -244,16 +244,16 @@ static int vf610_gpio_probe(struct platform_device *pdev)
244 gc = &port->gc; 244 gc = &port->gc;
245 gc->of_node = np; 245 gc->of_node = np;
246 gc->dev = dev; 246 gc->dev = dev;
247 gc->label = "vf610-gpio", 247 gc->label = "vf610-gpio";
248 gc->ngpio = VF610_GPIO_PER_PORT, 248 gc->ngpio = VF610_GPIO_PER_PORT;
249 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; 249 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
250 250
251 gc->request = vf610_gpio_request, 251 gc->request = vf610_gpio_request;
252 gc->free = vf610_gpio_free, 252 gc->free = vf610_gpio_free;
253 gc->direction_input = vf610_gpio_direction_input, 253 gc->direction_input = vf610_gpio_direction_input;
254 gc->get = vf610_gpio_get, 254 gc->get = vf610_gpio_get;
255 gc->direction_output = vf610_gpio_direction_output, 255 gc->direction_output = vf610_gpio_direction_output;
256 gc->set = vf610_gpio_set, 256 gc->set = vf610_gpio_set;
257 257
258 ret = gpiochip_add(gc); 258 ret = gpiochip_add(gc);
259 if (ret < 0) 259 if (ret < 0)
diff --git a/drivers/gpio/gpio-xgene-sb.c b/drivers/gpio/gpio-xgene-sb.c
index b6a15c39293e..fb9d29a5d584 100644
--- a/drivers/gpio/gpio-xgene-sb.c
+++ b/drivers/gpio/gpio-xgene-sb.c
@@ -93,7 +93,7 @@ static int xgene_gpio_sb_probe(struct platform_device *pdev)
93 93
94 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 94 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
95 regs = devm_ioremap_resource(&pdev->dev, res); 95 regs = devm_ioremap_resource(&pdev->dev, res);
96 if (!regs) 96 if (IS_ERR(regs))
97 return PTR_ERR(regs); 97 return PTR_ERR(regs);
98 98
99 ret = bgpio_init(&priv->bgc, &pdev->dev, 4, 99 ret = bgpio_init(&priv->bgc, &pdev->dev, 4,
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
index df990f29757a..d2303d50f561 100644
--- a/drivers/gpio/gpiolib-acpi.c
+++ b/drivers/gpio/gpiolib-acpi.c
@@ -304,7 +304,7 @@ void acpi_gpiochip_request_interrupts(struct gpio_chip *chip)
304 return; 304 return;
305 305
306 INIT_LIST_HEAD(&acpi_gpio->events); 306 INIT_LIST_HEAD(&acpi_gpio->events);
307 acpi_walk_resources(ACPI_HANDLE(chip->dev), "_AEI", 307 acpi_walk_resources(handle, "_AEI",
308 acpi_gpiochip_request_interrupt, acpi_gpio); 308 acpi_gpiochip_request_interrupt, acpi_gpio);
309} 309}
310 310
@@ -722,3 +722,87 @@ void acpi_gpiochip_remove(struct gpio_chip *chip)
722 acpi_detach_data(handle, acpi_gpio_chip_dh); 722 acpi_detach_data(handle, acpi_gpio_chip_dh);
723 kfree(acpi_gpio); 723 kfree(acpi_gpio);
724} 724}
725
726static unsigned int acpi_gpio_package_count(const union acpi_object *obj)
727{
728 const union acpi_object *element = obj->package.elements;
729 const union acpi_object *end = element + obj->package.count;
730 unsigned int count = 0;
731
732 while (element < end) {
733 if (element->type == ACPI_TYPE_LOCAL_REFERENCE)
734 count++;
735
736 element++;
737 }
738 return count;
739}
740
741static int acpi_find_gpio_count(struct acpi_resource *ares, void *data)
742{
743 unsigned int *count = data;
744
745 if (ares->type == ACPI_RESOURCE_TYPE_GPIO)
746 *count += ares->data.gpio.pin_table_length;
747
748 return 1;
749}
750
751/**
752 * acpi_gpio_count - return the number of GPIOs associated with a
753 * device / function or -ENOENT if no GPIO has been
754 * assigned to the requested function.
755 * @dev: GPIO consumer, can be NULL for system-global GPIOs
756 * @con_id: function within the GPIO consumer
757 */
758int acpi_gpio_count(struct device *dev, const char *con_id)
759{
760 struct acpi_device *adev = ACPI_COMPANION(dev);
761 const union acpi_object *obj;
762 const struct acpi_gpio_mapping *gm;
763 int count = -ENOENT;
764 int ret;
765 char propname[32];
766 unsigned int i;
767
768 /* Try first from _DSD */
769 for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
770 if (con_id && strcmp(con_id, "gpios"))
771 snprintf(propname, sizeof(propname), "%s-%s",
772 con_id, gpio_suffixes[i]);
773 else
774 snprintf(propname, sizeof(propname), "%s",
775 gpio_suffixes[i]);
776
777 ret = acpi_dev_get_property(adev, propname, ACPI_TYPE_ANY,
778 &obj);
779 if (ret == 0) {
780 if (obj->type == ACPI_TYPE_LOCAL_REFERENCE)
781 count = 1;
782 else if (obj->type == ACPI_TYPE_PACKAGE)
783 count = acpi_gpio_package_count(obj);
784 } else if (adev->driver_gpios) {
785 for (gm = adev->driver_gpios; gm->name; gm++)
786 if (strcmp(propname, gm->name) == 0) {
787 count = gm->size;
788 break;
789 }
790 }
791 if (count >= 0)
792 break;
793 }
794
795 /* Then from plain _CRS GPIOs */
796 if (count < 0) {
797 struct list_head resource_list;
798 unsigned int crs_count = 0;
799
800 INIT_LIST_HEAD(&resource_list);
801 acpi_dev_get_resources(adev, &resource_list,
802 acpi_find_gpio_count, &crs_count);
803 acpi_dev_free_resource_list(&resource_list);
804 if (crs_count > 0)
805 count = crs_count;
806 }
807 return count;
808}
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 4650bf830d6b..a6c67c6b4680 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -22,6 +22,7 @@
22#include <linux/of_gpio.h> 22#include <linux/of_gpio.h>
23#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinctrl.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25#include <linux/gpio/machine.h>
25 26
26#include "gpiolib.h" 27#include "gpiolib.h"
27 28
@@ -118,6 +119,114 @@ int of_get_named_gpio_flags(struct device_node *np, const char *list_name,
118EXPORT_SYMBOL(of_get_named_gpio_flags); 119EXPORT_SYMBOL(of_get_named_gpio_flags);
119 120
120/** 121/**
122 * of_get_gpio_hog() - Get a GPIO hog descriptor, names and flags for GPIO API
123 * @np: device node to get GPIO from
124 * @name: GPIO line name
125 * @lflags: gpio_lookup_flags - returned from of_find_gpio() or
126 * of_get_gpio_hog()
127 * @dflags: gpiod_flags - optional GPIO initialization flags
128 *
129 * Returns GPIO descriptor to use with Linux GPIO API, or one of the errno
130 * value on the error condition.
131 */
132static struct gpio_desc *of_get_gpio_hog(struct device_node *np,
133 const char **name,
134 enum gpio_lookup_flags *lflags,
135 enum gpiod_flags *dflags)
136{
137 struct device_node *chip_np;
138 enum of_gpio_flags xlate_flags;
139 struct gpio_desc *desc;
140 struct gg_data gg_data = {
141 .flags = &xlate_flags,
142 };
143 u32 tmp;
144 int i, ret;
145
146 chip_np = np->parent;
147 if (!chip_np)
148 return ERR_PTR(-EINVAL);
149
150 xlate_flags = 0;
151 *lflags = 0;
152 *dflags = 0;
153
154 ret = of_property_read_u32(chip_np, "#gpio-cells", &tmp);
155 if (ret)
156 return ERR_PTR(ret);
157
158 if (tmp > MAX_PHANDLE_ARGS)
159 return ERR_PTR(-EINVAL);
160
161 gg_data.gpiospec.args_count = tmp;
162 gg_data.gpiospec.np = chip_np;
163 for (i = 0; i < tmp; i++) {
164 ret = of_property_read_u32_index(np, "gpios", i,
165 &gg_data.gpiospec.args[i]);
166 if (ret)
167 return ERR_PTR(ret);
168 }
169
170 gpiochip_find(&gg_data, of_gpiochip_find_and_xlate);
171 if (!gg_data.out_gpio) {
172 if (np->parent == np)
173 return ERR_PTR(-ENXIO);
174 else
175 return ERR_PTR(-EINVAL);
176 }
177
178 if (xlate_flags & OF_GPIO_ACTIVE_LOW)
179 *lflags |= GPIO_ACTIVE_LOW;
180
181 if (of_property_read_bool(np, "input"))
182 *dflags |= GPIOD_IN;
183 else if (of_property_read_bool(np, "output-low"))
184 *dflags |= GPIOD_OUT_LOW;
185 else if (of_property_read_bool(np, "output-high"))
186 *dflags |= GPIOD_OUT_HIGH;
187 else {
188 pr_warn("GPIO line %d (%s): no hogging state specified, bailing out\n",
189 desc_to_gpio(gg_data.out_gpio), np->name);
190 return ERR_PTR(-EINVAL);
191 }
192
193 if (name && of_property_read_string(np, "line-name", name))
194 *name = np->name;
195
196 desc = gg_data.out_gpio;
197
198 return desc;
199}
200
201/**
202 * of_gpiochip_scan_hogs - Scan gpio-controller and apply GPIO hog as requested
203 * @chip: gpio chip to act on
204 *
205 * This is only used by of_gpiochip_add to request/set GPIO initial
206 * configuration.
207 */
208static void of_gpiochip_scan_hogs(struct gpio_chip *chip)
209{
210 struct gpio_desc *desc = NULL;
211 struct device_node *np;
212 const char *name;
213 enum gpio_lookup_flags lflags;
214 enum gpiod_flags dflags;
215
216 for_each_child_of_node(chip->of_node, np) {
217 if (!of_property_read_bool(np, "gpio-hog"))
218 continue;
219
220 desc = of_get_gpio_hog(np, &name, &lflags, &dflags);
221 if (IS_ERR(desc))
222 continue;
223
224 if (gpiod_hog(desc, name, lflags, dflags))
225 continue;
226 }
227}
228
229/**
121 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags 230 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
122 * @gc: pointer to the gpio_chip structure 231 * @gc: pointer to the gpio_chip structure
123 * @np: device node of the GPIO chip 232 * @np: device node of the GPIO chip
@@ -326,6 +435,8 @@ void of_gpiochip_add(struct gpio_chip *chip)
326 435
327 of_gpiochip_add_pin_range(chip); 436 of_gpiochip_add_pin_range(chip);
328 of_node_get(chip->of_node); 437 of_node_get(chip->of_node);
438
439 of_gpiochip_scan_hogs(chip);
329} 440}
330 441
331void of_gpiochip_remove(struct gpio_chip *chip) 442void of_gpiochip_remove(struct gpio_chip *chip)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 1ca9295b2c10..59eaa23767d8 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -315,6 +315,7 @@ EXPORT_SYMBOL_GPL(gpiochip_add);
315 315
316/* Forward-declaration */ 316/* Forward-declaration */
317static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip); 317static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
318static void gpiochip_free_hogs(struct gpio_chip *chip);
318 319
319/** 320/**
320 * gpiochip_remove() - unregister a gpio_chip 321 * gpiochip_remove() - unregister a gpio_chip
@@ -333,6 +334,7 @@ void gpiochip_remove(struct gpio_chip *chip)
333 334
334 acpi_gpiochip_remove(chip); 335 acpi_gpiochip_remove(chip);
335 gpiochip_remove_pin_ranges(chip); 336 gpiochip_remove_pin_ranges(chip);
337 gpiochip_free_hogs(chip);
336 of_gpiochip_remove(chip); 338 of_gpiochip_remove(chip);
337 339
338 spin_lock_irqsave(&gpio_lock, flags); 340 spin_lock_irqsave(&gpio_lock, flags);
@@ -866,6 +868,7 @@ static bool __gpiod_free(struct gpio_desc *desc)
866 clear_bit(FLAG_REQUESTED, &desc->flags); 868 clear_bit(FLAG_REQUESTED, &desc->flags);
867 clear_bit(FLAG_OPEN_DRAIN, &desc->flags); 869 clear_bit(FLAG_OPEN_DRAIN, &desc->flags);
868 clear_bit(FLAG_OPEN_SOURCE, &desc->flags); 870 clear_bit(FLAG_OPEN_SOURCE, &desc->flags);
871 clear_bit(FLAG_IS_HOGGED, &desc->flags);
869 ret = true; 872 ret = true;
870 } 873 }
871 874
@@ -1659,19 +1662,18 @@ static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
1659 unsigned int idx, 1662 unsigned int idx,
1660 enum gpio_lookup_flags *flags) 1663 enum gpio_lookup_flags *flags)
1661{ 1664{
1662 static const char * const suffixes[] = { "gpios", "gpio" };
1663 char prop_name[32]; /* 32 is max size of property name */ 1665 char prop_name[32]; /* 32 is max size of property name */
1664 enum of_gpio_flags of_flags; 1666 enum of_gpio_flags of_flags;
1665 struct gpio_desc *desc; 1667 struct gpio_desc *desc;
1666 unsigned int i; 1668 unsigned int i;
1667 1669
1668 for (i = 0; i < ARRAY_SIZE(suffixes); i++) { 1670 for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
1669 if (con_id) 1671 if (con_id)
1670 snprintf(prop_name, sizeof(prop_name), "%s-%s", con_id, 1672 snprintf(prop_name, sizeof(prop_name), "%s-%s", con_id,
1671 suffixes[i]); 1673 gpio_suffixes[i]);
1672 else 1674 else
1673 snprintf(prop_name, sizeof(prop_name), "%s", 1675 snprintf(prop_name, sizeof(prop_name), "%s",
1674 suffixes[i]); 1676 gpio_suffixes[i]);
1675 1677
1676 desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx, 1678 desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
1677 &of_flags); 1679 &of_flags);
@@ -1692,7 +1694,6 @@ static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id,
1692 unsigned int idx, 1694 unsigned int idx,
1693 enum gpio_lookup_flags *flags) 1695 enum gpio_lookup_flags *flags)
1694{ 1696{
1695 static const char * const suffixes[] = { "gpios", "gpio" };
1696 struct acpi_device *adev = ACPI_COMPANION(dev); 1697 struct acpi_device *adev = ACPI_COMPANION(dev);
1697 struct acpi_gpio_info info; 1698 struct acpi_gpio_info info;
1698 struct gpio_desc *desc; 1699 struct gpio_desc *desc;
@@ -1700,13 +1701,13 @@ static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id,
1700 int i; 1701 int i;
1701 1702
1702 /* Try first from _DSD */ 1703 /* Try first from _DSD */
1703 for (i = 0; i < ARRAY_SIZE(suffixes); i++) { 1704 for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
1704 if (con_id && strcmp(con_id, "gpios")) { 1705 if (con_id && strcmp(con_id, "gpios")) {
1705 snprintf(propname, sizeof(propname), "%s-%s", 1706 snprintf(propname, sizeof(propname), "%s-%s",
1706 con_id, suffixes[i]); 1707 con_id, gpio_suffixes[i]);
1707 } else { 1708 } else {
1708 snprintf(propname, sizeof(propname), "%s", 1709 snprintf(propname, sizeof(propname), "%s",
1709 suffixes[i]); 1710 gpio_suffixes[i]);
1710 } 1711 }
1711 1712
1712 desc = acpi_get_gpiod_by_index(adev, propname, idx, &info); 1713 desc = acpi_get_gpiod_by_index(adev, propname, idx, &info);
@@ -1805,6 +1806,70 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
1805 return desc; 1806 return desc;
1806} 1807}
1807 1808
1809static int dt_gpio_count(struct device *dev, const char *con_id)
1810{
1811 int ret;
1812 char propname[32];
1813 unsigned int i;
1814
1815 for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
1816 if (con_id)
1817 snprintf(propname, sizeof(propname), "%s-%s",
1818 con_id, gpio_suffixes[i]);
1819 else
1820 snprintf(propname, sizeof(propname), "%s",
1821 gpio_suffixes[i]);
1822
1823 ret = of_gpio_named_count(dev->of_node, propname);
1824 if (ret >= 0)
1825 break;
1826 }
1827 return ret;
1828}
1829
1830static int platform_gpio_count(struct device *dev, const char *con_id)
1831{
1832 struct gpiod_lookup_table *table;
1833 struct gpiod_lookup *p;
1834 unsigned int count = 0;
1835
1836 table = gpiod_find_lookup_table(dev);
1837 if (!table)
1838 return -ENOENT;
1839
1840 for (p = &table->table[0]; p->chip_label; p++) {
1841 if ((con_id && p->con_id && !strcmp(con_id, p->con_id)) ||
1842 (!con_id && !p->con_id))
1843 count++;
1844 }
1845 if (!count)
1846 return -ENOENT;
1847
1848 return count;
1849}
1850
1851/**
1852 * gpiod_count - return the number of GPIOs associated with a device / function
1853 * or -ENOENT if no GPIO has been assigned to the requested function
1854 * @dev: GPIO consumer, can be NULL for system-global GPIOs
1855 * @con_id: function within the GPIO consumer
1856 */
1857int gpiod_count(struct device *dev, const char *con_id)
1858{
1859 int count = -ENOENT;
1860
1861 if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node)
1862 count = dt_gpio_count(dev, con_id);
1863 else if (IS_ENABLED(CONFIG_ACPI) && dev && ACPI_HANDLE(dev))
1864 count = acpi_gpio_count(dev, con_id);
1865
1866 if (count < 0)
1867 count = platform_gpio_count(dev, con_id);
1868
1869 return count;
1870}
1871EXPORT_SYMBOL_GPL(gpiod_count);
1872
1808/** 1873/**
1809 * gpiod_get - obtain a GPIO for a given GPIO function 1874 * gpiod_get - obtain a GPIO for a given GPIO function
1810 * @dev: GPIO consumer, can be NULL for system-global GPIOs 1875 * @dev: GPIO consumer, can be NULL for system-global GPIOs
@@ -1840,6 +1905,47 @@ struct gpio_desc *__must_check __gpiod_get_optional(struct device *dev,
1840} 1905}
1841EXPORT_SYMBOL_GPL(__gpiod_get_optional); 1906EXPORT_SYMBOL_GPL(__gpiod_get_optional);
1842 1907
1908
1909/**
1910 * gpiod_configure_flags - helper function to configure a given GPIO
1911 * @desc: gpio whose value will be assigned
1912 * @con_id: function within the GPIO consumer
1913 * @lflags: gpio_lookup_flags - returned from of_find_gpio() or
1914 * of_get_gpio_hog()
1915 * @dflags: gpiod_flags - optional GPIO initialization flags
1916 *
1917 * Return 0 on success, -ENOENT if no GPIO has been assigned to the
1918 * requested function and/or index, or another IS_ERR() code if an error
1919 * occurred while trying to acquire the GPIO.
1920 */
1921static int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id,
1922 unsigned long lflags, enum gpiod_flags dflags)
1923{
1924 int status;
1925
1926 if (lflags & GPIO_ACTIVE_LOW)
1927 set_bit(FLAG_ACTIVE_LOW, &desc->flags);
1928 if (lflags & GPIO_OPEN_DRAIN)
1929 set_bit(FLAG_OPEN_DRAIN, &desc->flags);
1930 if (lflags & GPIO_OPEN_SOURCE)
1931 set_bit(FLAG_OPEN_SOURCE, &desc->flags);
1932
1933 /* No particular flag request, return here... */
1934 if (!(dflags & GPIOD_FLAGS_BIT_DIR_SET)) {
1935 pr_debug("no flags found for %s\n", con_id);
1936 return 0;
1937 }
1938
1939 /* Process flags */
1940 if (dflags & GPIOD_FLAGS_BIT_DIR_OUT)
1941 status = gpiod_direction_output(desc,
1942 dflags & GPIOD_FLAGS_BIT_DIR_VAL);
1943 else
1944 status = gpiod_direction_input(desc);
1945
1946 return status;
1947}
1948
1843/** 1949/**
1844 * gpiod_get_index - obtain a GPIO from a multi-index GPIO function 1950 * gpiod_get_index - obtain a GPIO from a multi-index GPIO function
1845 * @dev: GPIO consumer, can be NULL for system-global GPIOs 1951 * @dev: GPIO consumer, can be NULL for system-global GPIOs
@@ -1865,13 +1971,15 @@ struct gpio_desc *__must_check __gpiod_get_index(struct device *dev,
1865 1971
1866 dev_dbg(dev, "GPIO lookup for consumer %s\n", con_id); 1972 dev_dbg(dev, "GPIO lookup for consumer %s\n", con_id);
1867 1973
1868 /* Using device tree? */ 1974 if (dev) {
1869 if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node) { 1975 /* Using device tree? */
1870 dev_dbg(dev, "using device tree for GPIO lookup\n"); 1976 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
1871 desc = of_find_gpio(dev, con_id, idx, &lookupflags); 1977 dev_dbg(dev, "using device tree for GPIO lookup\n");
1872 } else if (IS_ENABLED(CONFIG_ACPI) && dev && ACPI_HANDLE(dev)) { 1978 desc = of_find_gpio(dev, con_id, idx, &lookupflags);
1873 dev_dbg(dev, "using ACPI for GPIO lookup\n"); 1979 } else if (ACPI_COMPANION(dev)) {
1874 desc = acpi_find_gpio(dev, con_id, idx, &lookupflags); 1980 dev_dbg(dev, "using ACPI for GPIO lookup\n");
1981 desc = acpi_find_gpio(dev, con_id, idx, &lookupflags);
1982 }
1875 } 1983 }
1876 1984
1877 /* 1985 /*
@@ -1889,28 +1997,10 @@ struct gpio_desc *__must_check __gpiod_get_index(struct device *dev,
1889 } 1997 }
1890 1998
1891 status = gpiod_request(desc, con_id); 1999 status = gpiod_request(desc, con_id);
1892
1893 if (status < 0) 2000 if (status < 0)
1894 return ERR_PTR(status); 2001 return ERR_PTR(status);
1895 2002
1896 if (lookupflags & GPIO_ACTIVE_LOW) 2003 status = gpiod_configure_flags(desc, con_id, lookupflags, flags);
1897 set_bit(FLAG_ACTIVE_LOW, &desc->flags);
1898 if (lookupflags & GPIO_OPEN_DRAIN)
1899 set_bit(FLAG_OPEN_DRAIN, &desc->flags);
1900 if (lookupflags & GPIO_OPEN_SOURCE)
1901 set_bit(FLAG_OPEN_SOURCE, &desc->flags);
1902
1903 /* No particular flag request, return here... */
1904 if (!(flags & GPIOD_FLAGS_BIT_DIR_SET))
1905 return desc;
1906
1907 /* Process flags */
1908 if (flags & GPIOD_FLAGS_BIT_DIR_OUT)
1909 status = gpiod_direction_output(desc,
1910 flags & GPIOD_FLAGS_BIT_DIR_VAL);
1911 else
1912 status = gpiod_direction_input(desc);
1913
1914 if (status < 0) { 2004 if (status < 0) {
1915 dev_dbg(dev, "setup of GPIO %s failed\n", con_id); 2005 dev_dbg(dev, "setup of GPIO %s failed\n", con_id);
1916 gpiod_put(desc); 2006 gpiod_put(desc);
@@ -2006,6 +2096,132 @@ struct gpio_desc *__must_check __gpiod_get_index_optional(struct device *dev,
2006EXPORT_SYMBOL_GPL(__gpiod_get_index_optional); 2096EXPORT_SYMBOL_GPL(__gpiod_get_index_optional);
2007 2097
2008/** 2098/**
2099 * gpiod_hog - Hog the specified GPIO desc given the provided flags
2100 * @desc: gpio whose value will be assigned
2101 * @name: gpio line name
2102 * @lflags: gpio_lookup_flags - returned from of_find_gpio() or
2103 * of_get_gpio_hog()
2104 * @dflags: gpiod_flags - optional GPIO initialization flags
2105 */
2106int gpiod_hog(struct gpio_desc *desc, const char *name,
2107 unsigned long lflags, enum gpiod_flags dflags)
2108{
2109 struct gpio_chip *chip;
2110 struct gpio_desc *local_desc;
2111 int hwnum;
2112 int status;
2113
2114 chip = gpiod_to_chip(desc);
2115 hwnum = gpio_chip_hwgpio(desc);
2116
2117 local_desc = gpiochip_request_own_desc(chip, hwnum, name);
2118 if (IS_ERR(local_desc)) {
2119 pr_debug("requesting own GPIO %s failed\n", name);
2120 return PTR_ERR(local_desc);
2121 }
2122
2123 status = gpiod_configure_flags(desc, name, lflags, dflags);
2124 if (status < 0) {
2125 pr_debug("setup of GPIO %s failed\n", name);
2126 gpiochip_free_own_desc(desc);
2127 return status;
2128 }
2129
2130 /* Mark GPIO as hogged so it can be identified and removed later */
2131 set_bit(FLAG_IS_HOGGED, &desc->flags);
2132
2133 pr_info("GPIO line %d (%s) hogged as %s%s\n",
2134 desc_to_gpio(desc), name,
2135 (dflags&GPIOD_FLAGS_BIT_DIR_OUT) ? "output" : "input",
2136 (dflags&GPIOD_FLAGS_BIT_DIR_OUT) ?
2137 (dflags&GPIOD_FLAGS_BIT_DIR_VAL) ? "/high" : "/low":"");
2138
2139 return 0;
2140}
2141
2142/**
2143 * gpiochip_free_hogs - Scan gpio-controller chip and release GPIO hog
2144 * @chip: gpio chip to act on
2145 *
2146 * This is only used by of_gpiochip_remove to free hogged gpios
2147 */
2148static void gpiochip_free_hogs(struct gpio_chip *chip)
2149{
2150 int id;
2151
2152 for (id = 0; id < chip->ngpio; id++) {
2153 if (test_bit(FLAG_IS_HOGGED, &chip->desc[id].flags))
2154 gpiochip_free_own_desc(&chip->desc[id]);
2155 }
2156}
2157
2158/**
2159 * gpiod_get_array - obtain multiple GPIOs from a multi-index GPIO function
2160 * @dev: GPIO consumer, can be NULL for system-global GPIOs
2161 * @con_id: function within the GPIO consumer
2162 * @flags: optional GPIO initialization flags
2163 *
2164 * This function acquires all the GPIOs defined under a given function.
2165 *
2166 * Return a struct gpio_descs containing an array of descriptors, -ENOENT if
2167 * no GPIO has been assigned to the requested function, or another IS_ERR()
2168 * code if an error occurred while trying to acquire the GPIOs.
2169 */
2170struct gpio_descs *__must_check gpiod_get_array(struct device *dev,
2171 const char *con_id,
2172 enum gpiod_flags flags)
2173{
2174 struct gpio_desc *desc;
2175 struct gpio_descs *descs;
2176 int count;
2177
2178 count = gpiod_count(dev, con_id);
2179 if (count < 0)
2180 return ERR_PTR(count);
2181
2182 descs = kzalloc(sizeof(*descs) + sizeof(descs->desc[0]) * count,
2183 GFP_KERNEL);
2184 if (!descs)
2185 return ERR_PTR(-ENOMEM);
2186
2187 for (descs->ndescs = 0; descs->ndescs < count; ) {
2188 desc = gpiod_get_index(dev, con_id, descs->ndescs, flags);
2189 if (IS_ERR(desc)) {
2190 gpiod_put_array(descs);
2191 return ERR_CAST(desc);
2192 }
2193 descs->desc[descs->ndescs] = desc;
2194 descs->ndescs++;
2195 }
2196 return descs;
2197}
2198EXPORT_SYMBOL_GPL(gpiod_get_array);
2199
2200/**
2201 * gpiod_get_array_optional - obtain multiple GPIOs from a multi-index GPIO
2202 * function
2203 * @dev: GPIO consumer, can be NULL for system-global GPIOs
2204 * @con_id: function within the GPIO consumer
2205 * @flags: optional GPIO initialization flags
2206 *
2207 * This is equivalent to gpiod_get_array(), except that when no GPIO was
2208 * assigned to the requested function it will return NULL.
2209 */
2210struct gpio_descs *__must_check gpiod_get_array_optional(struct device *dev,
2211 const char *con_id,
2212 enum gpiod_flags flags)
2213{
2214 struct gpio_descs *descs;
2215
2216 descs = gpiod_get_array(dev, con_id, flags);
2217 if (IS_ERR(descs) && (PTR_ERR(descs) == -ENOENT))
2218 return NULL;
2219
2220 return descs;
2221}
2222EXPORT_SYMBOL_GPL(gpiod_get_array_optional);
2223
2224/**
2009 * gpiod_put - dispose of a GPIO descriptor 2225 * gpiod_put - dispose of a GPIO descriptor
2010 * @desc: GPIO descriptor to dispose of 2226 * @desc: GPIO descriptor to dispose of
2011 * 2227 *
@@ -2017,6 +2233,21 @@ void gpiod_put(struct gpio_desc *desc)
2017} 2233}
2018EXPORT_SYMBOL_GPL(gpiod_put); 2234EXPORT_SYMBOL_GPL(gpiod_put);
2019 2235
2236/**
2237 * gpiod_put_array - dispose of multiple GPIO descriptors
2238 * @descs: struct gpio_descs containing an array of descriptors
2239 */
2240void gpiod_put_array(struct gpio_descs *descs)
2241{
2242 unsigned int i;
2243
2244 for (i = 0; i < descs->ndescs; i++)
2245 gpiod_put(descs->desc[i]);
2246
2247 kfree(descs);
2248}
2249EXPORT_SYMBOL_GPL(gpiod_put_array);
2250
2020#ifdef CONFIG_DEBUG_FS 2251#ifdef CONFIG_DEBUG_FS
2021 2252
2022static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) 2253static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
index ab892be26dc2..594b1798c0e7 100644
--- a/drivers/gpio/gpiolib.h
+++ b/drivers/gpio/gpiolib.h
@@ -29,6 +29,9 @@ struct acpi_gpio_info {
29 bool active_low; 29 bool active_low;
30}; 30};
31 31
32/* gpio suffixes used for ACPI and device tree lookup */
33static const char * const gpio_suffixes[] = { "gpios", "gpio" };
34
32#ifdef CONFIG_ACPI 35#ifdef CONFIG_ACPI
33void acpi_gpiochip_add(struct gpio_chip *chip); 36void acpi_gpiochip_add(struct gpio_chip *chip);
34void acpi_gpiochip_remove(struct gpio_chip *chip); 37void acpi_gpiochip_remove(struct gpio_chip *chip);
@@ -39,6 +42,8 @@ void acpi_gpiochip_free_interrupts(struct gpio_chip *chip);
39struct gpio_desc *acpi_get_gpiod_by_index(struct acpi_device *adev, 42struct gpio_desc *acpi_get_gpiod_by_index(struct acpi_device *adev,
40 const char *propname, int index, 43 const char *propname, int index,
41 struct acpi_gpio_info *info); 44 struct acpi_gpio_info *info);
45
46int acpi_gpio_count(struct device *dev, const char *con_id);
42#else 47#else
43static inline void acpi_gpiochip_add(struct gpio_chip *chip) { } 48static inline void acpi_gpiochip_add(struct gpio_chip *chip) { }
44static inline void acpi_gpiochip_remove(struct gpio_chip *chip) { } 49static inline void acpi_gpiochip_remove(struct gpio_chip *chip) { }
@@ -55,6 +60,11 @@ acpi_get_gpiod_by_index(struct acpi_device *adev, const char *propname,
55{ 60{
56 return ERR_PTR(-ENOSYS); 61 return ERR_PTR(-ENOSYS);
57} 62}
63
64static inline int acpi_gpio_count(struct device *dev, const char *con_id)
65{
66 return -ENODEV;
67}
58#endif 68#endif
59 69
60struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np, 70struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
@@ -80,6 +90,7 @@ struct gpio_desc {
80#define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */ 90#define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */
81#define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ 91#define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */
82#define FLAG_SYSFS_DIR 10 /* show sysfs direction attribute */ 92#define FLAG_SYSFS_DIR 10 /* show sysfs direction attribute */
93#define FLAG_IS_HOGGED 11 /* GPIO is hogged */
83 94
84#define ID_SHIFT 16 /* add new flags before this one */ 95#define ID_SHIFT 16 /* add new flags before this one */
85 96
@@ -91,6 +102,8 @@ struct gpio_desc {
91 102
92int gpiod_request(struct gpio_desc *desc, const char *label); 103int gpiod_request(struct gpio_desc *desc, const char *label);
93void gpiod_free(struct gpio_desc *desc); 104void gpiod_free(struct gpio_desc *desc);
105int gpiod_hog(struct gpio_desc *desc, const char *name,
106 unsigned long lflags, enum gpiod_flags dflags);
94 107
95/* 108/*
96 * Return the GPIO number of the passed descriptor relative to its chip 109 * Return the GPIO number of the passed descriptor relative to its chip
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 18:01:51 -0500