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-rw-r--r--drivers/gpio/Kconfig9
-rw-r--r--drivers/gpio/Makefile7
-rw-r--r--drivers/gpio/gpio-davinci.c455
-rw-r--r--drivers/gpio/gpio-ep93xx.c22
-rw-r--r--drivers/gpio/gpio-ks8695.c319
-rw-r--r--drivers/gpio/gpio-lpc32xx.c446
-rw-r--r--drivers/gpio/gpio-nomadik.c3
-rw-r--r--drivers/gpio/gpio-omap.c2
-rw-r--r--drivers/gpio/gpio-pxa.c338
-rw-r--r--drivers/gpio/gpio-sa1100.c63
-rw-r--r--drivers/gpio/gpio-tegra.c23
-rw-r--r--drivers/gpio/gpio-tnetv107x.c205
-rw-r--r--drivers/gpio/gpio-u300.c1190
13 files changed, 2586 insertions, 496 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d539efd96d4b..4caa3d37bbde 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -178,6 +178,15 @@ config GPIO_SCH
178 The Intel Tunnel Creek processor has 5 GPIOs powered by the 178 The Intel Tunnel Creek processor has 5 GPIOs powered by the
179 core power rail and 9 from suspend power supply. 179 core power rail and 9 from suspend power supply.
180 180
181config GPIO_U300
182 bool "ST-Ericsson U300 COH 901 335/571 GPIO"
183 depends on GPIOLIB && ARCH_U300
184 help
185 Say yes here to support GPIO interface on ST-Ericsson U300.
186 The names of the two IP block variants supported are
187 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
188 ports of 8 GPIO pins each.
189
181config GPIO_VX855 190config GPIO_VX855
182 tristate "VIA VX855/VX875 GPIO" 191 tristate "VIA VX855/VX875 GPIO"
183 depends on MFD_SUPPORT && PCI 192 depends on MFD_SUPPORT && PCI
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9588948c96f0..19c5d27b6d2e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,11 +14,14 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
14obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o 14obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
15obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o 15obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
16obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o 16obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
17obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o
17obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o 18obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
18obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o 19obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o
19obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o 20obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o
20obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o 21obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
22obj-$(CONFIG_MACH_KS8695) += gpio-ks8695.o
21obj-$(CONFIG_GPIO_LANGWELL) += gpio-langwell.o 23obj-$(CONFIG_GPIO_LANGWELL) += gpio-langwell.o
24obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
22obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o 25obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
23obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o 26obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
24obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o 27obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
@@ -37,18 +40,20 @@ obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
37obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o 40obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
38obj-$(CONFIG_GPIO_PCH) += gpio-pch.o 41obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
39obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o 42obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
43obj-$(CONFIG_PLAT_PXA) += gpio-pxa.o
40obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o 44obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
41 45
42obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o 46obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
43obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o 47obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o
44obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o 48obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o
45 49obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
46obj-$(CONFIG_GPIO_SCH) += gpio-sch.o 50obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
47obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o 51obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
48obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o 52obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
49obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o 53obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
50obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o 54obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o
51obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o 55obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
56obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o
52obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o 57obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
53obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o 58obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
54obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o 59obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
new file mode 100644
index 000000000000..df0d59570a84
--- /dev/null
+++ b/drivers/gpio/gpio-davinci.c
@@ -0,0 +1,455 @@
1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21struct davinci_gpio_regs {
22 u32 dir;
23 u32 out_data;
24 u32 set_data;
25 u32 clr_data;
26 u32 in_data;
27 u32 set_rising;
28 u32 clr_rising;
29 u32 set_falling;
30 u32 clr_falling;
31 u32 intstat;
32};
33
34#define chip2controller(chip) \
35 container_of(chip, struct davinci_gpio_controller, chip)
36
37static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
38static void __iomem *gpio_base;
39
40static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
41{
42 void __iomem *ptr;
43
44 if (gpio < 32 * 1)
45 ptr = gpio_base + 0x10;
46 else if (gpio < 32 * 2)
47 ptr = gpio_base + 0x38;
48 else if (gpio < 32 * 3)
49 ptr = gpio_base + 0x60;
50 else if (gpio < 32 * 4)
51 ptr = gpio_base + 0x88;
52 else if (gpio < 32 * 5)
53 ptr = gpio_base + 0xb0;
54 else
55 ptr = NULL;
56 return ptr;
57}
58
59static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
60{
61 struct davinci_gpio_regs __iomem *g;
62
63 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
64
65 return g;
66}
67
68static int __init davinci_gpio_irq_setup(void);
69
70/*--------------------------------------------------------------------------*/
71
72/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
73static inline int __davinci_direction(struct gpio_chip *chip,
74 unsigned offset, bool out, int value)
75{
76 struct davinci_gpio_controller *d = chip2controller(chip);
77 struct davinci_gpio_regs __iomem *g = d->regs;
78 unsigned long flags;
79 u32 temp;
80 u32 mask = 1 << offset;
81
82 spin_lock_irqsave(&d->lock, flags);
83 temp = __raw_readl(&g->dir);
84 if (out) {
85 temp &= ~mask;
86 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
87 } else {
88 temp |= mask;
89 }
90 __raw_writel(temp, &g->dir);
91 spin_unlock_irqrestore(&d->lock, flags);
92
93 return 0;
94}
95
96static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
97{
98 return __davinci_direction(chip, offset, false, 0);
99}
100
101static int
102davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
103{
104 return __davinci_direction(chip, offset, true, value);
105}
106
107/*
108 * Read the pin's value (works even if it's set up as output);
109 * returns zero/nonzero.
110 *
111 * Note that changes are synched to the GPIO clock, so reading values back
112 * right after you've set them may give old values.
113 */
114static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct davinci_gpio_controller *d = chip2controller(chip);
117 struct davinci_gpio_regs __iomem *g = d->regs;
118
119 return (1 << offset) & __raw_readl(&g->in_data);
120}
121
122/*
123 * Assuming the pin is muxed as a gpio output, set its output value.
124 */
125static void
126davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127{
128 struct davinci_gpio_controller *d = chip2controller(chip);
129 struct davinci_gpio_regs __iomem *g = d->regs;
130
131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
132}
133
134static int __init davinci_gpio_setup(void)
135{
136 int i, base;
137 unsigned ngpio;
138 struct davinci_soc_info *soc_info = &davinci_soc_info;
139 struct davinci_gpio_regs *regs;
140
141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
142 return 0;
143
144 /*
145 * The gpio banks conceptually expose a segmented bitmap,
146 * and "ngpio" is one more than the largest zero-based
147 * bit index that's valid.
148 */
149 ngpio = soc_info->gpio_num;
150 if (ngpio == 0) {
151 pr_err("GPIO setup: how many GPIOs?\n");
152 return -EINVAL;
153 }
154
155 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
156 ngpio = DAVINCI_N_GPIO;
157
158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
159 if (WARN_ON(!gpio_base))
160 return -ENOMEM;
161
162 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
163 chips[i].chip.label = "DaVinci";
164
165 chips[i].chip.direction_input = davinci_direction_in;
166 chips[i].chip.get = davinci_gpio_get;
167 chips[i].chip.direction_output = davinci_direction_out;
168 chips[i].chip.set = davinci_gpio_set;
169
170 chips[i].chip.base = base;
171 chips[i].chip.ngpio = ngpio - base;
172 if (chips[i].chip.ngpio > 32)
173 chips[i].chip.ngpio = 32;
174
175 spin_lock_init(&chips[i].lock);
176
177 regs = gpio2regs(base);
178 chips[i].regs = regs;
179 chips[i].set_data = &regs->set_data;
180 chips[i].clr_data = &regs->clr_data;
181 chips[i].in_data = &regs->in_data;
182
183 gpiochip_add(&chips[i].chip);
184 }
185
186 soc_info->gpio_ctlrs = chips;
187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
188
189 davinci_gpio_irq_setup();
190 return 0;
191}
192pure_initcall(davinci_gpio_setup);
193
194/*--------------------------------------------------------------------------*/
195/*
196 * We expect irqs will normally be set up as input pins, but they can also be
197 * used as output pins ... which is convenient for testing.
198 *
199 * NOTE: The first few GPIOs also have direct INTC hookups in addition
200 * to their GPIOBNK0 irq, with a bit less overhead.
201 *
202 * All those INTC hookups (direct, plus several IRQ banks) can also
203 * serve as EDMA event triggers.
204 */
205
206static void gpio_irq_disable(struct irq_data *d)
207{
208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
209 u32 mask = (u32) irq_data_get_irq_handler_data(d);
210
211 __raw_writel(mask, &g->clr_falling);
212 __raw_writel(mask, &g->clr_rising);
213}
214
215static void gpio_irq_enable(struct irq_data *d)
216{
217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
218 u32 mask = (u32) irq_data_get_irq_handler_data(d);
219 unsigned status = irqd_get_trigger_type(d);
220
221 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
222 if (!status)
223 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224
225 if (status & IRQ_TYPE_EDGE_FALLING)
226 __raw_writel(mask, &g->set_falling);
227 if (status & IRQ_TYPE_EDGE_RISING)
228 __raw_writel(mask, &g->set_rising);
229}
230
231static int gpio_irq_type(struct irq_data *d, unsigned trigger)
232{
233 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
234 return -EINVAL;
235
236 return 0;
237}
238
239static struct irq_chip gpio_irqchip = {
240 .name = "GPIO",
241 .irq_enable = gpio_irq_enable,
242 .irq_disable = gpio_irq_disable,
243 .irq_set_type = gpio_irq_type,
244 .flags = IRQCHIP_SET_TYPE_MASKED,
245};
246
247static void
248gpio_irq_handler(unsigned irq, struct irq_desc *desc)
249{
250 struct davinci_gpio_regs __iomem *g;
251 u32 mask = 0xffff;
252 struct davinci_gpio_controller *d;
253
254 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
255 g = (struct davinci_gpio_regs __iomem *)d->regs;
256
257 /* we only care about one bank */
258 if (irq & 1)
259 mask <<= 16;
260
261 /* temporarily mask (level sensitive) parent IRQ */
262 desc->irq_data.chip->irq_mask(&desc->irq_data);
263 desc->irq_data.chip->irq_ack(&desc->irq_data);
264 while (1) {
265 u32 status;
266 int n;
267 int res;
268
269 /* ack any irqs */
270 status = __raw_readl(&g->intstat) & mask;
271 if (!status)
272 break;
273 __raw_writel(status, &g->intstat);
274
275 /* now demux them to the right lowlevel handler */
276 n = d->irq_base;
277 if (irq & 1) {
278 n += 16;
279 status >>= 16;
280 }
281
282 while (status) {
283 res = ffs(status);
284 n += res;
285 generic_handle_irq(n - 1);
286 status >>= res;
287 }
288 }
289 desc->irq_data.chip->irq_unmask(&desc->irq_data);
290 /* now it may re-trigger */
291}
292
293static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
294{
295 struct davinci_gpio_controller *d = chip2controller(chip);
296
297 if (d->irq_base >= 0)
298 return d->irq_base + offset;
299 else
300 return -ENODEV;
301}
302
303static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
304{
305 struct davinci_soc_info *soc_info = &davinci_soc_info;
306
307 /* NOTE: we assume for now that only irqs in the first gpio_chip
308 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
309 */
310 if (offset < soc_info->gpio_unbanked)
311 return soc_info->gpio_irq + offset;
312 else
313 return -ENODEV;
314}
315
316static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
317{
318 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
319 u32 mask = (u32) irq_data_get_irq_handler_data(d);
320
321 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
322 return -EINVAL;
323
324 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
325 ? &g->set_falling : &g->clr_falling);
326 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
327 ? &g->set_rising : &g->clr_rising);
328
329 return 0;
330}
331
332/*
333 * NOTE: for suspend/resume, probably best to make a platform_device with
334 * suspend_late/resume_resume calls hooking into results of the set_wake()
335 * calls ... so if no gpios are wakeup events the clock can be disabled,
336 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
337 * (dm6446) can be set appropriately for GPIOV33 pins.
338 */
339
340static int __init davinci_gpio_irq_setup(void)
341{
342 unsigned gpio, irq, bank;
343 struct clk *clk;
344 u32 binten = 0;
345 unsigned ngpio, bank_irq;
346 struct davinci_soc_info *soc_info = &davinci_soc_info;
347 struct davinci_gpio_regs __iomem *g;
348
349 ngpio = soc_info->gpio_num;
350
351 bank_irq = soc_info->gpio_irq;
352 if (bank_irq == 0) {
353 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
354 return -EINVAL;
355 }
356
357 clk = clk_get(NULL, "gpio");
358 if (IS_ERR(clk)) {
359 printk(KERN_ERR "Error %ld getting gpio clock?\n",
360 PTR_ERR(clk));
361 return PTR_ERR(clk);
362 }
363 clk_enable(clk);
364
365 /* Arrange gpio_to_irq() support, handling either direct IRQs or
366 * banked IRQs. Having GPIOs in the first GPIO bank use direct
367 * IRQs, while the others use banked IRQs, would need some setup
368 * tweaks to recognize hardware which can do that.
369 */
370 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
371 chips[bank].chip.to_irq = gpio_to_irq_banked;
372 chips[bank].irq_base = soc_info->gpio_unbanked
373 ? -EINVAL
374 : (soc_info->intc_irq_num + gpio);
375 }
376
377 /*
378 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
379 * controller only handling trigger modes. We currently assume no
380 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
381 */
382 if (soc_info->gpio_unbanked) {
383 static struct irq_chip gpio_irqchip_unbanked;
384
385 /* pass "bank 0" GPIO IRQs to AINTC */
386 chips[0].chip.to_irq = gpio_to_irq_unbanked;
387 binten = BIT(0);
388
389 /* AINTC handles mask/unmask; GPIO handles triggering */
390 irq = bank_irq;
391 gpio_irqchip_unbanked = *irq_get_chip(irq);
392 gpio_irqchip_unbanked.name = "GPIO-AINTC";
393 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
394
395 /* default trigger: both edges */
396 g = gpio2regs(0);
397 __raw_writel(~0, &g->set_falling);
398 __raw_writel(~0, &g->set_rising);
399
400 /* set the direct IRQs up to use that irqchip */
401 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
402 irq_set_chip(irq, &gpio_irqchip_unbanked);
403 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
404 irq_set_chip_data(irq, (__force void *)g);
405 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
406 }
407
408 goto done;
409 }
410
411 /*
412 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
413 * then chain through our own handler.
414 */
415 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
416 gpio < ngpio;
417 bank++, bank_irq++) {
418 unsigned i;
419
420 /* disabled by default, enabled only as needed */
421 g = gpio2regs(gpio);
422 __raw_writel(~0, &g->clr_falling);
423 __raw_writel(~0, &g->clr_rising);
424
425 /* set up all irqs in this bank */
426 irq_set_chained_handler(bank_irq, gpio_irq_handler);
427
428 /*
429 * Each chip handles 32 gpios, and each irq bank consists of 16
430 * gpio irqs. Pass the irq bank's corresponding controller to
431 * the chained irq handler.
432 */
433 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
434
435 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
436 irq_set_chip(irq, &gpio_irqchip);
437 irq_set_chip_data(irq, (__force void *)g);
438 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
439 irq_set_handler(irq, handle_simple_irq);
440 set_irq_flags(irq, IRQF_VALID);
441 }
442
443 binten |= BIT(bank);
444 }
445
446done:
447 /* BINTEN -- per-bank interrupt enable. genirq would also let these
448 * bits be set/cleared dynamically.
449 */
450 __raw_writel(binten, gpio_base + 0x08);
451
452 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
453
454 return 0;
455}
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 72fb9c665320..7aafbb437339 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -23,6 +23,9 @@
23#include <linux/basic_mmio_gpio.h> 23#include <linux/basic_mmio_gpio.h>
24 24
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/gpio-ep93xx.h>
27
28#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
26 29
27struct ep93xx_gpio { 30struct ep93xx_gpio {
28 void __iomem *mmio_base; 31 void __iomem *mmio_base;
@@ -307,6 +310,21 @@ static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
307 return 0; 310 return 0;
308} 311}
309 312
313/*
314 * Map GPIO A0..A7 (0..7) to irq 64..71,
315 * B0..B7 (7..15) to irq 72..79, and
316 * F0..F7 (16..24) to irq 80..87.
317 */
318static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
319{
320 int gpio = chip->base + offset;
321
322 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
323 return -EINVAL;
324
325 return 64 + gpio;
326}
327
310static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev, 328static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
311 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank) 329 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
312{ 330{
@@ -321,8 +339,10 @@ static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
321 bgc->gc.label = bank->label; 339 bgc->gc.label = bank->label;
322 bgc->gc.base = bank->base; 340 bgc->gc.base = bank->base;
323 341
324 if (bank->has_debounce) 342 if (bank->has_debounce) {
325 bgc->gc.set_debounce = ep93xx_gpio_set_debounce; 343 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
344 bgc->gc.to_irq = ep93xx_gpio_to_irq;
345 }
326 346
327 return gpiochip_add(&bgc->gc); 347 return gpiochip_add(&bgc->gc);
328} 348}
diff --git a/drivers/gpio/gpio-ks8695.c b/drivers/gpio/gpio-ks8695.c
new file mode 100644
index 000000000000..a3ac66ea364b
--- /dev/null
+++ b/drivers/gpio/gpio-ks8695.c
@@ -0,0 +1,319 @@
1/*
2 * arch/arm/mach-ks8695/gpio.c
3 *
4 * Copyright (C) 2006 Andrew Victor
5 * Updated to GPIOLIB, Copyright 2008 Simtec Electronics
6 * Daniel Silverstone <dsilvers@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/gpio.h>
22#include <linux/kernel.h>
23#include <linux/mm.h>
24#include <linux/init.h>
25#include <linux/debugfs.h>
26#include <linux/seq_file.h>
27#include <linux/module.h>
28#include <linux/io.h>
29
30#include <mach/hardware.h>
31#include <asm/mach/irq.h>
32
33#include <mach/regs-gpio.h>
34#include <mach/gpio-ks8695.h>
35
36/*
37 * Configure a GPIO line for either GPIO function, or its internal
38 * function (Interrupt, Timer, etc).
39 */
40static void ks8695_gpio_mode(unsigned int pin, short gpio)
41{
42 unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN };
43 unsigned long x, flags;
44
45 if (pin > KS8695_GPIO_5) /* only GPIO 0..5 have internal functions */
46 return;
47
48 local_irq_save(flags);
49
50 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
51 if (gpio) /* GPIO: set bit to 0 */
52 x &= ~enable[pin];
53 else /* Internal function: set bit to 1 */
54 x |= enable[pin];
55 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPC);
56
57 local_irq_restore(flags);
58}
59
60
61static unsigned short gpio_irq[] = { KS8695_IRQ_EXTERN0, KS8695_IRQ_EXTERN1, KS8695_IRQ_EXTERN2, KS8695_IRQ_EXTERN3 };
62
63/*
64 * Configure GPIO pin as external interrupt source.
65 */
66int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
67{
68 unsigned long x, flags;
69
70 if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */
71 return -EINVAL;
72
73 local_irq_save(flags);
74
75 /* set pin as input */
76 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
77 x &= ~IOPM(pin);
78 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
79
80 local_irq_restore(flags);
81
82 /* Set IRQ triggering type */
83 irq_set_irq_type(gpio_irq[pin], type);
84
85 /* enable interrupt mode */
86 ks8695_gpio_mode(pin, 0);
87
88 return 0;
89}
90EXPORT_SYMBOL(ks8695_gpio_interrupt);
91
92
93
94/* .... Generic GPIO interface .............................................. */
95
96/*
97 * Configure the GPIO line as an input.
98 */
99static int ks8695_gpio_direction_input(struct gpio_chip *gc, unsigned int pin)
100{
101 unsigned long x, flags;
102
103 if (pin > KS8695_GPIO_15)
104 return -EINVAL;
105
106 /* set pin to GPIO mode */
107 ks8695_gpio_mode(pin, 1);
108
109 local_irq_save(flags);
110
111 /* set pin as input */
112 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
113 x &= ~IOPM(pin);
114 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
115
116 local_irq_restore(flags);
117
118 return 0;
119}
120
121
122/*
123 * Configure the GPIO line as an output, with default state.
124 */
125static int ks8695_gpio_direction_output(struct gpio_chip *gc,
126 unsigned int pin, int state)
127{
128 unsigned long x, flags;
129
130 if (pin > KS8695_GPIO_15)
131 return -EINVAL;
132
133 /* set pin to GPIO mode */
134 ks8695_gpio_mode(pin, 1);
135
136 local_irq_save(flags);
137
138 /* set line state */
139 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
140 if (state)
141 x |= IOPD(pin);
142 else
143 x &= ~IOPD(pin);
144 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
145
146 /* set pin as output */
147 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
148 x |= IOPM(pin);
149 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
150
151 local_irq_restore(flags);
152
153 return 0;
154}
155
156
157/*
158 * Set the state of an output GPIO line.
159 */
160static void ks8695_gpio_set_value(struct gpio_chip *gc,
161 unsigned int pin, int state)
162{
163 unsigned long x, flags;
164
165 if (pin > KS8695_GPIO_15)
166 return;
167
168 local_irq_save(flags);
169
170 /* set output line state */
171 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
172 if (state)
173 x |= IOPD(pin);
174 else
175 x &= ~IOPD(pin);
176 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
177
178 local_irq_restore(flags);
179}
180
181
182/*
183 * Read the state of a GPIO line.
184 */
185static int ks8695_gpio_get_value(struct gpio_chip *gc, unsigned int pin)
186{
187 unsigned long x;
188
189 if (pin > KS8695_GPIO_15)
190 return -EINVAL;
191
192 x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
193 return (x & IOPD(pin)) != 0;
194}
195
196
197/*
198 * Map GPIO line to IRQ number.
199 */
200static int ks8695_gpio_to_irq(struct gpio_chip *gc, unsigned int pin)
201{
202 if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */
203 return -EINVAL;
204
205 return gpio_irq[pin];
206}
207
208/*
209 * Map IRQ number to GPIO line.
210 */
211int irq_to_gpio(unsigned int irq)
212{
213 if ((irq < KS8695_IRQ_EXTERN0) || (irq > KS8695_IRQ_EXTERN3))
214 return -EINVAL;
215
216 return (irq - KS8695_IRQ_EXTERN0);
217}
218EXPORT_SYMBOL(irq_to_gpio);
219
220/* GPIOLIB interface */
221
222static struct gpio_chip ks8695_gpio_chip = {
223 .label = "KS8695",
224 .direction_input = ks8695_gpio_direction_input,
225 .direction_output = ks8695_gpio_direction_output,
226 .get = ks8695_gpio_get_value,
227 .set = ks8695_gpio_set_value,
228 .to_irq = ks8695_gpio_to_irq,
229 .base = 0,
230 .ngpio = 16,
231 .can_sleep = 0,
232};
233
234/* Register the GPIOs */
235void ks8695_register_gpios(void)
236{
237 if (gpiochip_add(&ks8695_gpio_chip))
238 printk(KERN_ERR "Unable to register core GPIOs\n");
239}
240
241/* .... Debug interface ..................................................... */
242
243#ifdef CONFIG_DEBUG_FS
244
245static int ks8695_gpio_show(struct seq_file *s, void *unused)
246{
247 unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN };
248 unsigned int intmask[] = { IOPC_IOEINT0TM, IOPC_IOEINT1TM, IOPC_IOEINT2TM, IOPC_IOEINT3TM };
249 unsigned long mode, ctrl, data;
250 int i;
251
252 mode = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
253 ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
254 data = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
255
256 seq_printf(s, "Pin\tI/O\tFunction\tState\n\n");
257
258 for (i = KS8695_GPIO_0; i <= KS8695_GPIO_15 ; i++) {
259 seq_printf(s, "%i:\t", i);
260
261 seq_printf(s, "%s\t", (mode & IOPM(i)) ? "Output" : "Input");
262
263 if (i <= KS8695_GPIO_3) {
264 if (ctrl & enable[i]) {
265 seq_printf(s, "EXT%i ", i);
266
267 switch ((ctrl & intmask[i]) >> (4 * i)) {
268 case IOPC_TM_LOW:
269 seq_printf(s, "(Low)"); break;
270 case IOPC_TM_HIGH:
271 seq_printf(s, "(High)"); break;
272 case IOPC_TM_RISING:
273 seq_printf(s, "(Rising)"); break;
274 case IOPC_TM_FALLING:
275 seq_printf(s, "(Falling)"); break;
276 case IOPC_TM_EDGE:
277 seq_printf(s, "(Edges)"); break;
278 }
279 }
280 else
281 seq_printf(s, "GPIO\t");
282 }
283 else if (i <= KS8695_GPIO_5) {
284 if (ctrl & enable[i])
285 seq_printf(s, "TOUT%i\t", i - KS8695_GPIO_4);
286 else
287 seq_printf(s, "GPIO\t");
288 }
289 else
290 seq_printf(s, "GPIO\t");
291
292 seq_printf(s, "\t");
293
294 seq_printf(s, "%i\n", (data & IOPD(i)) ? 1 : 0);
295 }
296 return 0;
297}
298
299static int ks8695_gpio_open(struct inode *inode, struct file *file)
300{
301 return single_open(file, ks8695_gpio_show, NULL);
302}
303
304static const struct file_operations ks8695_gpio_operations = {
305 .open = ks8695_gpio_open,
306 .read = seq_read,
307 .llseek = seq_lseek,
308 .release = single_release,
309};
310
311static int __init ks8695_gpio_debugfs_init(void)
312{
313 /* /sys/kernel/debug/ks8695_gpio */
314 (void) debugfs_create_file("ks8695_gpio", S_IFREG | S_IRUGO, NULL, NULL, &ks8695_gpio_operations);
315 return 0;
316}
317postcore_initcall(ks8695_gpio_debugfs_init);
318
319#endif
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
new file mode 100644
index 000000000000..5b6948081f8f
--- /dev/null
+++ b/drivers/gpio/gpio-lpc32xx.c
@@ -0,0 +1,446 @@
1/*
2 * arch/arm/mach-lpc32xx/gpiolib.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio.h>
24
25#include <mach/hardware.h>
26#include <mach/platform.h>
27#include <mach/gpio-lpc32xx.h>
28
29#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
30#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
31#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
32#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
33#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
34#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
35#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
36#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
37#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
38#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
39#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
40#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
41#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
42#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
43#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
44#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
45#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
46#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
47#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
48#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
49#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
50#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
51#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
52#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
53#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
54#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
55#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
56
57#define GPIO012_PIN_TO_BIT(x) (1 << (x))
58#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
59#define GPO3_PIN_TO_BIT(x) (1 << (x))
60#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
61#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
62#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y))
63#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
64#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65
66struct gpio_regs {
67 void __iomem *inp_state;
68 void __iomem *outp_set;
69 void __iomem *outp_clr;
70 void __iomem *dir_set;
71 void __iomem *dir_clr;
72};
73
74/*
75 * GPIO names
76 */
77static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
78 "p0.0", "p0.1", "p0.2", "p0.3",
79 "p0.4", "p0.5", "p0.6", "p0.7"
80};
81
82static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
83 "p1.0", "p1.1", "p1.2", "p1.3",
84 "p1.4", "p1.5", "p1.6", "p1.7",
85 "p1.8", "p1.9", "p1.10", "p1.11",
86 "p1.12", "p1.13", "p1.14", "p1.15",
87 "p1.16", "p1.17", "p1.18", "p1.19",
88 "p1.20", "p1.21", "p1.22", "p1.23",
89};
90
91static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
92 "p2.0", "p2.1", "p2.2", "p2.3",
93 "p2.4", "p2.5", "p2.6", "p2.7",
94 "p2.8", "p2.9", "p2.10", "p2.11",
95 "p2.12"
96};
97
98static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
99 "gpi000", "gpio01", "gpio02", "gpio03",
100 "gpio04", "gpio05"
101};
102
103static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
104 "gpi00", "gpi01", "gpi02", "gpi03",
105 "gpi04", "gpi05", "gpi06", "gpi07",
106 "gpi08", "gpi09", NULL, NULL,
107 NULL, NULL, NULL, "gpi15",
108 "gpi16", "gpi17", "gpi18", "gpi19",
109 "gpi20", "gpi21", "gpi22", "gpi23",
110 "gpi24", "gpi25", "gpi26", "gpi27"
111};
112
113static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
114 "gpo00", "gpo01", "gpo02", "gpo03",
115 "gpo04", "gpo05", "gpo06", "gpo07",
116 "gpo08", "gpo09", "gpo10", "gpo11",
117 "gpo12", "gpo13", "gpo14", "gpo15",
118 "gpo16", "gpo17", "gpo18", "gpo19",
119 "gpo20", "gpo21", "gpo22", "gpo23"
120};
121
122static struct gpio_regs gpio_grp_regs_p0 = {
123 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
124 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
125 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
126 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
127 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
128};
129
130static struct gpio_regs gpio_grp_regs_p1 = {
131 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
132 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
133 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
134 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
135 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
136};
137
138static struct gpio_regs gpio_grp_regs_p2 = {
139 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
140 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
141 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
142 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
143 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
144};
145
146static struct gpio_regs gpio_grp_regs_p3 = {
147 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
148 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
149 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
150 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
151 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
152};
153
154struct lpc32xx_gpio_chip {
155 struct gpio_chip chip;
156 struct gpio_regs *gpio_grp;
157};
158
159static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
160 struct gpio_chip *gpc)
161{
162 return container_of(gpc, struct lpc32xx_gpio_chip, chip);
163}
164
165static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
166 unsigned pin, int input)
167{
168 if (input)
169 __raw_writel(GPIO012_PIN_TO_BIT(pin),
170 group->gpio_grp->dir_clr);
171 else
172 __raw_writel(GPIO012_PIN_TO_BIT(pin),
173 group->gpio_grp->dir_set);
174}
175
176static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
177 unsigned pin, int input)
178{
179 u32 u = GPIO3_PIN_TO_BIT(pin);
180
181 if (input)
182 __raw_writel(u, group->gpio_grp->dir_clr);
183 else
184 __raw_writel(u, group->gpio_grp->dir_set);
185}
186
187static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
188 unsigned pin, int high)
189{
190 if (high)
191 __raw_writel(GPIO012_PIN_TO_BIT(pin),
192 group->gpio_grp->outp_set);
193 else
194 __raw_writel(GPIO012_PIN_TO_BIT(pin),
195 group->gpio_grp->outp_clr);
196}
197
198static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
199 unsigned pin, int high)
200{
201 u32 u = GPIO3_PIN_TO_BIT(pin);
202
203 if (high)
204 __raw_writel(u, group->gpio_grp->outp_set);
205 else
206 __raw_writel(u, group->gpio_grp->outp_clr);
207}
208
209static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
210 unsigned pin, int high)
211{
212 if (high)
213 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
214 else
215 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
216}
217
218static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
219 unsigned pin)
220{
221 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
222 pin);
223}
224
225static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
226 unsigned pin)
227{
228 int state = __raw_readl(group->gpio_grp->inp_state);
229
230 /*
231 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
232 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
233 */
234 return GPIO3_PIN_IN_SEL(state, pin);
235}
236
237static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
238 unsigned pin)
239{
240 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
241}
242
243/*
244 * GENERIC_GPIO primitives.
245 */
246static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
247 unsigned pin)
248{
249 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
250
251 __set_gpio_dir_p012(group, pin, 1);
252
253 return 0;
254}
255
256static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
257 unsigned pin)
258{
259 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
260
261 __set_gpio_dir_p3(group, pin, 1);
262
263 return 0;
264}
265
266static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
267 unsigned pin)
268{
269 return 0;
270}
271
272static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
273{
274 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
275
276 return __get_gpio_state_p012(group, pin);
277}
278
279static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
280{
281 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
282
283 return __get_gpio_state_p3(group, pin);
284}
285
286static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
287{
288 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
289
290 return __get_gpi_state_p3(group, pin);
291}
292
293static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
294 int value)
295{
296 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
297
298 __set_gpio_dir_p012(group, pin, 0);
299
300 return 0;
301}
302
303static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
304 int value)
305{
306 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
307
308 __set_gpio_dir_p3(group, pin, 0);
309
310 return 0;
311}
312
313static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
314 int value)
315{
316 return 0;
317}
318
319static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
320 int value)
321{
322 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
323
324 __set_gpio_level_p012(group, pin, value);
325}
326
327static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
328 int value)
329{
330 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
331
332 __set_gpio_level_p3(group, pin, value);
333}
334
335static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
336 int value)
337{
338 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
339
340 __set_gpo_level_p3(group, pin, value);
341}
342
343static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
344{
345 if (pin < chip->ngpio)
346 return 0;
347
348 return -EINVAL;
349}
350
351static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
352 {
353 .chip = {
354 .label = "gpio_p0",
355 .direction_input = lpc32xx_gpio_dir_input_p012,
356 .get = lpc32xx_gpio_get_value_p012,
357 .direction_output = lpc32xx_gpio_dir_output_p012,
358 .set = lpc32xx_gpio_set_value_p012,
359 .request = lpc32xx_gpio_request,
360 .base = LPC32XX_GPIO_P0_GRP,
361 .ngpio = LPC32XX_GPIO_P0_MAX,
362 .names = gpio_p0_names,
363 .can_sleep = 0,
364 },
365 .gpio_grp = &gpio_grp_regs_p0,
366 },
367 {
368 .chip = {
369 .label = "gpio_p1",
370 .direction_input = lpc32xx_gpio_dir_input_p012,
371 .get = lpc32xx_gpio_get_value_p012,
372 .direction_output = lpc32xx_gpio_dir_output_p012,
373 .set = lpc32xx_gpio_set_value_p012,
374 .request = lpc32xx_gpio_request,
375 .base = LPC32XX_GPIO_P1_GRP,
376 .ngpio = LPC32XX_GPIO_P1_MAX,
377 .names = gpio_p1_names,
378 .can_sleep = 0,
379 },
380 .gpio_grp = &gpio_grp_regs_p1,
381 },
382 {
383 .chip = {
384 .label = "gpio_p2",
385 .direction_input = lpc32xx_gpio_dir_input_p012,
386 .get = lpc32xx_gpio_get_value_p012,
387 .direction_output = lpc32xx_gpio_dir_output_p012,
388 .set = lpc32xx_gpio_set_value_p012,
389 .request = lpc32xx_gpio_request,
390 .base = LPC32XX_GPIO_P2_GRP,
391 .ngpio = LPC32XX_GPIO_P2_MAX,
392 .names = gpio_p2_names,
393 .can_sleep = 0,
394 },
395 .gpio_grp = &gpio_grp_regs_p2,
396 },
397 {
398 .chip = {
399 .label = "gpio_p3",
400 .direction_input = lpc32xx_gpio_dir_input_p3,
401 .get = lpc32xx_gpio_get_value_p3,
402 .direction_output = lpc32xx_gpio_dir_output_p3,
403 .set = lpc32xx_gpio_set_value_p3,
404 .request = lpc32xx_gpio_request,
405 .base = LPC32XX_GPIO_P3_GRP,
406 .ngpio = LPC32XX_GPIO_P3_MAX,
407 .names = gpio_p3_names,
408 .can_sleep = 0,
409 },
410 .gpio_grp = &gpio_grp_regs_p3,
411 },
412 {
413 .chip = {
414 .label = "gpi_p3",
415 .direction_input = lpc32xx_gpio_dir_in_always,
416 .get = lpc32xx_gpi_get_value,
417 .request = lpc32xx_gpio_request,
418 .base = LPC32XX_GPI_P3_GRP,
419 .ngpio = LPC32XX_GPI_P3_MAX,
420 .names = gpi_p3_names,
421 .can_sleep = 0,
422 },
423 .gpio_grp = &gpio_grp_regs_p3,
424 },
425 {
426 .chip = {
427 .label = "gpo_p3",
428 .direction_output = lpc32xx_gpio_dir_out_always,
429 .set = lpc32xx_gpo_set_value,
430 .request = lpc32xx_gpio_request,
431 .base = LPC32XX_GPO_P3_GRP,
432 .ngpio = LPC32XX_GPO_P3_MAX,
433 .names = gpo_p3_names,
434 .can_sleep = 0,
435 },
436 .gpio_grp = &gpio_grp_regs_p3,
437 },
438};
439
440void __init lpc32xx_gpio_init(void)
441{
442 int i;
443
444 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
445 gpiochip_add(&lpc32xx_gpiochip[i].chip);
446}
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c
index 2c212c732d76..740caed2b278 100644
--- a/drivers/gpio/gpio-nomadik.c
+++ b/drivers/gpio/gpio-nomadik.c
@@ -27,8 +27,9 @@
27#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
28 28
29#include <plat/pincfg.h> 29#include <plat/pincfg.h>
30#include <plat/gpio-nomadik.h>
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <mach/gpio.h> 32#include <asm/gpio.h>
32 33
33/* 34/*
34 * The GPIO module in the Nomadik family of Systems-on-Chip is an 35 * The GPIO module in the Nomadik family of Systems-on-Chip is an
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 0599854e2217..9c27244fd680 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,7 +25,7 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <asm/irq.h> 26#include <asm/irq.h>
27#include <mach/irqs.h> 27#include <mach/irqs.h>
28#include <mach/gpio.h> 28#include <asm/gpio.h>
29#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
30 30
31struct gpio_bank { 31struct gpio_bank {
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
new file mode 100644
index 000000000000..ee137712f9db
--- /dev/null
+++ b/drivers/gpio/gpio-pxa.c
@@ -0,0 +1,338 @@
1/*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/gpio.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19#include <linux/slab.h>
20
21#include <mach/gpio-pxa.h>
22
23int pxa_last_gpio;
24
25struct pxa_gpio_chip {
26 struct gpio_chip chip;
27 void __iomem *regbase;
28 char label[10];
29
30 unsigned long irq_mask;
31 unsigned long irq_edge_rise;
32 unsigned long irq_edge_fall;
33
34#ifdef CONFIG_PM
35 unsigned long saved_gplr;
36 unsigned long saved_gpdr;
37 unsigned long saved_grer;
38 unsigned long saved_gfer;
39#endif
40};
41
42static DEFINE_SPINLOCK(gpio_lock);
43static struct pxa_gpio_chip *pxa_gpio_chips;
44
45#define for_each_gpio_chip(i, c) \
46 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
47
48static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
49{
50 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
51}
52
53static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
54{
55 return &pxa_gpio_chips[gpio_to_bank(gpio)];
56}
57
58static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
59{
60 void __iomem *base = gpio_chip_base(chip);
61 uint32_t value, mask = 1 << offset;
62 unsigned long flags;
63
64 spin_lock_irqsave(&gpio_lock, flags);
65
66 value = __raw_readl(base + GPDR_OFFSET);
67 if (__gpio_is_inverted(chip->base + offset))
68 value |= mask;
69 else
70 value &= ~mask;
71 __raw_writel(value, base + GPDR_OFFSET);
72
73 spin_unlock_irqrestore(&gpio_lock, flags);
74 return 0;
75}
76
77static int pxa_gpio_direction_output(struct gpio_chip *chip,
78 unsigned offset, int value)
79{
80 void __iomem *base = gpio_chip_base(chip);
81 uint32_t tmp, mask = 1 << offset;
82 unsigned long flags;
83
84 __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
85
86 spin_lock_irqsave(&gpio_lock, flags);
87
88 tmp = __raw_readl(base + GPDR_OFFSET);
89 if (__gpio_is_inverted(chip->base + offset))
90 tmp &= ~mask;
91 else
92 tmp |= mask;
93 __raw_writel(tmp, base + GPDR_OFFSET);
94
95 spin_unlock_irqrestore(&gpio_lock, flags);
96 return 0;
97}
98
99static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
100{
101 return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
102}
103
104static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
105{
106 __raw_writel(1 << offset, gpio_chip_base(chip) +
107 (value ? GPSR_OFFSET : GPCR_OFFSET));
108}
109
110static int __init pxa_init_gpio_chip(int gpio_end)
111{
112 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
113 struct pxa_gpio_chip *chips;
114
115 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
116 if (chips == NULL) {
117 pr_err("%s: failed to allocate GPIO chips\n", __func__);
118 return -ENOMEM;
119 }
120
121 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
122 struct gpio_chip *c = &chips[i].chip;
123
124 sprintf(chips[i].label, "gpio-%d", i);
125 chips[i].regbase = GPIO_BANK(i);
126
127 c->base = gpio;
128 c->label = chips[i].label;
129
130 c->direction_input = pxa_gpio_direction_input;
131 c->direction_output = pxa_gpio_direction_output;
132 c->get = pxa_gpio_get;
133 c->set = pxa_gpio_set;
134
135 /* number of GPIOs on last bank may be less than 32 */
136 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
137 gpiochip_add(c);
138 }
139 pxa_gpio_chips = chips;
140 return 0;
141}
142
143/* Update only those GRERx and GFERx edge detection register bits if those
144 * bits are set in c->irq_mask
145 */
146static inline void update_edge_detect(struct pxa_gpio_chip *c)
147{
148 uint32_t grer, gfer;
149
150 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
151 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
152 grer |= c->irq_edge_rise & c->irq_mask;
153 gfer |= c->irq_edge_fall & c->irq_mask;
154 __raw_writel(grer, c->regbase + GRER_OFFSET);
155 __raw_writel(gfer, c->regbase + GFER_OFFSET);
156}
157
158static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
159{
160 struct pxa_gpio_chip *c;
161 int gpio = irq_to_gpio(d->irq);
162 unsigned long gpdr, mask = GPIO_bit(gpio);
163
164 c = gpio_to_pxachip(gpio);
165
166 if (type == IRQ_TYPE_PROBE) {
167 /* Don't mess with enabled GPIOs using preconfigured edges or
168 * GPIOs set to alternate function or to output during probe
169 */
170 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
171 return 0;
172
173 if (__gpio_is_occupied(gpio))
174 return 0;
175
176 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
177 }
178
179 gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
180
181 if (__gpio_is_inverted(gpio))
182 __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET);
183 else
184 __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
185
186 if (type & IRQ_TYPE_EDGE_RISING)
187 c->irq_edge_rise |= mask;
188 else
189 c->irq_edge_rise &= ~mask;
190
191 if (type & IRQ_TYPE_EDGE_FALLING)
192 c->irq_edge_fall |= mask;
193 else
194 c->irq_edge_fall &= ~mask;
195
196 update_edge_detect(c);
197
198 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
199 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
200 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
201 return 0;
202}
203
204static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
205{
206 struct pxa_gpio_chip *c;
207 int loop, gpio, gpio_base, n;
208 unsigned long gedr;
209
210 do {
211 loop = 0;
212 for_each_gpio_chip(gpio, c) {
213 gpio_base = c->chip.base;
214
215 gedr = __raw_readl(c->regbase + GEDR_OFFSET);
216 gedr = gedr & c->irq_mask;
217 __raw_writel(gedr, c->regbase + GEDR_OFFSET);
218
219 n = find_first_bit(&gedr, BITS_PER_LONG);
220 while (n < BITS_PER_LONG) {
221 loop = 1;
222
223 generic_handle_irq(gpio_to_irq(gpio_base + n));
224 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
225 }
226 }
227 } while (loop);
228}
229
230static void pxa_ack_muxed_gpio(struct irq_data *d)
231{
232 int gpio = irq_to_gpio(d->irq);
233 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
234
235 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
236}
237
238static void pxa_mask_muxed_gpio(struct irq_data *d)
239{
240 int gpio = irq_to_gpio(d->irq);
241 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
242 uint32_t grer, gfer;
243
244 c->irq_mask &= ~GPIO_bit(gpio);
245
246 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
247 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
248 __raw_writel(grer, c->regbase + GRER_OFFSET);
249 __raw_writel(gfer, c->regbase + GFER_OFFSET);
250}
251
252static void pxa_unmask_muxed_gpio(struct irq_data *d)
253{
254 int gpio = irq_to_gpio(d->irq);
255 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
256
257 c->irq_mask |= GPIO_bit(gpio);
258 update_edge_detect(c);
259}
260
261static struct irq_chip pxa_muxed_gpio_chip = {
262 .name = "GPIO",
263 .irq_ack = pxa_ack_muxed_gpio,
264 .irq_mask = pxa_mask_muxed_gpio,
265 .irq_unmask = pxa_unmask_muxed_gpio,
266 .irq_set_type = pxa_gpio_irq_type,
267};
268
269void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
270{
271 struct pxa_gpio_chip *c;
272 int gpio, irq;
273
274 pxa_last_gpio = end;
275
276 /* Initialize GPIO chips */
277 pxa_init_gpio_chip(end);
278
279 /* clear all GPIO edge detects */
280 for_each_gpio_chip(gpio, c) {
281 __raw_writel(0, c->regbase + GFER_OFFSET);
282 __raw_writel(0, c->regbase + GRER_OFFSET);
283 __raw_writel(~0,c->regbase + GEDR_OFFSET);
284 }
285
286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
287 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288 handle_edge_irq);
289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290 }
291
292 /* Install handler for GPIO>=2 edge detect interrupts */
293 irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
294 pxa_muxed_gpio_chip.irq_set_wake = fn;
295}
296
297#ifdef CONFIG_PM
298static int pxa_gpio_suspend(void)
299{
300 struct pxa_gpio_chip *c;
301 int gpio;
302
303 for_each_gpio_chip(gpio, c) {
304 c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
305 c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
306 c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
307 c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
308
309 /* Clear GPIO transition detect bits */
310 __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
311 }
312 return 0;
313}
314
315static void pxa_gpio_resume(void)
316{
317 struct pxa_gpio_chip *c;
318 int gpio;
319
320 for_each_gpio_chip(gpio, c) {
321 /* restore level with set/clear */
322 __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
323 __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
324
325 __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
326 __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
327 __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
328 }
329}
330#else
331#define pxa_gpio_suspend NULL
332#define pxa_gpio_resume NULL
333#endif
334
335struct syscore_ops pxa_gpio_syscore_ops = {
336 .suspend = pxa_gpio_suspend,
337 .resume = pxa_gpio_resume,
338};
diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c
new file mode 100644
index 000000000000..b6c1f6d80649
--- /dev/null
+++ b/drivers/gpio/gpio-sa1100.c
@@ -0,0 +1,63 @@
1/*
2 * linux/arch/arm/mach-sa1100/gpio.c
3 *
4 * Generic SA-1100 GPIO handling
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/gpio.h>
11#include <linux/init.h>
12#include <linux/module.h>
13
14#include <mach/hardware.h>
15
16static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
17{
18 return GPLR & GPIO_GPIO(offset);
19}
20
21static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
22{
23 if (value)
24 GPSR = GPIO_GPIO(offset);
25 else
26 GPCR = GPIO_GPIO(offset);
27}
28
29static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
30{
31 unsigned long flags;
32
33 local_irq_save(flags);
34 GPDR &= ~GPIO_GPIO(offset);
35 local_irq_restore(flags);
36 return 0;
37}
38
39static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
40{
41 unsigned long flags;
42
43 local_irq_save(flags);
44 sa1100_gpio_set(chip, offset, value);
45 GPDR |= GPIO_GPIO(offset);
46 local_irq_restore(flags);
47 return 0;
48}
49
50static struct gpio_chip sa1100_gpio_chip = {
51 .label = "gpio",
52 .direction_input = sa1100_direction_input,
53 .direction_output = sa1100_direction_output,
54 .set = sa1100_gpio_set,
55 .get = sa1100_gpio_get,
56 .base = 0,
57 .ngpio = GPIO_MAX + 1,
58};
59
60void __init sa1100_init_gpio(void)
61{
62 gpiochip_add(&sa1100_gpio_chip);
63}
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 747eb40e8afe..6b65207c8106 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -27,6 +27,7 @@
27 27
28#include <asm/mach/irq.h> 28#include <asm/mach/irq.h>
29 29
30#include <mach/gpio-tegra.h>
30#include <mach/iomap.h> 31#include <mach/iomap.h>
31#include <mach/suspend.h> 32#include <mach/suspend.h>
32 33
@@ -134,7 +135,10 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
134 return 0; 135 return 0;
135} 136}
136 137
137 138static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
139{
140 return TEGRA_GPIO_TO_IRQ(offset);
141}
138 142
139static struct gpio_chip tegra_gpio_chip = { 143static struct gpio_chip tegra_gpio_chip = {
140 .label = "tegra-gpio", 144 .label = "tegra-gpio",
@@ -142,6 +146,7 @@ static struct gpio_chip tegra_gpio_chip = {
142 .get = tegra_gpio_get, 146 .get = tegra_gpio_get,
143 .direction_output = tegra_gpio_direction_output, 147 .direction_output = tegra_gpio_direction_output,
144 .set = tegra_gpio_set, 148 .set = tegra_gpio_set,
149 .to_irq = tegra_gpio_to_irq,
145 .base = 0, 150 .base = 0,
146 .ngpio = TEGRA_NR_GPIOS, 151 .ngpio = TEGRA_NR_GPIOS,
147}; 152};
@@ -331,6 +336,7 @@ static struct lock_class_key gpio_lock_class;
331static int __init tegra_gpio_init(void) 336static int __init tegra_gpio_init(void)
332{ 337{
333 struct tegra_gpio_bank *bank; 338 struct tegra_gpio_bank *bank;
339 int gpio;
334 int i; 340 int i;
335 int j; 341 int j;
336 342
@@ -352,14 +358,17 @@ static int __init tegra_gpio_init(void)
352 358
353 gpiochip_add(&tegra_gpio_chip); 359 gpiochip_add(&tegra_gpio_chip);
354 360
355 for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { 361 for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
356 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; 362 int irq = TEGRA_GPIO_TO_IRQ(gpio);
363 /* No validity check; all Tegra GPIOs are valid IRQs */
364
365 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
357 366
358 irq_set_lockdep_class(i, &gpio_lock_class); 367 irq_set_lockdep_class(irq, &gpio_lock_class);
359 irq_set_chip_data(i, bank); 368 irq_set_chip_data(irq, bank);
360 irq_set_chip_and_handler(i, &tegra_gpio_irq_chip, 369 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
361 handle_simple_irq); 370 handle_simple_irq);
362 set_irq_flags(i, IRQF_VALID); 371 set_irq_flags(irq, IRQF_VALID);
363 } 372 }
364 373
365 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { 374 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
diff --git a/drivers/gpio/gpio-tnetv107x.c b/drivers/gpio/gpio-tnetv107x.c
new file mode 100644
index 000000000000..3fa3e2867e19
--- /dev/null
+++ b/drivers/gpio/gpio-tnetv107x.c
@@ -0,0 +1,205 @@
1/*
2 * Texas Instruments TNETV107X GPIO Controller
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18
19#include <mach/common.h>
20#include <mach/tnetv107x.h>
21
22struct tnetv107x_gpio_regs {
23 u32 idver;
24 u32 data_in[3];
25 u32 data_out[3];
26 u32 direction[3];
27 u32 enable[3];
28};
29
30#define gpio_reg_index(gpio) ((gpio) >> 5)
31#define gpio_reg_bit(gpio) BIT((gpio) & 0x1f)
32
33#define gpio_reg_rmw(reg, mask, val) \
34 __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
35
36#define gpio_reg_set_bit(reg, gpio) \
37 gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
38
39#define gpio_reg_clear_bit(reg, gpio) \
40 gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
41
42#define gpio_reg_get_bit(reg, gpio) \
43 (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
44
45#define chip2controller(chip) \
46 container_of(chip, struct davinci_gpio_controller, chip)
47
48#define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
49
50static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
51
52static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
53{
54 struct davinci_gpio_controller *ctlr = chip2controller(chip);
55 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
56 unsigned gpio = chip->base + offset;
57 unsigned long flags;
58
59 spin_lock_irqsave(&ctlr->lock, flags);
60
61 gpio_reg_set_bit(regs->enable, gpio);
62
63 spin_unlock_irqrestore(&ctlr->lock, flags);
64
65 return 0;
66}
67
68static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
69{
70 struct davinci_gpio_controller *ctlr = chip2controller(chip);
71 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
72 unsigned gpio = chip->base + offset;
73 unsigned long flags;
74
75 spin_lock_irqsave(&ctlr->lock, flags);
76
77 gpio_reg_clear_bit(regs->enable, gpio);
78
79 spin_unlock_irqrestore(&ctlr->lock, flags);
80}
81
82static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
83{
84 struct davinci_gpio_controller *ctlr = chip2controller(chip);
85 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
86 unsigned gpio = chip->base + offset;
87 unsigned long flags;
88
89 spin_lock_irqsave(&ctlr->lock, flags);
90
91 gpio_reg_set_bit(regs->direction, gpio);
92
93 spin_unlock_irqrestore(&ctlr->lock, flags);
94
95 return 0;
96}
97
98static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
99 unsigned offset, int value)
100{
101 struct davinci_gpio_controller *ctlr = chip2controller(chip);
102 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
103 unsigned gpio = chip->base + offset;
104 unsigned long flags;
105
106 spin_lock_irqsave(&ctlr->lock, flags);
107
108 if (value)
109 gpio_reg_set_bit(regs->data_out, gpio);
110 else
111 gpio_reg_clear_bit(regs->data_out, gpio);
112
113 gpio_reg_clear_bit(regs->direction, gpio);
114
115 spin_unlock_irqrestore(&ctlr->lock, flags);
116
117 return 0;
118}
119
120static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
121{
122 struct davinci_gpio_controller *ctlr = chip2controller(chip);
123 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
124 unsigned gpio = chip->base + offset;
125 int ret;
126
127 ret = gpio_reg_get_bit(regs->data_in, gpio);
128
129 return ret ? 1 : 0;
130}
131
132static void tnetv107x_gpio_set(struct gpio_chip *chip,
133 unsigned offset, int value)
134{
135 struct davinci_gpio_controller *ctlr = chip2controller(chip);
136 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
137 unsigned gpio = chip->base + offset;
138 unsigned long flags;
139
140 spin_lock_irqsave(&ctlr->lock, flags);
141
142 if (value)
143 gpio_reg_set_bit(regs->data_out, gpio);
144 else
145 gpio_reg_clear_bit(regs->data_out, gpio);
146
147 spin_unlock_irqrestore(&ctlr->lock, flags);
148}
149
150static int __init tnetv107x_gpio_setup(void)
151{
152 int i, base;
153 unsigned ngpio;
154 struct davinci_soc_info *soc_info = &davinci_soc_info;
155 struct tnetv107x_gpio_regs *regs;
156 struct davinci_gpio_controller *ctlr;
157
158 if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
159 return 0;
160
161 ngpio = soc_info->gpio_num;
162 if (ngpio == 0) {
163 pr_err("GPIO setup: how many GPIOs?\n");
164 return -EINVAL;
165 }
166
167 if (WARN_ON(TNETV107X_N_GPIO < ngpio))
168 ngpio = TNETV107X_N_GPIO;
169
170 regs = ioremap(soc_info->gpio_base, SZ_4K);
171 if (WARN_ON(!regs))
172 return -EINVAL;
173
174 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
175 ctlr = &chips[i];
176
177 ctlr->chip.label = "tnetv107x";
178 ctlr->chip.can_sleep = 0;
179 ctlr->chip.base = base;
180 ctlr->chip.ngpio = ngpio - base;
181 if (ctlr->chip.ngpio > 32)
182 ctlr->chip.ngpio = 32;
183
184 ctlr->chip.request = tnetv107x_gpio_request;
185 ctlr->chip.free = tnetv107x_gpio_free;
186 ctlr->chip.direction_input = tnetv107x_gpio_dir_in;
187 ctlr->chip.get = tnetv107x_gpio_get;
188 ctlr->chip.direction_output = tnetv107x_gpio_dir_out;
189 ctlr->chip.set = tnetv107x_gpio_set;
190
191 spin_lock_init(&ctlr->lock);
192
193 ctlr->regs = regs;
194 ctlr->set_data = &regs->data_out[i];
195 ctlr->clr_data = &regs->data_out[i];
196 ctlr->in_data = &regs->data_in[i];
197
198 gpiochip_add(&ctlr->chip);
199 }
200
201 soc_info->gpio_ctlrs = chips;
202 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
203 return 0;
204}
205pure_initcall(tnetv107x_gpio_setup);
diff --git a/drivers/gpio/gpio-u300.c b/drivers/gpio/gpio-u300.c
index 53e8255cb0ba..4035778852b0 100644
--- a/drivers/gpio/gpio-u300.c
+++ b/drivers/gpio/gpio-u300.c
@@ -1,18 +1,17 @@
1/* 1/*
2 * U300 GPIO module. 2 * U300 GPIO module.
3 * 3 *
4 * Copyright (C) 2007-2009 ST-Ericsson AB 4 * Copyright (C) 2007-2011 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
6 * This can driver either of the two basic GPIO cores 6 * This can driver either of the two basic GPIO cores
7 * available in the U300 platforms: 7 * available in the U300 platforms:
8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) 8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
10 * Notice that you also have inline macros in <asm-arch/gpio.h> 10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 * Author: Linus Walleij <linus.walleij@stericsson.com>
12 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
13 *
14 */ 12 */
15#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/irq.h>
16#include <linux/interrupt.h> 15#include <linux/interrupt.h>
17#include <linux/delay.h> 16#include <linux/delay.h>
18#include <linux/errno.h> 17#include <linux/errno.h>
@@ -21,677 +20,898 @@
21#include <linux/err.h> 20#include <linux/err.h>
22#include <linux/platform_device.h> 21#include <linux/platform_device.h>
23#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/list.h>
24#include <linux/slab.h>
25#include <mach/gpio-u300.h>
24 26
25/* Reference to GPIO block clock */ 27/*
26static struct clk *clk; 28 * Bias modes for U300 GPIOs
29 *
30 * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
31 * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
32 * is not controlled by software
33 * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
34 * impedance to VDD)
35 */
36#define GPIO_U300_CONFIG_BIAS_UNKNOWN 0x1000
37#define GPIO_U300_CONFIG_BIAS_FLOAT 0x1001
38#define GPIO_U300_CONFIG_BIAS_PULL_UP 0x1002
27 39
28/* Memory resource */ 40/*
29static struct resource *memres; 41 * Drive modes for U300 GPIOs (output)
30static void __iomem *virtbase; 42 *
31static struct device *gpiodev; 43 * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
44 * low, this is the most typical case and is typically achieved with two
45 * active transistors on the output
46 * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain
47 * (open collector) which means it is usually wired with other output
48 * ports which are then pulled up with an external resistor
49 * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
50 * (open emitter) which is the same as open drain mutatis mutandis but
51 * pulled to ground
52 */
53#define GPIO_U300_CONFIG_DRIVE_PUSH_PULL 0x2000
54#define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN 0x2001
55#define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE 0x2002
56
57/*
58 * Register definitions for COH 901 335 variant
59 */
60#define U300_335_PORT_STRIDE (0x1C)
61/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
62#define U300_335_PXPDIR (0x00)
63#define U300_335_PXPDOR (0x00)
64/* Port X Pin Config Register 32bit (R/W) */
65#define U300_335_PXPCR (0x04)
66/* This register layout is the same in both blocks */
67#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
68#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
69#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
70#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
71#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
72#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
73#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
74/* Port X Interrupt Event Register 32bit (R/W) */
75#define U300_335_PXIEV (0x08)
76/* Port X Interrupt Enable Register 32bit (R/W) */
77#define U300_335_PXIEN (0x0C)
78/* Port X Interrupt Force Register 32bit (R/W) */
79#define U300_335_PXIFR (0x10)
80/* Port X Interrupt Config Register 32bit (R/W) */
81#define U300_335_PXICR (0x14)
82/* This register layout is the same in both blocks */
83#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
84#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
85#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
86#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
87/* Port X Pull-up Enable Register 32bit (R/W) */
88#define U300_335_PXPER (0x18)
89/* This register layout is the same in both blocks */
90#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
91#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
92/* Control Register 32bit (R/W) */
93#define U300_335_CR (0x54)
94#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
95
96/*
97 * Register definitions for COH 901 571 / 3 variant
98 */
99#define U300_571_PORT_STRIDE (0x30)
100/*
101 * Control Register 32bit (R/W)
102 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
103 * gives the number of GPIO pins.
104 * bit 8-2 (mask 0x000001FC) contains the core version ID.
105 */
106#define U300_571_CR (0x00)
107#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
108#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
109/*
110 * These registers have the same layout and function as the corresponding
111 * COH 901 335 registers, just at different offset.
112 */
113#define U300_571_PXPDIR (0x04)
114#define U300_571_PXPDOR (0x08)
115#define U300_571_PXPCR (0x0C)
116#define U300_571_PXPER (0x10)
117#define U300_571_PXIEV (0x14)
118#define U300_571_PXIEN (0x18)
119#define U300_571_PXIFR (0x1C)
120#define U300_571_PXICR (0x20)
121
122/* 8 bits per port, no version has more than 7 ports */
123#define U300_GPIO_PINS_PER_PORT 8
124#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
125
126struct u300_gpio {
127 struct gpio_chip chip;
128 struct list_head port_list;
129 struct clk *clk;
130 struct resource *memres;
131 void __iomem *base;
132 struct device *dev;
133 int irq_base;
134 u32 stride;
135 /* Register offsets */
136 u32 pcr;
137 u32 dor;
138 u32 dir;
139 u32 per;
140 u32 icr;
141 u32 ien;
142 u32 iev;
143};
32 144
33struct u300_gpio_port { 145struct u300_gpio_port {
34 const char *name; 146 struct list_head node;
147 struct u300_gpio *gpio;
148 char name[8];
35 int irq; 149 int irq;
36 int number; 150 int number;
151 u8 toggle_edge_mode;
37}; 152};
38 153
154/*
155 * Macro to expand to read a specific register found in the "gpio"
156 * struct. It requires the struct u300_gpio *gpio variable to exist in
157 * its context. It calculates the port offset from the given pin
158 * offset, muliplies by the port stride and adds the register offset
159 * so it provides a pointer to the desired register.
160 */
161#define U300_PIN_REG(pin, reg) \
162 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
39 163
40static struct u300_gpio_port gpio_ports[] = { 164/*
41 { 165 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
42 .name = "gpio0", 166 * register.
43 .number = 0, 167 */
44 }, 168#define U300_PIN_BIT(pin) \
45 { 169 (1 << (pin & 0x07))
46 .name = "gpio1",
47 .number = 1,
48 },
49 {
50 .name = "gpio2",
51 .number = 2,
52 },
53#ifdef U300_COH901571_3
54 {
55 .name = "gpio3",
56 .number = 3,
57 },
58 {
59 .name = "gpio4",
60 .number = 4,
61 },
62#ifdef CONFIG_MACH_U300_BS335
63 {
64 .name = "gpio5",
65 .number = 5,
66 },
67 {
68 .name = "gpio6",
69 .number = 6,
70 },
71#endif
72#endif
73 170
171struct u300_gpio_confdata {
172 u16 bias_mode;
173 bool output;
174 int outval;
74}; 175};
75 176
177/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
178#define BS335_GPIO_NUM_PORTS 7
179/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
180#define BS365_GPIO_NUM_PORTS 5
76 181
77#ifdef U300_COH901571_3 182#define U300_FLOATING_INPUT { \
183 .bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \
184 .output = false, \
185}
78 186
79/* Default input value */ 187#define U300_PULL_UP_INPUT { \
80#define DEFAULT_OUTPUT_LOW 0 188 .bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \
81#define DEFAULT_OUTPUT_HIGH 1 189 .output = false, \
190}
82 191
83/* GPIO Pull-Up status */ 192#define U300_OUTPUT_LOW { \
84#define DISABLE_PULL_UP 0 193 .output = true, \
85#define ENABLE_PULL_UP 1 194 .outval = 0, \
195}
86 196
87#define GPIO_NOT_USED 0 197#define U300_OUTPUT_HIGH { \
88#define GPIO_IN 1 198 .output = true, \
89#define GPIO_OUT 2 199 .outval = 1, \
200}
90 201
91struct u300_gpio_configuration_data {
92 unsigned char pin_usage;
93 unsigned char default_output_value;
94 unsigned char pull_up;
95};
96 202
97/* Initial configuration */ 203/* Initial configuration */
98const struct u300_gpio_configuration_data 204static const struct __initdata u300_gpio_confdata
99u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 205bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
100#ifdef CONFIG_MACH_U300_BS335
101 /* Port 0, pins 0-7 */ 206 /* Port 0, pins 0-7 */
102 { 207 {
103 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 208 U300_FLOATING_INPUT,
104 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 209 U300_OUTPUT_HIGH,
105 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 210 U300_FLOATING_INPUT,
106 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 211 U300_OUTPUT_LOW,
107 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 212 U300_OUTPUT_LOW,
108 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 213 U300_OUTPUT_LOW,
109 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 214 U300_OUTPUT_LOW,
110 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 215 U300_OUTPUT_LOW,
111 }, 216 },
112 /* Port 1, pins 0-7 */ 217 /* Port 1, pins 0-7 */
113 { 218 {
114 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 219 U300_OUTPUT_LOW,
115 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 220 U300_OUTPUT_LOW,
116 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 221 U300_OUTPUT_LOW,
117 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 222 U300_PULL_UP_INPUT,
118 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 223 U300_FLOATING_INPUT,
119 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 224 U300_OUTPUT_HIGH,
120 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 225 U300_OUTPUT_LOW,
121 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 226 U300_OUTPUT_LOW,
122 }, 227 },
123 /* Port 2, pins 0-7 */ 228 /* Port 2, pins 0-7 */
124 { 229 {
125 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 230 U300_FLOATING_INPUT,
126 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 231 U300_FLOATING_INPUT,
127 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 232 U300_FLOATING_INPUT,
128 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 233 U300_FLOATING_INPUT,
129 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 234 U300_OUTPUT_LOW,
130 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 235 U300_PULL_UP_INPUT,
131 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 236 U300_OUTPUT_LOW,
132 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 237 U300_PULL_UP_INPUT,
133 }, 238 },
134 /* Port 3, pins 0-7 */ 239 /* Port 3, pins 0-7 */
135 { 240 {
136 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 241 U300_PULL_UP_INPUT,
137 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 242 U300_OUTPUT_LOW,
138 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 243 U300_FLOATING_INPUT,
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 244 U300_FLOATING_INPUT,
140 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 245 U300_FLOATING_INPUT,
141 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 246 U300_FLOATING_INPUT,
142 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 247 U300_FLOATING_INPUT,
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 248 U300_FLOATING_INPUT,
144 }, 249 },
145 /* Port 4, pins 0-7 */ 250 /* Port 4, pins 0-7 */
146 { 251 {
147 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 252 U300_FLOATING_INPUT,
148 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 253 U300_FLOATING_INPUT,
149 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 254 U300_FLOATING_INPUT,
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 255 U300_FLOATING_INPUT,
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 256 U300_FLOATING_INPUT,
152 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 257 U300_FLOATING_INPUT,
153 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 258 U300_FLOATING_INPUT,
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 259 U300_FLOATING_INPUT,
155 }, 260 },
156 /* Port 5, pins 0-7 */ 261 /* Port 5, pins 0-7 */
157 { 262 {
158 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 263 U300_FLOATING_INPUT,
159 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 264 U300_FLOATING_INPUT,
160 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 265 U300_FLOATING_INPUT,
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 266 U300_FLOATING_INPUT,
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 267 U300_FLOATING_INPUT,
163 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 268 U300_FLOATING_INPUT,
164 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 269 U300_FLOATING_INPUT,
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 270 U300_FLOATING_INPUT,
166 }, 271 },
167 /* Port 6, pind 0-7 */ 272 /* Port 6, pind 0-7 */
168 { 273 {
169 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 274 U300_FLOATING_INPUT,
170 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 275 U300_FLOATING_INPUT,
171 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 276 U300_FLOATING_INPUT,
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 277 U300_FLOATING_INPUT,
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 278 U300_FLOATING_INPUT,
174 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 279 U300_FLOATING_INPUT,
175 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 280 U300_FLOATING_INPUT,
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 281 U300_FLOATING_INPUT,
177 } 282 }
178#endif 283};
179 284
180#ifdef CONFIG_MACH_U300_BS365 285static const struct __initdata u300_gpio_confdata
286bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
181 /* Port 0, pins 0-7 */ 287 /* Port 0, pins 0-7 */
182 { 288 {
183 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 289 U300_FLOATING_INPUT,
184 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 290 U300_OUTPUT_LOW,
185 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 291 U300_FLOATING_INPUT,
186 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 292 U300_OUTPUT_LOW,
187 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 293 U300_OUTPUT_LOW,
188 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 294 U300_OUTPUT_LOW,
189 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 295 U300_PULL_UP_INPUT,
190 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 296 U300_FLOATING_INPUT,
191 }, 297 },
192 /* Port 1, pins 0-7 */ 298 /* Port 1, pins 0-7 */
193 { 299 {
194 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 300 U300_OUTPUT_LOW,
195 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 301 U300_FLOATING_INPUT,
196 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 302 U300_OUTPUT_LOW,
197 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 303 U300_FLOATING_INPUT,
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 304 U300_FLOATING_INPUT,
199 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 305 U300_OUTPUT_HIGH,
200 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 306 U300_OUTPUT_LOW,
201 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 307 U300_OUTPUT_LOW,
202 }, 308 },
203 /* Port 2, pins 0-7 */ 309 /* Port 2, pins 0-7 */
204 { 310 {
205 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 311 U300_FLOATING_INPUT,
206 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 312 U300_PULL_UP_INPUT,
207 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 313 U300_OUTPUT_LOW,
208 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 314 U300_OUTPUT_LOW,
209 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 315 U300_PULL_UP_INPUT,
210 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 316 U300_PULL_UP_INPUT,
211 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 317 U300_PULL_UP_INPUT,
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 318 U300_PULL_UP_INPUT,
213 }, 319 },
214 /* Port 3, pins 0-7 */ 320 /* Port 3, pins 0-7 */
215 { 321 {
216 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 322 U300_PULL_UP_INPUT,
217 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 323 U300_PULL_UP_INPUT,
218 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 324 U300_PULL_UP_INPUT,
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 325 U300_PULL_UP_INPUT,
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 326 U300_PULL_UP_INPUT,
221 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 327 U300_PULL_UP_INPUT,
222 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 328 U300_PULL_UP_INPUT,
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 329 U300_PULL_UP_INPUT,
224 }, 330 },
225 /* Port 4, pins 0-7 */ 331 /* Port 4, pins 0-7 */
226 { 332 {
227 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 333 U300_PULL_UP_INPUT,
228 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 334 U300_PULL_UP_INPUT,
229 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 335 U300_PULL_UP_INPUT,
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 336 U300_PULL_UP_INPUT,
231 /* These 4 pins doesn't exist on DB3210 */ 337 /* These 4 pins doesn't exist on DB3210 */
232 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 338 U300_OUTPUT_LOW,
233 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 339 U300_OUTPUT_LOW,
234 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 340 U300_OUTPUT_LOW,
235 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 341 U300_OUTPUT_LOW,
236 } 342 }
237#endif
238}; 343};
239#endif
240 344
241 345/**
242/* No users == we can power down GPIO */ 346 * to_u300_gpio() - get the pointer to u300_gpio
243static int gpio_users; 347 * @chip: the gpio chip member of the structure u300_gpio
244
245struct gpio_struct {
246 int (*callback)(void *);
247 void *data;
248 int users;
249};
250
251static struct gpio_struct gpio_pin[U300_GPIO_MAX];
252
253/*
254 * Let drivers register callback in order to get notified when there is
255 * an interrupt on the gpio pin
256 */ 348 */
257int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data) 349static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
258{ 350{
259 if (gpio_pin[gpio].callback) 351 return container_of(chip, struct u300_gpio, chip);
260 dev_warn(gpiodev, "%s: WARNING: callback already "
261 "registered for gpio pin#%d\n", __func__, gpio);
262 gpio_pin[gpio].callback = func;
263 gpio_pin[gpio].data = data;
264
265 return 0;
266} 352}
267EXPORT_SYMBOL(gpio_register_callback);
268 353
269int gpio_unregister_callback(unsigned gpio) 354static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
270{ 355{
271 if (!gpio_pin[gpio].callback) 356 struct u300_gpio *gpio = to_u300_gpio(chip);
272 dev_warn(gpiodev, "%s: WARNING: callback already "
273 "unregistered for gpio pin#%d\n", __func__, gpio);
274 gpio_pin[gpio].callback = NULL;
275 gpio_pin[gpio].data = NULL;
276 357
277 return 0; 358 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
278} 359}
279EXPORT_SYMBOL(gpio_unregister_callback);
280 360
281/* Non-zero means valid */ 361static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
282int gpio_is_valid(int number)
283{ 362{
284 if (number >= 0 && 363 struct u300_gpio *gpio = to_u300_gpio(chip);
285 number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT)) 364 unsigned long flags;
286 return 1; 365 u32 val;
287 return 0;
288}
289EXPORT_SYMBOL(gpio_is_valid);
290 366
291int gpio_request(unsigned gpio, const char *label) 367 local_irq_save(flags);
292{
293 if (gpio_pin[gpio].users)
294 return -EINVAL;
295 else
296 gpio_pin[gpio].users++;
297 368
298 gpio_users++; 369 val = readl(U300_PIN_REG(offset, dor));
370 if (value)
371 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
372 else
373 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
299 374
300 return 0; 375 local_irq_restore(flags);
301} 376}
302EXPORT_SYMBOL(gpio_request);
303 377
304void gpio_free(unsigned gpio) 378static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
305{ 379{
306 gpio_users--; 380 struct u300_gpio *gpio = to_u300_gpio(chip);
307 gpio_pin[gpio].users--; 381 unsigned long flags;
308 if (unlikely(gpio_pin[gpio].users < 0)) { 382 u32 val;
309 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
310 gpio);
311 gpio_pin[gpio].users = 0;
312 }
313
314 return;
315}
316EXPORT_SYMBOL(gpio_free);
317 383
318/* This returns zero or nonzero */ 384 local_irq_save(flags);
319int gpio_get_value(unsigned gpio) 385 val = readl(U300_PIN_REG(offset, pcr));
320{ 386 /* Mask out this pin, note 2 bits per setting */
321 return readl(virtbase + U300_GPIO_PXPDIR + 387 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
322 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07)); 388 writel(val, U300_PIN_REG(offset, pcr));
389 local_irq_restore(flags);
390 return 0;
323} 391}
324EXPORT_SYMBOL(gpio_get_value);
325 392
326/* 393static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
327 * We hope that the compiler will optimize away the unused branch 394 int value)
328 * in case "value" is a constant
329 */
330void gpio_set_value(unsigned gpio, int value)
331{ 395{
332 u32 val; 396 struct u300_gpio *gpio = to_u300_gpio(chip);
333 unsigned long flags; 397 unsigned long flags;
398 u32 oldmode;
399 u32 val;
334 400
335 local_irq_save(flags); 401 local_irq_save(flags);
336 if (value) { 402 val = readl(U300_PIN_REG(offset, pcr));
337 /* set */ 403 /*
338 val = readl(virtbase + U300_GPIO_PXPDOR + 404 * Drive mode must be set by the special mode set function, set
339 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) 405 * push/pull mode by default if no mode has been selected.
340 & (1 << (gpio & 0x07)); 406 */
341 writel(val | (1 << (gpio & 0x07)), virtbase + 407 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
342 U300_GPIO_PXPDOR + 408 ((offset & 0x07) << 1));
343 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); 409 /* mode = 0 means input, else some mode is already set */
344 } else { 410 if (oldmode == 0) {
345 /* clear */ 411 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
346 val = readl(virtbase + U300_GPIO_PXPDOR + 412 ((offset & 0x07) << 1));
347 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) 413 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
348 & (1 << (gpio & 0x07)); 414 << ((offset & 0x07) << 1));
349 writel(val & ~(1 << (gpio & 0x07)), virtbase + 415 writel(val, U300_PIN_REG(offset, pcr));
350 U300_GPIO_PXPDOR +
351 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
352 } 416 }
417 u300_gpio_set(chip, offset, value);
353 local_irq_restore(flags); 418 local_irq_restore(flags);
419 return 0;
354} 420}
355EXPORT_SYMBOL(gpio_set_value);
356 421
357int gpio_direction_input(unsigned gpio) 422static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
358{ 423{
424 struct u300_gpio *gpio = to_u300_gpio(chip);
425 int retirq = gpio->irq_base + offset;
426
427 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
428 retirq);
429 return retirq;
430}
431
432static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
433 u16 param, unsigned long *data)
434{
435 struct u300_gpio *gpio = to_u300_gpio(chip);
359 unsigned long flags; 436 unsigned long flags;
360 u32 val; 437 u32 val;
361 438
362 if (gpio > U300_GPIO_MAX)
363 return -EINVAL;
364
365 local_irq_save(flags); 439 local_irq_save(flags);
366 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 440 switch (param) {
367 U300_GPIO_PORTX_SPACING); 441 case GPIO_U300_CONFIG_BIAS_UNKNOWN:
368 /* Mask out this pin*/ 442 case GPIO_U300_CONFIG_BIAS_FLOAT:
369 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); 443 val = readl(U300_PIN_REG(offset, per));
370 /* This is not needed since it sets the bits to zero.*/ 444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
371 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */ 445 break;
372 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 446 case GPIO_U300_CONFIG_BIAS_PULL_UP:
373 U300_GPIO_PORTX_SPACING); 447 val = readl(U300_PIN_REG(offset, per));
448 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
449 break;
450 case GPIO_U300_CONFIG_DRIVE_PUSH_PULL:
451 val = readl(U300_PIN_REG(offset, pcr));
452 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
453 << ((offset & 0x07) << 1));
454 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
455 << ((offset & 0x07) << 1));
456 writel(val, U300_PIN_REG(offset, pcr));
457 break;
458 case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN:
459 val = readl(U300_PIN_REG(offset, pcr));
460 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
461 << ((offset & 0x07) << 1));
462 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
463 << ((offset & 0x07) << 1));
464 writel(val, U300_PIN_REG(offset, pcr));
465 break;
466 case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE:
467 val = readl(U300_PIN_REG(offset, pcr));
468 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
469 << ((offset & 0x07) << 1));
470 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
471 << ((offset & 0x07) << 1));
472 writel(val, U300_PIN_REG(offset, pcr));
473 break;
474 default:
475 local_irq_restore(flags);
476 dev_err(gpio->dev, "illegal configuration requested\n");
477 return -EINVAL;
478 }
374 local_irq_restore(flags); 479 local_irq_restore(flags);
375 return 0; 480 return 0;
376} 481}
377EXPORT_SYMBOL(gpio_direction_input);
378 482
379int gpio_direction_output(unsigned gpio, int value) 483static struct gpio_chip u300_gpio_chip = {
484 .label = "u300-gpio-chip",
485 .owner = THIS_MODULE,
486 .get = u300_gpio_get,
487 .set = u300_gpio_set,
488 .direction_input = u300_gpio_direction_input,
489 .direction_output = u300_gpio_direction_output,
490 .to_irq = u300_gpio_to_irq,
491};
492
493static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
380{ 494{
381 unsigned long flags;
382 u32 val; 495 u32 val;
383 496
384 if (gpio > U300_GPIO_MAX) 497 val = readl(U300_PIN_REG(offset, icr));
385 return -EINVAL; 498 /* Set mode depending on state */
386 499 if (u300_gpio_get(&gpio->chip, offset)) {
387 local_irq_save(flags); 500 /* High now, let's trigger on falling edge next then */
388 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 501 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
389 U300_GPIO_PORTX_SPACING); 502 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
390 /* Mask out this pin */ 503 offset);
391 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); 504 } else {
392 /* 505 /* Low now, let's trigger on rising edge next then */
393 * FIXME: configure for push/pull, open drain or open source per pin 506 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
394 * in setup. The current driver will only support push/pull. 507 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
395 */ 508 offset);
396 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 509 }
397 << ((gpio & 0x07) << 1));
398 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
399 U300_GPIO_PORTX_SPACING);
400 gpio_set_value(gpio, value);
401 local_irq_restore(flags);
402 return 0;
403} 510}
404EXPORT_SYMBOL(gpio_direction_output);
405 511
406/* 512static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
407 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
408 */
409void enable_irq_on_gpio_pin(unsigned gpio, int edge)
410{ 513{
514 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
515 struct u300_gpio *gpio = port->gpio;
516 int offset = d->irq - gpio->irq_base;
411 u32 val; 517 u32 val;
412 unsigned long flags;
413 local_irq_save(flags);
414 518
415 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 519 if ((trigger & IRQF_TRIGGER_RISING) &&
416 U300_GPIO_PORTX_SPACING); 520 (trigger & IRQF_TRIGGER_FALLING)) {
417 val |= (1 << (gpio & 0x07)); 521 /*
418 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 522 * The GPIO block can only trigger on falling OR rising edges,
419 U300_GPIO_PORTX_SPACING); 523 * not both. So we need to toggle the mode whenever the pin
420 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * 524 * goes from one state to the other with a special state flag
421 U300_GPIO_PORTX_SPACING); 525 */
422 if (edge) 526 dev_dbg(gpio->dev,
423 val |= (1 << (gpio & 0x07)); 527 "trigger on both rising and falling edge on pin %d\n",
424 else 528 offset);
425 val &= ~(1 << (gpio & 0x07)); 529 port->toggle_edge_mode |= U300_PIN_BIT(offset);
426 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * 530 u300_toggle_trigger(gpio, offset);
427 U300_GPIO_PORTX_SPACING); 531 } else if (trigger & IRQF_TRIGGER_RISING) {
428 local_irq_restore(flags); 532 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
533 offset);
534 val = readl(U300_PIN_REG(offset, icr));
535 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
536 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
537 } else if (trigger & IRQF_TRIGGER_FALLING) {
538 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
539 offset);
540 val = readl(U300_PIN_REG(offset, icr));
541 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
542 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
543 }
544
545 return 0;
429} 546}
430EXPORT_SYMBOL(enable_irq_on_gpio_pin);
431 547
432void disable_irq_on_gpio_pin(unsigned gpio) 548static void u300_gpio_irq_enable(struct irq_data *d)
433{ 549{
550 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
551 struct u300_gpio *gpio = port->gpio;
552 int offset = d->irq - gpio->irq_base;
434 u32 val; 553 u32 val;
435 unsigned long flags; 554 unsigned long flags;
436 555
437 local_irq_save(flags); 556 local_irq_save(flags);
438 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 557 val = readl(U300_PIN_REG(offset, ien));
439 U300_GPIO_PORTX_SPACING); 558 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
440 val &= ~(1 << (gpio & 0x07));
441 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
442 U300_GPIO_PORTX_SPACING);
443 local_irq_restore(flags); 559 local_irq_restore(flags);
444} 560}
445EXPORT_SYMBOL(disable_irq_on_gpio_pin);
446 561
447/* Enable (value == 0) or disable (value == 1) internal pullup */ 562static void u300_gpio_irq_disable(struct irq_data *d)
448void gpio_pullup(unsigned gpio, int value)
449{ 563{
564 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
565 struct u300_gpio *gpio = port->gpio;
566 int offset = d->irq - gpio->irq_base;
450 u32 val; 567 u32 val;
451 unsigned long flags; 568 unsigned long flags;
452 569
453 local_irq_save(flags); 570 local_irq_save(flags);
454 if (value) { 571 val = readl(U300_PIN_REG(offset, ien));
455 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) * 572 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
456 U300_GPIO_PORTX_SPACING);
457 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
458 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
459 } else {
460 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
461 U300_GPIO_PORTX_SPACING);
462 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
463 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
464 }
465 local_irq_restore(flags); 573 local_irq_restore(flags);
466} 574}
467EXPORT_SYMBOL(gpio_pullup);
468 575
469static irqreturn_t gpio_irq_handler(int irq, void *dev_id) 576static struct irq_chip u300_gpio_irqchip = {
577 .name = "u300-gpio-irqchip",
578 .irq_enable = u300_gpio_irq_enable,
579 .irq_disable = u300_gpio_irq_disable,
580 .irq_set_type = u300_gpio_irq_type,
581
582};
583
584static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
470{ 585{
471 struct u300_gpio_port *port = dev_id; 586 struct u300_gpio_port *port = irq_get_handler_data(irq);
472 u32 val; 587 struct u300_gpio *gpio = port->gpio;
473 int pin; 588 int pinoffset = port->number << 3; /* get the right stride */
589 unsigned long val;
474 590
591 desc->irq_data.chip->irq_ack(&desc->irq_data);
475 /* Read event register */ 592 /* Read event register */
476 val = readl(virtbase + U300_GPIO_PXIEV + port->number * 593 val = readl(U300_PIN_REG(pinoffset, iev));
477 U300_GPIO_PORTX_SPACING);
478 /* Mask with enable register */
479 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
480 U300_GPIO_PORTX_SPACING);
481 /* Mask relevant bits */ 594 /* Mask relevant bits */
482 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK; 595 val &= 0xFFU; /* 8 bits per port */
483 /* ACK IRQ (clear event) */ 596 /* ACK IRQ (clear event) */
484 writel(val, virtbase + U300_GPIO_PXIEV + port->number * 597 writel(val, U300_PIN_REG(pinoffset, iev));
485 U300_GPIO_PORTX_SPACING); 598
486 /* Print message */ 599 /* Call IRQ handler */
487 while (val != 0) { 600 if (val != 0) {
488 unsigned gpio; 601 int irqoffset;
489 602
490 pin = __ffs(val); 603 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
491 /* mask off this pin */ 604 int pin_irq = gpio->irq_base + (port->number << 3)
492 val &= ~(1 << pin); 605 + irqoffset;
493 gpio = (port->number << 3) + pin; 606 int offset = pinoffset + irqoffset;
494 607
495 if (gpio_pin[gpio].callback) 608 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
496 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data); 609 pin_irq, offset);
497 else 610 generic_handle_irq(pin_irq);
498 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n", 611 /*
499 gpio); 612 * Triggering IRQ on both rising and falling edge
613 * needs mockery
614 */
615 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
616 u300_toggle_trigger(gpio, offset);
617 }
500 } 618 }
501 return IRQ_HANDLED; 619
620 desc->irq_data.chip->irq_unmask(&desc->irq_data);
502} 621}
503 622
504static void gpio_set_initial_values(void) 623static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
624 int offset,
625 const struct u300_gpio_confdata *conf)
505{ 626{
506#ifdef U300_COH901571_3 627 /* Set mode: input or output */
507 int i, j; 628 if (conf->output) {
508 unsigned long flags; 629 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
509 u32 val;
510 630
511 /* Write default values to all pins */ 631 /* Deactivate bias mode for output */
512 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 632 u300_gpio_config(&gpio->chip, offset,
513 val = 0; 633 GPIO_U300_CONFIG_BIAS_FLOAT,
514 for (j = 0; j < 8; j++) 634 NULL);
515 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j; 635
516 local_irq_save(flags); 636 /* Set drive mode for output */
517 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING); 637 u300_gpio_config(&gpio->chip, offset,
518 local_irq_restore(flags); 638 GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL);
639
640 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
641 offset, conf->outval);
642 } else {
643 u300_gpio_direction_input(&gpio->chip, offset);
644
645 /* Always set output low on input pins */
646 u300_gpio_set(&gpio->chip, offset, 0);
647
648 /* Set bias mode for input */
649 u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL);
650
651 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
652 offset, conf->bias_mode);
519 } 653 }
654}
520 655
521 /* 656static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
522 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED' 657 struct u300_gpio_platform *plat)
523 * to output and 'GPIO_IN' to input for each port. And initialize 658{
524 * default value on outputs. 659 int i, j;
525 */ 660
526 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 661 /* Write default config and values to all pins */
527 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) { 662 for (i = 0; i < plat->ports; i++) {
528 local_irq_save(flags); 663 for (j = 0; j < 8; j++) {
529 val = readl(virtbase + U300_GPIO_PXPCR + 664 const struct u300_gpio_confdata *conf;
530 i * U300_GPIO_PORTX_SPACING); 665 int offset = (i*8) + j;
531 /* Mask out this pin */ 666
532 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1)); 667 if (plat->variant == U300_GPIO_COH901571_3_BS335)
533 668 conf = &bs335_gpio_config[i][j];
534 if (u300_gpio_config[i][j].pin_usage != GPIO_IN) 669 else if (plat->variant == U300_GPIO_COH901571_3_BS365)
535 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1)); 670 conf = &bs365_gpio_config[i][j];
536 writel(val, virtbase + U300_GPIO_PXPCR + 671 else
537 i * U300_GPIO_PORTX_SPACING); 672 break;
538 local_irq_restore(flags); 673
674 u300_gpio_init_pin(gpio, offset, conf);
539 } 675 }
540 } 676 }
677}
541 678
542 /* Enable or disable the internal pull-ups in the GPIO ASIC block */ 679static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
543 for (i = 0; i < U300_GPIO_MAX; i++) { 680{
544 val = 0; 681 struct u300_gpio_port *port;
545 for (j = 0; j < 8; j++) 682 struct list_head *p, *n;
546 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j); 683
547 local_irq_save(flags); 684 list_for_each_safe(p, n, &gpio->port_list) {
548 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); 685 port = list_entry(p, struct u300_gpio_port, node);
549 local_irq_restore(flags); 686 list_del(&port->node);
687 free_irq(port->irq, port);
688 kfree(port);
550 } 689 }
551#endif
552} 690}
553 691
554static int __init gpio_probe(struct platform_device *pdev) 692static int __init u300_gpio_probe(struct platform_device *pdev)
555{ 693{
556 u32 val; 694 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
695 struct u300_gpio *gpio;
557 int err = 0; 696 int err = 0;
697 int portno;
698 u32 val;
699 u32 ifr;
558 int i; 700 int i;
559 int num_irqs;
560 701
561 gpiodev = &pdev->dev; 702 gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
562 memset(gpio_pin, 0, sizeof(gpio_pin)); 703 if (gpio == NULL) {
704 dev_err(&pdev->dev, "failed to allocate memory\n");
705 return -ENOMEM;
706 }
707
708 gpio->chip = u300_gpio_chip;
709 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
710 gpio->irq_base = plat->gpio_irq_base;
711 gpio->chip.dev = &pdev->dev;
712 gpio->chip.base = plat->gpio_base;
713 gpio->dev = &pdev->dev;
563 714
564 /* Get GPIO clock */ 715 /* Get GPIO clock */
565 clk = clk_get(&pdev->dev, NULL); 716 gpio->clk = clk_get(gpio->dev, NULL);
566 if (IS_ERR(clk)) { 717 if (IS_ERR(gpio->clk)) {
567 err = PTR_ERR(clk); 718 err = PTR_ERR(gpio->clk);
568 dev_err(gpiodev, "could not get GPIO clock\n"); 719 dev_err(gpio->dev, "could not get GPIO clock\n");
569 goto err_no_clk; 720 goto err_no_clk;
570 } 721 }
571 err = clk_enable(clk); 722 err = clk_enable(gpio->clk);
572 if (err) { 723 if (err) {
573 dev_err(gpiodev, "could not enable GPIO clock\n"); 724 dev_err(gpio->dev, "could not enable GPIO clock\n");
574 goto err_no_clk_enable; 725 goto err_no_clk_enable;
575 } 726 }
576 727
577 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 728 gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
578 if (!memres) 729 if (!gpio->memres) {
730 dev_err(gpio->dev, "could not get GPIO memory resource\n");
731 err = -ENODEV;
579 goto err_no_resource; 732 goto err_no_resource;
733 }
580 734
581 if (!request_mem_region(memres->start, resource_size(memres), 735 if (!request_mem_region(gpio->memres->start,
736 resource_size(gpio->memres),
582 "GPIO Controller")) { 737 "GPIO Controller")) {
583 err = -ENODEV; 738 err = -ENODEV;
584 goto err_no_ioregion; 739 goto err_no_ioregion;
585 } 740 }
586 741
587 virtbase = ioremap(memres->start, resource_size(memres)); 742 gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
588 if (!virtbase) { 743 if (!gpio->base) {
589 err = -ENOMEM; 744 err = -ENOMEM;
590 goto err_no_ioremap; 745 goto err_no_ioremap;
591 } 746 }
592 dev_info(gpiodev, "remapped 0x%08x to %p\n", 747
593 memres->start, virtbase); 748 if (plat->variant == U300_GPIO_COH901335) {
594 749 dev_info(gpio->dev,
595#ifdef U300_COH901335 750 "initializing GPIO Controller COH 901 335\n");
596 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n"); 751 gpio->stride = U300_335_PORT_STRIDE;
597 /* Turn on the GPIO block */ 752 gpio->pcr = U300_335_PXPCR;
598 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR); 753 gpio->dor = U300_335_PXPDOR;
599#endif 754 gpio->dir = U300_335_PXPDIR;
600 755 gpio->per = U300_335_PXPER;
601#ifdef U300_COH901571_3 756 gpio->icr = U300_335_PXICR;
602 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n"); 757 gpio->ien = U300_335_PXIEN;
603 val = readl(virtbase + U300_GPIO_CR); 758 gpio->iev = U300_335_PXIEV;
604 dev_info(gpiodev, "COH901571/3 block version: %d, " \ 759 ifr = U300_335_PXIFR;
605 "number of cores: %d\n", 760
606 ((val & 0x0000FE00) >> 9), 761 /* Turn on the GPIO block */
607 ((val & 0x000001FC) >> 2)); 762 writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
608 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR); 763 gpio->base + U300_335_CR);
609#endif 764 } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
610 765 plat->variant == U300_GPIO_COH901571_3_BS365) {
611 gpio_set_initial_values(); 766 dev_info(gpio->dev,
612 767 "initializing GPIO Controller COH 901 571/3\n");
613 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) { 768 gpio->stride = U300_571_PORT_STRIDE;
614 769 gpio->pcr = U300_571_PXPCR;
615 gpio_ports[num_irqs].irq = 770 gpio->dor = U300_571_PXPDOR;
616 platform_get_irq_byname(pdev, 771 gpio->dir = U300_571_PXPDIR;
617 gpio_ports[num_irqs].name); 772 gpio->per = U300_571_PXPER;
618 773 gpio->icr = U300_571_PXICR;
619 err = request_irq(gpio_ports[num_irqs].irq, 774 gpio->ien = U300_571_PXIEN;
620 gpio_irq_handler, IRQF_DISABLED, 775 gpio->iev = U300_571_PXIEV;
621 gpio_ports[num_irqs].name, 776 ifr = U300_571_PXIFR;
622 &gpio_ports[num_irqs]); 777
623 if (err) { 778 val = readl(gpio->base + U300_571_CR);
624 dev_err(gpiodev, "cannot allocate IRQ for %s!\n", 779 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
625 gpio_ports[num_irqs].name); 780 "number of cores: %d totalling %d pins\n",
626 goto err_no_irq; 781 ((val & 0x000001FC) >> 2),
782 ((val & 0x0000FE00) >> 9),
783 ((val & 0x0000FE00) >> 9) * 8);
784 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
785 gpio->base + U300_571_CR);
786 u300_gpio_init_coh901571(gpio, plat);
787 } else {
788 dev_err(gpio->dev, "unknown block variant\n");
789 err = -ENODEV;
790 goto err_unknown_variant;
791 }
792
793 /* Add each port with its IRQ separately */
794 INIT_LIST_HEAD(&gpio->port_list);
795 for (portno = 0 ; portno < plat->ports; portno++) {
796 struct u300_gpio_port *port =
797 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
798
799 if (!port) {
800 dev_err(gpio->dev, "out of memory\n");
801 err = -ENOMEM;
802 goto err_no_port;
627 } 803 }
628 /* Turns off PortX_irq_force */ 804
629 writel(0x0, virtbase + U300_GPIO_PXIFR + 805 snprintf(port->name, 8, "gpio%d", portno);
630 num_irqs * U300_GPIO_PORTX_SPACING); 806 port->number = portno;
807 port->gpio = gpio;
808
809 port->irq = platform_get_irq_byname(pdev,
810 port->name);
811
812 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
813 port->name);
814
815 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
816 irq_set_handler_data(port->irq, port);
817
818 /* For each GPIO pin set the unique IRQ handler */
819 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
820 int irqno = gpio->irq_base + (portno << 3) + i;
821
822 dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
823 irqno, port->name);
824 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
825 handle_simple_irq);
826 set_irq_flags(irqno, IRQF_VALID);
827 irq_set_chip_data(irqno, port);
828 }
829
830 /* Turns off irq force (test register) for this port */
831 writel(0x0, gpio->base + portno * gpio->stride + ifr);
832
833 list_add_tail(&port->node, &gpio->port_list);
631 } 834 }
835 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
836
837 err = gpiochip_add(&gpio->chip);
838 if (err) {
839 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
840 goto err_no_chip;
841 }
842
843 platform_set_drvdata(pdev, gpio);
632 844
633 return 0; 845 return 0;
634 846
635 err_no_irq: 847err_no_chip:
636 for (i = 0; i < num_irqs; i++) 848err_no_port:
637 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 849 u300_gpio_free_ports(gpio);
638 iounmap(virtbase); 850err_unknown_variant:
639 err_no_ioremap: 851 iounmap(gpio->base);
640 release_mem_region(memres->start, resource_size(memres)); 852err_no_ioremap:
641 err_no_ioregion: 853 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
642 err_no_resource: 854err_no_ioregion:
643 clk_disable(clk); 855err_no_resource:
644 err_no_clk_enable: 856 clk_disable(gpio->clk);
645 clk_put(clk); 857err_no_clk_enable:
646 err_no_clk: 858 clk_put(gpio->clk);
647 dev_info(gpiodev, "module ERROR:%d\n", err); 859err_no_clk:
860 kfree(gpio);
861 dev_info(&pdev->dev, "module ERROR:%d\n", err);
648 return err; 862 return err;
649} 863}
650 864
651static int __exit gpio_remove(struct platform_device *pdev) 865static int __exit u300_gpio_remove(struct platform_device *pdev)
652{ 866{
653 int i; 867 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
868 struct u300_gpio *gpio = platform_get_drvdata(pdev);
869 int err;
654 870
655 /* Turn off the GPIO block */ 871 /* Turn off the GPIO block */
656 writel(0x00000000U, virtbase + U300_GPIO_CR); 872 if (plat->variant == U300_GPIO_COH901335)
657 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++) 873 writel(0x00000000U, gpio->base + U300_335_CR);
658 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 874 if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
659 iounmap(virtbase); 875 plat->variant == U300_GPIO_COH901571_3_BS365)
660 release_mem_region(memres->start, resource_size(memres)); 876 writel(0x00000000U, gpio->base + U300_571_CR);
661 clk_disable(clk); 877
662 clk_put(clk); 878 err = gpiochip_remove(&gpio->chip);
879 if (err < 0) {
880 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
881 return err;
882 }
883 u300_gpio_free_ports(gpio);
884 iounmap(gpio->base);
885 release_mem_region(gpio->memres->start,
886 resource_size(gpio->memres));
887 clk_disable(gpio->clk);
888 clk_put(gpio->clk);
889 platform_set_drvdata(pdev, NULL);
890 kfree(gpio);
663 return 0; 891 return 0;
664} 892}
665 893
666static struct platform_driver gpio_driver = { 894static struct platform_driver u300_gpio_driver = {
667 .driver = { 895 .driver = {
668 .name = "u300-gpio", 896 .name = "u300-gpio",
669 }, 897 },
670 .remove = __exit_p(gpio_remove), 898 .remove = __exit_p(u300_gpio_remove),
671}; 899};
672 900
673 901
674static int __init u300_gpio_init(void) 902static int __init u300_gpio_init(void)
675{ 903{
676 return platform_driver_probe(&gpio_driver, gpio_probe); 904 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
677} 905}
678 906
679static void __exit u300_gpio_exit(void) 907static void __exit u300_gpio_exit(void)
680{ 908{
681 platform_driver_unregister(&gpio_driver); 909 platform_driver_unregister(&u300_gpio_driver);
682} 910}
683 911
684arch_initcall(u300_gpio_init); 912arch_initcall(u300_gpio_init);
685module_exit(u300_gpio_exit); 913module_exit(u300_gpio_exit);
686 914
687MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 915MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
688 916MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
689#ifdef U300_COH901571_3
690MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
691#endif
692
693#ifdef U300_COH901335
694MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
695#endif
696
697MODULE_LICENSE("GPL"); 917MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 04:38:54 -0500