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-rw-r--r--drivers/gpio/74x164.c182
-rw-r--r--drivers/gpio/Kconfig130
-rw-r--r--drivers/gpio/Makefile23
-rw-r--r--drivers/gpio/ab8500-gpio.c521
-rw-r--r--drivers/gpio/adp5588-gpio.c278
-rw-r--r--drivers/gpio/basic_mmio_gpio.c548
-rw-r--r--drivers/gpio/cs5535-gpio.c172
-rw-r--r--drivers/gpio/gpio-exynos4.c386
-rw-r--r--drivers/gpio/gpio-nomadik.c1087
-rw-r--r--drivers/gpio/gpio-omap.c2009
-rw-r--r--drivers/gpio/gpio-plat-samsung.c206
-rw-r--r--drivers/gpio/gpio-s5pc100.c355
-rw-r--r--drivers/gpio/gpio-s5pv210.c288
-rw-r--r--drivers/gpio/gpio-u300.c700
-rw-r--r--drivers/gpio/gpiolib.c71
-rw-r--r--drivers/gpio/langwell_gpio.c212
-rw-r--r--drivers/gpio/max732x.c46
-rw-r--r--drivers/gpio/mc33880.c4
-rw-r--r--drivers/gpio/mcp23s08.c191
-rw-r--r--drivers/gpio/ml_ioh_gpio.c357
-rw-r--r--drivers/gpio/pca953x.c350
-rw-r--r--drivers/gpio/pch_gpio.c316
-rw-r--r--drivers/gpio/pl061.c44
-rw-r--r--drivers/gpio/sch_gpio.c57
-rw-r--r--drivers/gpio/stmpe-gpio.c61
-rw-r--r--drivers/gpio/sx150x.c107
-rw-r--r--drivers/gpio/tc35892-gpio.c381
-rw-r--r--drivers/gpio/tc3589x-gpio.c389
-rw-r--r--drivers/gpio/timbgpio.c65
-rw-r--r--drivers/gpio/tps65910-gpio.c102
-rw-r--r--drivers/gpio/vr41xx_giu.c60
-rw-r--r--drivers/gpio/vx855_gpio.c333
-rw-r--r--drivers/gpio/wm831x-gpio.c1
-rw-r--r--drivers/gpio/wm8994-gpio.c25
-rw-r--r--drivers/gpio/xilinx_gpio.c6
35 files changed, 9150 insertions, 913 deletions
diff --git a/drivers/gpio/74x164.c b/drivers/gpio/74x164.c
new file mode 100644
index 000000000000..84e070219839
--- /dev/null
+++ b/drivers/gpio/74x164.c
@@ -0,0 +1,182 @@
1/*
2 * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
3 *
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/mutex.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/74x164.h>
16#include <linux/gpio.h>
17#include <linux/slab.h>
18
19#define GEN_74X164_GPIO_COUNT 8
20
21
22struct gen_74x164_chip {
23 struct spi_device *spi;
24 struct gpio_chip gpio_chip;
25 struct mutex lock;
26 u8 port_config;
27};
28
29static void gen_74x164_set_value(struct gpio_chip *, unsigned, int);
30
31static struct gen_74x164_chip *gpio_to_chip(struct gpio_chip *gc)
32{
33 return container_of(gc, struct gen_74x164_chip, gpio_chip);
34}
35
36static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
37{
38 return spi_write(chip->spi,
39 &chip->port_config, sizeof(chip->port_config));
40}
41
42static int gen_74x164_direction_output(struct gpio_chip *gc,
43 unsigned offset, int val)
44{
45 gen_74x164_set_value(gc, offset, val);
46 return 0;
47}
48
49static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
50{
51 struct gen_74x164_chip *chip = gpio_to_chip(gc);
52 int ret;
53
54 mutex_lock(&chip->lock);
55 ret = (chip->port_config >> offset) & 0x1;
56 mutex_unlock(&chip->lock);
57
58 return ret;
59}
60
61static void gen_74x164_set_value(struct gpio_chip *gc,
62 unsigned offset, int val)
63{
64 struct gen_74x164_chip *chip = gpio_to_chip(gc);
65
66 mutex_lock(&chip->lock);
67 if (val)
68 chip->port_config |= (1 << offset);
69 else
70 chip->port_config &= ~(1 << offset);
71
72 __gen_74x164_write_config(chip);
73 mutex_unlock(&chip->lock);
74}
75
76static int __devinit gen_74x164_probe(struct spi_device *spi)
77{
78 struct gen_74x164_chip *chip;
79 struct gen_74x164_chip_platform_data *pdata;
80 int ret;
81
82 pdata = spi->dev.platform_data;
83 if (!pdata || !pdata->base) {
84 dev_dbg(&spi->dev, "incorrect or missing platform data\n");
85 return -EINVAL;
86 }
87
88 /*
89 * bits_per_word cannot be configured in platform data
90 */
91 spi->bits_per_word = 8;
92
93 ret = spi_setup(spi);
94 if (ret < 0)
95 return ret;
96
97 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
98 if (!chip)
99 return -ENOMEM;
100
101 mutex_init(&chip->lock);
102
103 dev_set_drvdata(&spi->dev, chip);
104
105 chip->spi = spi;
106
107 chip->gpio_chip.label = GEN_74X164_DRIVER_NAME,
108 chip->gpio_chip.direction_output = gen_74x164_direction_output;
109 chip->gpio_chip.get = gen_74x164_get_value;
110 chip->gpio_chip.set = gen_74x164_set_value;
111 chip->gpio_chip.base = pdata->base;
112 chip->gpio_chip.ngpio = GEN_74X164_GPIO_COUNT;
113 chip->gpio_chip.can_sleep = 1;
114 chip->gpio_chip.dev = &spi->dev;
115 chip->gpio_chip.owner = THIS_MODULE;
116
117 ret = __gen_74x164_write_config(chip);
118 if (ret) {
119 dev_err(&spi->dev, "Failed writing: %d\n", ret);
120 goto exit_destroy;
121 }
122
123 ret = gpiochip_add(&chip->gpio_chip);
124 if (ret)
125 goto exit_destroy;
126
127 return ret;
128
129exit_destroy:
130 dev_set_drvdata(&spi->dev, NULL);
131 mutex_destroy(&chip->lock);
132 kfree(chip);
133 return ret;
134}
135
136static int __devexit gen_74x164_remove(struct spi_device *spi)
137{
138 struct gen_74x164_chip *chip;
139 int ret;
140
141 chip = dev_get_drvdata(&spi->dev);
142 if (chip == NULL)
143 return -ENODEV;
144
145 dev_set_drvdata(&spi->dev, NULL);
146
147 ret = gpiochip_remove(&chip->gpio_chip);
148 if (!ret) {
149 mutex_destroy(&chip->lock);
150 kfree(chip);
151 } else
152 dev_err(&spi->dev, "Failed to remove the GPIO controller: %d\n",
153 ret);
154
155 return ret;
156}
157
158static struct spi_driver gen_74x164_driver = {
159 .driver = {
160 .name = GEN_74X164_DRIVER_NAME,
161 .owner = THIS_MODULE,
162 },
163 .probe = gen_74x164_probe,
164 .remove = __devexit_p(gen_74x164_remove),
165};
166
167static int __init gen_74x164_init(void)
168{
169 return spi_register_driver(&gen_74x164_driver);
170}
171subsys_initcall(gen_74x164_init);
172
173static void __exit gen_74x164_exit(void)
174{
175 spi_unregister_driver(&gen_74x164_driver);
176}
177module_exit(gen_74x164_exit);
178
179MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
180MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
181MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
182MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 510aa2054544..2967002a9f82 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1,5 +1,5 @@
1# 1#
2# platform-neutral GPIO infrastructure and expanders 2# GPIO infrastructure and drivers
3# 3#
4 4
5config ARCH_WANT_OPTIONAL_GPIOLIB 5config ARCH_WANT_OPTIONAL_GPIOLIB
@@ -31,7 +31,7 @@ menuconfig GPIOLIB
31 help 31 help
32 This enables GPIO support through the generic GPIO library. 32 This enables GPIO support through the generic GPIO library.
33 You only need to enable this, if you also want to enable 33 You only need to enable this, if you also want to enable
34 one or more of the GPIO expansion card drivers below. 34 one or more of the GPIO drivers below.
35 35
36 If unsure, say N. 36 If unsure, say N.
37 37
@@ -63,19 +63,45 @@ config GPIO_SYSFS
63 Kernel drivers may also request that a particular GPIO be 63 Kernel drivers may also request that a particular GPIO be
64 exported to userspace; this can be useful when debugging. 64 exported to userspace; this can be useful when debugging.
65 65
66# put expanders in the right section, in alphabetical order 66# put drivers in the right section, in alphabetical order
67 67
68config GPIO_MAX730X 68config GPIO_MAX730X
69 tristate 69 tristate
70 70
71comment "Memory mapped GPIO expanders:" 71comment "Memory mapped GPIO drivers:"
72
73config GPIO_BASIC_MMIO_CORE
74 tristate
75 help
76 Provides core functionality for basic memory-mapped GPIO controllers.
77
78config GPIO_BASIC_MMIO
79 tristate "Basic memory-mapped GPIO controllers support"
80 select GPIO_BASIC_MMIO_CORE
81 help
82 Say yes here to support basic memory-mapped GPIO controllers.
72 83
73config GPIO_IT8761E 84config GPIO_IT8761E
74 tristate "IT8761E GPIO support" 85 tristate "IT8761E GPIO support"
75 depends on GPIOLIB
76 help 86 help
77 Say yes here to support GPIO functionality of IT8761E super I/O chip. 87 Say yes here to support GPIO functionality of IT8761E super I/O chip.
78 88
89config GPIO_EXYNOS4
90 def_bool y
91 depends on CPU_EXYNOS4210
92
93config GPIO_PLAT_SAMSUNG
94 def_bool y
95 depends on SAMSUNG_GPIOLIB_4BIT
96
97config GPIO_S5PC100
98 def_bool y
99 depends on CPU_S5PC100
100
101config GPIO_S5PV210
102 def_bool y
103 depends on CPU_S5PV210
104
79config GPIO_PL061 105config GPIO_PL061
80 bool "PrimeCell PL061 GPIO support" 106 bool "PrimeCell PL061 GPIO support"
81 depends on ARM_AMBA 107 depends on ARM_AMBA
@@ -95,22 +121,37 @@ config GPIO_VR41XX
95 Say yes here to support the NEC VR4100 series General-purpose I/O Uint 121 Say yes here to support the NEC VR4100 series General-purpose I/O Uint
96 122
97config GPIO_SCH 123config GPIO_SCH
98 tristate "Intel SCH GPIO" 124 tristate "Intel SCH/TunnelCreek GPIO"
99 depends on GPIOLIB && PCI 125 depends on PCI && X86
100 select MFD_CORE 126 select MFD_CORE
101 select LPC_SCH 127 select LPC_SCH
102 help 128 help
103 Say yes here to support GPIO interface on Intel Poulsbo SCH. 129 Say yes here to support GPIO interface on Intel Poulsbo SCH
130 or Intel Tunnel Creek processor.
104 The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are 131 The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
105 powered by the core power rail and are turned off during sleep 132 powered by the core power rail and are turned off during sleep
106 modes (S3 and higher). The remaining four GPIOs are powered by 133 modes (S3 and higher). The remaining four GPIOs are powered by
107 the Intel SCH suspend power supply. These GPIOs remain 134 the Intel SCH suspend power supply. These GPIOs remain
108 active during S3. The suspend powered GPIOs can be used to wake the 135 active during S3. The suspend powered GPIOs can be used to wake the
109 system from the Suspend-to-RAM state. 136 system from the Suspend-to-RAM state.
137 The Intel Tunnel Creek processor has 5 GPIOs powered by the
138 core power rail and 9 from suspend power supply.
110 139
111 This driver can also be built as a module. If so, the module 140 This driver can also be built as a module. If so, the module
112 will be called sch-gpio. 141 will be called sch-gpio.
113 142
143config GPIO_VX855
144 tristate "VIA VX855/VX875 GPIO"
145 depends on MFD_SUPPORT && PCI
146 select MFD_CORE
147 select MFD_VX855
148 help
149 Support access to the VX855/VX875 GPIO lines through the gpio library.
150
151 This driver provides common support for accessing the device,
152 additional drivers must be enabled in order to use the
153 functionality of the device.
154
114comment "I2C GPIO expanders:" 155comment "I2C GPIO expanders:"
115 156
116config GPIO_MAX7300 157config GPIO_MAX7300
@@ -213,11 +254,11 @@ config GPIO_STMPE
213 This enables support for the GPIOs found on the STMPE I/O 254 This enables support for the GPIOs found on the STMPE I/O
214 Expanders. 255 Expanders.
215 256
216config GPIO_TC35892 257config GPIO_TC3589X
217 bool "TC35892 GPIOs" 258 bool "TC3589X GPIOs"
218 depends on MFD_TC35892 259 depends on MFD_TC3589X
219 help 260 help
220 This enables support for the GPIOs found on the TC35892 261 This enables support for the GPIOs found on the TC3589X
221 I/O Expander. 262 I/O Expander.
222 263
223config GPIO_TWL4030 264config GPIO_TWL4030
@@ -267,11 +308,18 @@ config GPIO_ADP5588
267 To compile this driver as a module, choose M here: the module will be 308 To compile this driver as a module, choose M here: the module will be
268 called adp5588-gpio. 309 called adp5588-gpio.
269 310
311config GPIO_ADP5588_IRQ
312 bool "Interrupt controller support for ADP5588"
313 depends on GPIO_ADP5588=y
314 help
315 Say yes here to enable the adp5588 to be used as an interrupt
316 controller. It requires the driver to be built in the kernel.
317
270comment "PCI GPIO expanders:" 318comment "PCI GPIO expanders:"
271 319
272config GPIO_CS5535 320config GPIO_CS5535
273 tristate "AMD CS5535/CS5536 GPIO support" 321 tristate "AMD CS5535/CS5536 GPIO support"
274 depends on PCI && !CS5535_GPIO 322 depends on PCI && X86 && !CS5535_GPIO && MFD_CS5535
275 help 323 help
276 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that 324 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
277 can be used for quite a number of things. The CS5535/6 is found on 325 can be used for quite a number of things. The CS5535/6 is found on
@@ -297,19 +345,43 @@ config GPIO_BT8XX
297 345
298config GPIO_LANGWELL 346config GPIO_LANGWELL
299 bool "Intel Langwell/Penwell GPIO support" 347 bool "Intel Langwell/Penwell GPIO support"
300 depends on PCI 348 depends on PCI && X86
301 help 349 help
302 Say Y here to support Intel Langwell/Penwell GPIO. 350 Say Y here to support Intel Langwell/Penwell GPIO.
303 351
352config GPIO_PCH
353 tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GPIO"
354 depends on PCI && X86
355 help
356 This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff
357 which is an IOH(Input/Output Hub) for x86 embedded processor.
358 This driver can access PCH GPIO device.
359
360 This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
361 Output Hub), ML7223.
362 ML7223 IOH is for MP(Media Phone) use.
363 ML7223 is companion chip for Intel Atom E6xx series.
364 ML7223 is completely compatible for Intel EG20T PCH.
365
366config GPIO_ML_IOH
367 tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"
368 depends on PCI
369 help
370 ML7213 is companion chip for Intel Atom E6xx series.
371 This driver can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/Output
372 Hub) which is for IVI(In-Vehicle Infotainment) use.
373 This driver can access the IOH's GPIO device.
374
304config GPIO_TIMBERDALE 375config GPIO_TIMBERDALE
305 bool "Support for timberdale GPIO IP" 376 bool "Support for timberdale GPIO IP"
306 depends on MFD_TIMBERDALE && GPIOLIB && HAS_IOMEM 377 depends on MFD_TIMBERDALE && HAS_IOMEM
307 ---help--- 378 ---help---
308 Add support for the GPIO IP in the timberdale FPGA. 379 Add support for the GPIO IP in the timberdale FPGA.
309 380
310config GPIO_RDC321X 381config GPIO_RDC321X
311 tristate "RDC R-321x GPIO support" 382 tristate "RDC R-321x GPIO support"
312 depends on PCI && GPIOLIB 383 depends on PCI
384 select MFD_SUPPORT
313 select MFD_CORE 385 select MFD_CORE
314 select MFD_RDC321X 386 select MFD_RDC321X
315 help 387 help
@@ -326,11 +398,11 @@ config GPIO_MAX7301
326 GPIO driver for Maxim MAX7301 SPI-based GPIO expander. 398 GPIO driver for Maxim MAX7301 SPI-based GPIO expander.
327 399
328config GPIO_MCP23S08 400config GPIO_MCP23S08
329 tristate "Microchip MCP23S08 I/O expander" 401 tristate "Microchip MCP23Sxx I/O expander"
330 depends on SPI_MASTER 402 depends on SPI_MASTER
331 help 403 help
332 SPI driver for Microchip MCP23S08 I/O expander. This provides 404 SPI driver for Microchip MCP23S08/MPC23S17 I/O expanders.
333 a GPIO interface supporting inputs and outputs. 405 This provides a GPIO interface supporting inputs and outputs.
334 406
335config GPIO_MC33880 407config GPIO_MC33880
336 tristate "Freescale MC33880 high-side/low-side switch" 408 tristate "Freescale MC33880 high-side/low-side switch"
@@ -339,6 +411,14 @@ config GPIO_MC33880
339 SPI driver for Freescale MC33880 high-side/low-side switch. 411 SPI driver for Freescale MC33880 high-side/low-side switch.
340 This provides GPIO interface supporting inputs and outputs. 412 This provides GPIO interface supporting inputs and outputs.
341 413
414config GPIO_74X164
415 tristate "74x164 serial-in/parallel-out 8-bits shift register"
416 depends on SPI_MASTER
417 help
418 Platform driver for 74x164 compatible serial-in/parallel-out
419 8-outputs shift registers. This driver can be used to provide access
420 to more gpio outputs.
421
342comment "AC97 GPIO expanders:" 422comment "AC97 GPIO expanders:"
343 423
344config GPIO_UCB1400 424config GPIO_UCB1400
@@ -361,4 +441,16 @@ config GPIO_JANZ_TTL
361 This driver provides support for driving the pins in output 441 This driver provides support for driving the pins in output
362 mode only. Input mode is not supported. 442 mode only. Input mode is not supported.
363 443
444config AB8500_GPIO
445 bool "ST-Ericsson AB8500 Mixed Signal Circuit gpio functions"
446 depends on AB8500_CORE && BROKEN
447 help
448 Select this to enable the AB8500 IC GPIO driver
449
450config GPIO_TPS65910
451 bool "TPS65910 GPIO"
452 depends on MFD_TPS65910
453 help
454 Select this option to enable GPIO driver for the TPS65910
455 chip family.
364endif 456endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fc6019d93720..b605f8ec6fbe 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1,8 +1,4 @@
1# generic gpio support: dedicated expander chips, etc 1# generic gpio support: platform drivers, dedicated expander chips, etc
2#
3# NOTE: platform-specific GPIO drivers don't belong in the
4# drivers/gpio directory; put them with other platform setup
5# code, IRQ controllers, board init, etc.
6 2
7ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG 3ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
8 4
@@ -10,6 +6,12 @@ obj-$(CONFIG_GPIOLIB) += gpiolib.o
10 6
11obj-$(CONFIG_GPIO_ADP5520) += adp5520-gpio.o 7obj-$(CONFIG_GPIO_ADP5520) += adp5520-gpio.o
12obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o 8obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o
9obj-$(CONFIG_GPIO_BASIC_MMIO_CORE) += basic_mmio_gpio.o
10obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o
11obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o
12obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
13obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o
14obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o
13obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o 15obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o
14obj-$(CONFIG_GPIO_MAX730X) += max730x.o 16obj-$(CONFIG_GPIO_MAX730X) += max730x.o
15obj-$(CONFIG_GPIO_MAX7300) += max7300.o 17obj-$(CONFIG_GPIO_MAX7300) += max7300.o
@@ -17,11 +19,14 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o
17obj-$(CONFIG_GPIO_MAX732X) += max732x.o 19obj-$(CONFIG_GPIO_MAX732X) += max732x.o
18obj-$(CONFIG_GPIO_MC33880) += mc33880.o 20obj-$(CONFIG_GPIO_MC33880) += mc33880.o
19obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o 21obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o
22obj-$(CONFIG_GPIO_74X164) += 74x164.o
23obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
20obj-$(CONFIG_GPIO_PCA953X) += pca953x.o 24obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
21obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o 25obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
26obj-$(CONFIG_GPIO_PCH) += pch_gpio.o
22obj-$(CONFIG_GPIO_PL061) += pl061.o 27obj-$(CONFIG_GPIO_PL061) += pl061.o
23obj-$(CONFIG_GPIO_STMPE) += stmpe-gpio.o 28obj-$(CONFIG_GPIO_STMPE) += stmpe-gpio.o
24obj-$(CONFIG_GPIO_TC35892) += tc35892-gpio.o 29obj-$(CONFIG_GPIO_TC3589X) += tc3589x-gpio.o
25obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o 30obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o
26obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o 31obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
27obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o 32obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o
@@ -34,6 +39,12 @@ obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
34obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o 39obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o
35obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o 40obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o
36obj-$(CONFIG_GPIO_SCH) += sch_gpio.o 41obj-$(CONFIG_GPIO_SCH) += sch_gpio.o
42obj-$(CONFIG_MACH_U300) += gpio-u300.o
43obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
37obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o 44obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o
38obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o 45obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
39obj-$(CONFIG_GPIO_SX150X) += sx150x.o 46obj-$(CONFIG_GPIO_SX150X) += sx150x.o
47obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o
48obj-$(CONFIG_GPIO_ML_IOH) += ml_ioh_gpio.o
49obj-$(CONFIG_AB8500_GPIO) += ab8500-gpio.o
50obj-$(CONFIG_GPIO_TPS65910) += tps65910-gpio.o
diff --git a/drivers/gpio/ab8500-gpio.c b/drivers/gpio/ab8500-gpio.c
new file mode 100644
index 000000000000..970053c89ff7
--- /dev/null
+++ b/drivers/gpio/ab8500-gpio.c
@@ -0,0 +1,521 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * Author: BIBEK BASU <bibek.basu@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/gpio.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/mfd/ab8500.h>
23#include <linux/mfd/abx500.h>
24#include <linux/mfd/ab8500/gpio.h>
25
26/*
27 * GPIO registers offset
28 * Bank: 0x10
29 */
30#define AB8500_GPIO_SEL1_REG 0x00
31#define AB8500_GPIO_SEL2_REG 0x01
32#define AB8500_GPIO_SEL3_REG 0x02
33#define AB8500_GPIO_SEL4_REG 0x03
34#define AB8500_GPIO_SEL5_REG 0x04
35#define AB8500_GPIO_SEL6_REG 0x05
36
37#define AB8500_GPIO_DIR1_REG 0x10
38#define AB8500_GPIO_DIR2_REG 0x11
39#define AB8500_GPIO_DIR3_REG 0x12
40#define AB8500_GPIO_DIR4_REG 0x13
41#define AB8500_GPIO_DIR5_REG 0x14
42#define AB8500_GPIO_DIR6_REG 0x15
43
44#define AB8500_GPIO_OUT1_REG 0x20
45#define AB8500_GPIO_OUT2_REG 0x21
46#define AB8500_GPIO_OUT3_REG 0x22
47#define AB8500_GPIO_OUT4_REG 0x23
48#define AB8500_GPIO_OUT5_REG 0x24
49#define AB8500_GPIO_OUT6_REG 0x25
50
51#define AB8500_GPIO_PUD1_REG 0x30
52#define AB8500_GPIO_PUD2_REG 0x31
53#define AB8500_GPIO_PUD3_REG 0x32
54#define AB8500_GPIO_PUD4_REG 0x33
55#define AB8500_GPIO_PUD5_REG 0x34
56#define AB8500_GPIO_PUD6_REG 0x35
57
58#define AB8500_GPIO_IN1_REG 0x40
59#define AB8500_GPIO_IN2_REG 0x41
60#define AB8500_GPIO_IN3_REG 0x42
61#define AB8500_GPIO_IN4_REG 0x43
62#define AB8500_GPIO_IN5_REG 0x44
63#define AB8500_GPIO_IN6_REG 0x45
64#define AB8500_GPIO_ALTFUN_REG 0x45
65#define ALTFUN_REG_INDEX 6
66#define AB8500_NUM_GPIO 42
67#define AB8500_NUM_VIR_GPIO_IRQ 16
68
69enum ab8500_gpio_action {
70 NONE,
71 STARTUP,
72 SHUTDOWN,
73 MASK,
74 UNMASK
75};
76
77struct ab8500_gpio {
78 struct gpio_chip chip;
79 struct ab8500 *parent;
80 struct device *dev;
81 struct mutex lock;
82 u32 irq_base;
83 enum ab8500_gpio_action irq_action;
84 u16 rising;
85 u16 falling;
86};
87/**
88 * to_ab8500_gpio() - get the pointer to ab8500_gpio
89 * @chip: Member of the structure ab8500_gpio
90 */
91static inline struct ab8500_gpio *to_ab8500_gpio(struct gpio_chip *chip)
92{
93 return container_of(chip, struct ab8500_gpio, chip);
94}
95
96static int ab8500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
97 unsigned offset, int val)
98{
99 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
100 u8 pos = offset % 8;
101 int ret;
102
103 reg = reg + (offset / 8);
104 ret = abx500_mask_and_set_register_interruptible(ab8500_gpio->dev,
105 AB8500_MISC, reg, 1 << pos, val << pos);
106 if (ret < 0)
107 dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
108 return ret;
109}
110/**
111 * ab8500_gpio_get() - Get the particular GPIO value
112 * @chip: Gpio device
113 * @offset: GPIO number to read
114 */
115static int ab8500_gpio_get(struct gpio_chip *chip, unsigned offset)
116{
117 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
118 u8 mask = 1 << (offset % 8);
119 u8 reg = AB8500_GPIO_OUT1_REG + (offset / 8);
120 int ret;
121 u8 data;
122 ret = abx500_get_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
123 reg, &data);
124 if (ret < 0) {
125 dev_err(ab8500_gpio->dev, "%s read failed\n", __func__);
126 return ret;
127 }
128 return (data & mask) >> (offset % 8);
129}
130
131static void ab8500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
132{
133 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
134 int ret;
135 /* Write the data */
136 ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, 1);
137 if (ret < 0)
138 dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
139}
140
141static int ab8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
142 int val)
143{
144 int ret;
145 /* set direction as output */
146 ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
147 if (ret < 0)
148 return ret;
149 /* disable pull down */
150 ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
151 if (ret < 0)
152 return ret;
153 /* set the output as 1 or 0 */
154 return ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
155
156}
157
158static int ab8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
159{
160 /* set the register as input */
161 return ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
162}
163
164static int ab8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
165{
166 /*
167 * Only some GPIOs are interrupt capable, and they are
168 * organized in discontiguous clusters:
169 *
170 * GPIO6 to GPIO13
171 * GPIO24 and GPIO25
172 * GPIO36 to GPIO41
173 */
174 static struct ab8500_gpio_irq_cluster {
175 int start;
176 int end;
177 } clusters[] = {
178 {.start = 6, .end = 13},
179 {.start = 24, .end = 25},
180 {.start = 36, .end = 41},
181 };
182 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
183 int base = ab8500_gpio->irq_base;
184 int i;
185
186 for (i = 0; i < ARRAY_SIZE(clusters); i++) {
187 struct ab8500_gpio_irq_cluster *cluster = &clusters[i];
188
189 if (offset >= cluster->start && offset <= cluster->end)
190 return base + offset - cluster->start;
191
192 /* Advance by the number of gpios in this cluster */
193 base += cluster->end - cluster->start + 1;
194 }
195
196 return -EINVAL;
197}
198
199static struct gpio_chip ab8500gpio_chip = {
200 .label = "ab8500_gpio",
201 .owner = THIS_MODULE,
202 .direction_input = ab8500_gpio_direction_input,
203 .get = ab8500_gpio_get,
204 .direction_output = ab8500_gpio_direction_output,
205 .set = ab8500_gpio_set,
206 .to_irq = ab8500_gpio_to_irq,
207};
208
209static unsigned int irq_to_rising(unsigned int irq)
210{
211 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
212 int offset = irq - ab8500_gpio->irq_base;
213 int new_irq = offset + AB8500_INT_GPIO6R
214 + ab8500_gpio->parent->irq_base;
215 return new_irq;
216}
217
218static unsigned int irq_to_falling(unsigned int irq)
219{
220 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
221 int offset = irq - ab8500_gpio->irq_base;
222 int new_irq = offset + AB8500_INT_GPIO6F
223 + ab8500_gpio->parent->irq_base;
224 return new_irq;
225
226}
227
228static unsigned int rising_to_irq(unsigned int irq, void *dev)
229{
230 struct ab8500_gpio *ab8500_gpio = dev;
231 int offset = irq - AB8500_INT_GPIO6R
232 - ab8500_gpio->parent->irq_base ;
233 int new_irq = offset + ab8500_gpio->irq_base;
234 return new_irq;
235}
236
237static unsigned int falling_to_irq(unsigned int irq, void *dev)
238{
239 struct ab8500_gpio *ab8500_gpio = dev;
240 int offset = irq - AB8500_INT_GPIO6F
241 - ab8500_gpio->parent->irq_base ;
242 int new_irq = offset + ab8500_gpio->irq_base;
243 return new_irq;
244
245}
246
247/*
248 * IRQ handler
249 */
250
251static irqreturn_t handle_rising(int irq, void *dev)
252{
253
254 handle_nested_irq(rising_to_irq(irq , dev));
255 return IRQ_HANDLED;
256}
257
258static irqreturn_t handle_falling(int irq, void *dev)
259{
260
261 handle_nested_irq(falling_to_irq(irq, dev));
262 return IRQ_HANDLED;
263}
264
265static void ab8500_gpio_irq_lock(unsigned int irq)
266{
267 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
268 mutex_lock(&ab8500_gpio->lock);
269}
270
271static void ab8500_gpio_irq_sync_unlock(unsigned int irq)
272{
273 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
274 int offset = irq - ab8500_gpio->irq_base;
275 bool rising = ab8500_gpio->rising & BIT(offset);
276 bool falling = ab8500_gpio->falling & BIT(offset);
277 int ret;
278
279 switch (ab8500_gpio->irq_action) {
280 case STARTUP:
281 if (rising)
282 ret = request_threaded_irq(irq_to_rising(irq),
283 NULL, handle_rising,
284 IRQF_TRIGGER_RISING,
285 "ab8500-gpio-r", ab8500_gpio);
286 if (falling)
287 ret = request_threaded_irq(irq_to_falling(irq),
288 NULL, handle_falling,
289 IRQF_TRIGGER_FALLING,
290 "ab8500-gpio-f", ab8500_gpio);
291 break;
292 case SHUTDOWN:
293 if (rising)
294 free_irq(irq_to_rising(irq), ab8500_gpio);
295 if (falling)
296 free_irq(irq_to_falling(irq), ab8500_gpio);
297 break;
298 case MASK:
299 if (rising)
300 disable_irq(irq_to_rising(irq));
301 if (falling)
302 disable_irq(irq_to_falling(irq));
303 break;
304 case UNMASK:
305 if (rising)
306 enable_irq(irq_to_rising(irq));
307 if (falling)
308 enable_irq(irq_to_falling(irq));
309 break;
310 case NONE:
311 break;
312 }
313 ab8500_gpio->irq_action = NONE;
314 ab8500_gpio->rising &= ~(BIT(offset));
315 ab8500_gpio->falling &= ~(BIT(offset));
316 mutex_unlock(&ab8500_gpio->lock);
317}
318
319
320static void ab8500_gpio_irq_mask(unsigned int irq)
321{
322 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
323 ab8500_gpio->irq_action = MASK;
324}
325
326static void ab8500_gpio_irq_unmask(unsigned int irq)
327{
328 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
329 ab8500_gpio->irq_action = UNMASK;
330}
331
332static int ab8500_gpio_irq_set_type(unsigned int irq, unsigned int type)
333{
334 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
335 int offset = irq - ab8500_gpio->irq_base;
336
337 if (type == IRQ_TYPE_EDGE_BOTH) {
338 ab8500_gpio->rising = BIT(offset);
339 ab8500_gpio->falling = BIT(offset);
340 } else if (type == IRQ_TYPE_EDGE_RISING) {
341 ab8500_gpio->rising = BIT(offset);
342 } else {
343 ab8500_gpio->falling = BIT(offset);
344 }
345 return 0;
346}
347
348unsigned int ab8500_gpio_irq_startup(unsigned int irq)
349{
350 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
351 ab8500_gpio->irq_action = STARTUP;
352 return 0;
353}
354
355void ab8500_gpio_irq_shutdown(unsigned int irq)
356{
357 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
358 ab8500_gpio->irq_action = SHUTDOWN;
359}
360
361static struct irq_chip ab8500_gpio_irq_chip = {
362 .name = "ab8500-gpio",
363 .startup = ab8500_gpio_irq_startup,
364 .shutdown = ab8500_gpio_irq_shutdown,
365 .bus_lock = ab8500_gpio_irq_lock,
366 .bus_sync_unlock = ab8500_gpio_irq_sync_unlock,
367 .mask = ab8500_gpio_irq_mask,
368 .unmask = ab8500_gpio_irq_unmask,
369 .set_type = ab8500_gpio_irq_set_type,
370};
371
372static int ab8500_gpio_irq_init(struct ab8500_gpio *ab8500_gpio)
373{
374 u32 base = ab8500_gpio->irq_base;
375 int irq;
376
377 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
378 set_irq_chip_data(irq, ab8500_gpio);
379 set_irq_chip_and_handler(irq, &ab8500_gpio_irq_chip,
380 handle_simple_irq);
381 set_irq_nested_thread(irq, 1);
382#ifdef CONFIG_ARM
383 set_irq_flags(irq, IRQF_VALID);
384#else
385 set_irq_noprobe(irq);
386#endif
387 }
388
389 return 0;
390}
391
392static void ab8500_gpio_irq_remove(struct ab8500_gpio *ab8500_gpio)
393{
394 int base = ab8500_gpio->irq_base;
395 int irq;
396
397 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
398#ifdef CONFIG_ARM
399 set_irq_flags(irq, 0);
400#endif
401 set_irq_chip_and_handler(irq, NULL, NULL);
402 set_irq_chip_data(irq, NULL);
403 }
404}
405
406static int __devinit ab8500_gpio_probe(struct platform_device *pdev)
407{
408 struct ab8500_platform_data *ab8500_pdata =
409 dev_get_platdata(pdev->dev.parent);
410 struct ab8500_gpio_platform_data *pdata;
411 struct ab8500_gpio *ab8500_gpio;
412 int ret;
413 int i;
414
415 pdata = ab8500_pdata->gpio;
416 if (!pdata) {
417 dev_err(&pdev->dev, "gpio platform data missing\n");
418 return -ENODEV;
419 }
420
421 ab8500_gpio = kzalloc(sizeof(struct ab8500_gpio), GFP_KERNEL);
422 if (ab8500_gpio == NULL) {
423 dev_err(&pdev->dev, "failed to allocate memory\n");
424 return -ENOMEM;
425 }
426 ab8500_gpio->dev = &pdev->dev;
427 ab8500_gpio->parent = dev_get_drvdata(pdev->dev.parent);
428 ab8500_gpio->chip = ab8500gpio_chip;
429 ab8500_gpio->chip.ngpio = AB8500_NUM_GPIO;
430 ab8500_gpio->chip.dev = &pdev->dev;
431 ab8500_gpio->chip.base = pdata->gpio_base;
432 ab8500_gpio->irq_base = pdata->irq_base;
433 /* initialize the lock */
434 mutex_init(&ab8500_gpio->lock);
435 /*
436 * AB8500 core will handle and clear the IRQ
437 * configre GPIO based on config-reg value.
438 * These values are for selecting the PINs as
439 * GPIO or alternate function
440 */
441 for (i = AB8500_GPIO_SEL1_REG; i <= AB8500_GPIO_SEL6_REG; i++) {
442 ret = abx500_set_register_interruptible(ab8500_gpio->dev,
443 AB8500_MISC, i,
444 pdata->config_reg[i]);
445 if (ret < 0)
446 goto out_free;
447 }
448 ret = abx500_set_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
449 AB8500_GPIO_ALTFUN_REG,
450 pdata->config_reg[ALTFUN_REG_INDEX]);
451 if (ret < 0)
452 goto out_free;
453
454 ret = ab8500_gpio_irq_init(ab8500_gpio);
455 if (ret)
456 goto out_free;
457 ret = gpiochip_add(&ab8500_gpio->chip);
458 if (ret) {
459 dev_err(&pdev->dev, "unable to add gpiochip: %d\n",
460 ret);
461 goto out_rem_irq;
462 }
463 platform_set_drvdata(pdev, ab8500_gpio);
464 return 0;
465
466out_rem_irq:
467 ab8500_gpio_irq_remove(ab8500_gpio);
468out_free:
469 mutex_destroy(&ab8500_gpio->lock);
470 kfree(ab8500_gpio);
471 return ret;
472}
473
474/*
475 * ab8500_gpio_remove() - remove Ab8500-gpio driver
476 * @pdev : Platform device registered
477 */
478static int __devexit ab8500_gpio_remove(struct platform_device *pdev)
479{
480 struct ab8500_gpio *ab8500_gpio = platform_get_drvdata(pdev);
481 int ret;
482
483 ret = gpiochip_remove(&ab8500_gpio->chip);
484 if (ret < 0) {
485 dev_err(ab8500_gpio->dev, "unable to remove gpiochip: %d\n",
486 ret);
487 return ret;
488 }
489
490 platform_set_drvdata(pdev, NULL);
491 mutex_destroy(&ab8500_gpio->lock);
492 kfree(ab8500_gpio);
493
494 return 0;
495}
496
497static struct platform_driver ab8500_gpio_driver = {
498 .driver = {
499 .name = "ab8500-gpio",
500 .owner = THIS_MODULE,
501 },
502 .probe = ab8500_gpio_probe,
503 .remove = __devexit_p(ab8500_gpio_remove),
504};
505
506static int __init ab8500_gpio_init(void)
507{
508 return platform_driver_register(&ab8500_gpio_driver);
509}
510arch_initcall(ab8500_gpio_init);
511
512static void __exit ab8500_gpio_exit(void)
513{
514 platform_driver_unregister(&ab8500_gpio_driver);
515}
516module_exit(ab8500_gpio_exit);
517
518MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>");
519MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO");
520MODULE_ALIAS("AB8500 GPIO driver");
521MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/adp5588-gpio.c b/drivers/gpio/adp5588-gpio.c
index 2e8e9e24f887..3525ad918771 100644
--- a/drivers/gpio/adp5588-gpio.c
+++ b/drivers/gpio/adp5588-gpio.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * GPIO Chip driver for Analog Devices 2 * GPIO Chip driver for Analog Devices
3 * ADP5588 I/O Expander and QWERTY Keypad Controller 3 * ADP5588/ADP5587 I/O Expander and QWERTY Keypad Controller
4 * 4 *
5 * Copyright 2009 Analog Devices Inc. 5 * Copyright 2009-2010 Analog Devices Inc.
6 * 6 *
7 * Licensed under the GPL-2 or later. 7 * Licensed under the GPL-2 or later.
8 */ 8 */
@@ -13,21 +13,34 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/i2c.h> 14#include <linux/i2c.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
16 18
17#include <linux/i2c/adp5588.h> 19#include <linux/i2c/adp5588.h>
18 20
19#define DRV_NAME "adp5588-gpio" 21#define DRV_NAME "adp5588-gpio"
20#define MAXGPIO 18 22
21#define ADP_BANK(offs) ((offs) >> 3) 23/*
22#define ADP_BIT(offs) (1u << ((offs) & 0x7)) 24 * Early pre 4.0 Silicon required to delay readout by at least 25ms,
25 * since the Event Counter Register updated 25ms after the interrupt
26 * asserted.
27 */
28#define WA_DELAYED_READOUT_REVID(rev) ((rev) < 4)
23 29
24struct adp5588_gpio { 30struct adp5588_gpio {
25 struct i2c_client *client; 31 struct i2c_client *client;
26 struct gpio_chip gpio_chip; 32 struct gpio_chip gpio_chip;
27 struct mutex lock; /* protect cached dir, dat_out */ 33 struct mutex lock; /* protect cached dir, dat_out */
34 /* protect serialized access to the interrupt controller bus */
35 struct mutex irq_lock;
28 unsigned gpio_start; 36 unsigned gpio_start;
37 unsigned irq_base;
29 uint8_t dat_out[3]; 38 uint8_t dat_out[3];
30 uint8_t dir[3]; 39 uint8_t dir[3];
40 uint8_t int_lvl[3];
41 uint8_t int_en[3];
42 uint8_t irq_mask[3];
43 uint8_t irq_stat[3];
31}; 44};
32 45
33static int adp5588_gpio_read(struct i2c_client *client, u8 reg) 46static int adp5588_gpio_read(struct i2c_client *client, u8 reg)
@@ -55,8 +68,8 @@ static int adp5588_gpio_get_value(struct gpio_chip *chip, unsigned off)
55 struct adp5588_gpio *dev = 68 struct adp5588_gpio *dev =
56 container_of(chip, struct adp5588_gpio, gpio_chip); 69 container_of(chip, struct adp5588_gpio, gpio_chip);
57 70
58 return !!(adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + ADP_BANK(off)) 71 return !!(adp5588_gpio_read(dev->client,
59 & ADP_BIT(off)); 72 GPIO_DAT_STAT1 + ADP5588_BANK(off)) & ADP5588_BIT(off));
60} 73}
61 74
62static void adp5588_gpio_set_value(struct gpio_chip *chip, 75static void adp5588_gpio_set_value(struct gpio_chip *chip,
@@ -66,8 +79,8 @@ static void adp5588_gpio_set_value(struct gpio_chip *chip,
66 struct adp5588_gpio *dev = 79 struct adp5588_gpio *dev =
67 container_of(chip, struct adp5588_gpio, gpio_chip); 80 container_of(chip, struct adp5588_gpio, gpio_chip);
68 81
69 bank = ADP_BANK(off); 82 bank = ADP5588_BANK(off);
70 bit = ADP_BIT(off); 83 bit = ADP5588_BIT(off);
71 84
72 mutex_lock(&dev->lock); 85 mutex_lock(&dev->lock);
73 if (val) 86 if (val)
@@ -87,10 +100,10 @@ static int adp5588_gpio_direction_input(struct gpio_chip *chip, unsigned off)
87 struct adp5588_gpio *dev = 100 struct adp5588_gpio *dev =
88 container_of(chip, struct adp5588_gpio, gpio_chip); 101 container_of(chip, struct adp5588_gpio, gpio_chip);
89 102
90 bank = ADP_BANK(off); 103 bank = ADP5588_BANK(off);
91 104
92 mutex_lock(&dev->lock); 105 mutex_lock(&dev->lock);
93 dev->dir[bank] &= ~ADP_BIT(off); 106 dev->dir[bank] &= ~ADP5588_BIT(off);
94 ret = adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, dev->dir[bank]); 107 ret = adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, dev->dir[bank]);
95 mutex_unlock(&dev->lock); 108 mutex_unlock(&dev->lock);
96 109
@@ -105,8 +118,8 @@ static int adp5588_gpio_direction_output(struct gpio_chip *chip,
105 struct adp5588_gpio *dev = 118 struct adp5588_gpio *dev =
106 container_of(chip, struct adp5588_gpio, gpio_chip); 119 container_of(chip, struct adp5588_gpio, gpio_chip);
107 120
108 bank = ADP_BANK(off); 121 bank = ADP5588_BANK(off);
109 bit = ADP_BIT(off); 122 bit = ADP5588_BIT(off);
110 123
111 mutex_lock(&dev->lock); 124 mutex_lock(&dev->lock);
112 dev->dir[bank] |= bit; 125 dev->dir[bank] |= bit;
@@ -125,6 +138,214 @@ static int adp5588_gpio_direction_output(struct gpio_chip *chip,
125 return ret; 138 return ret;
126} 139}
127 140
141#ifdef CONFIG_GPIO_ADP5588_IRQ
142static int adp5588_gpio_to_irq(struct gpio_chip *chip, unsigned off)
143{
144 struct adp5588_gpio *dev =
145 container_of(chip, struct adp5588_gpio, gpio_chip);
146 return dev->irq_base + off;
147}
148
149static void adp5588_irq_bus_lock(struct irq_data *d)
150{
151 struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
152
153 mutex_lock(&dev->irq_lock);
154}
155
156 /*
157 * genirq core code can issue chip->mask/unmask from atomic context.
158 * This doesn't work for slow busses where an access needs to sleep.
159 * bus_sync_unlock() is therefore called outside the atomic context,
160 * syncs the current irq mask state with the slow external controller
161 * and unlocks the bus.
162 */
163
164static void adp5588_irq_bus_sync_unlock(struct irq_data *d)
165{
166 struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
167 int i;
168
169 for (i = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++)
170 if (dev->int_en[i] ^ dev->irq_mask[i]) {
171 dev->int_en[i] = dev->irq_mask[i];
172 adp5588_gpio_write(dev->client, GPIO_INT_EN1 + i,
173 dev->int_en[i]);
174 }
175
176 mutex_unlock(&dev->irq_lock);
177}
178
179static void adp5588_irq_mask(struct irq_data *d)
180{
181 struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
182 unsigned gpio = d->irq - dev->irq_base;
183
184 dev->irq_mask[ADP5588_BANK(gpio)] &= ~ADP5588_BIT(gpio);
185}
186
187static void adp5588_irq_unmask(struct irq_data *d)
188{
189 struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
190 unsigned gpio = d->irq - dev->irq_base;
191
192 dev->irq_mask[ADP5588_BANK(gpio)] |= ADP5588_BIT(gpio);
193}
194
195static int adp5588_irq_set_type(struct irq_data *d, unsigned int type)
196{
197 struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
198 uint16_t gpio = d->irq - dev->irq_base;
199 unsigned bank, bit;
200
201 if ((type & IRQ_TYPE_EDGE_BOTH)) {
202 dev_err(&dev->client->dev, "irq %d: unsupported type %d\n",
203 d->irq, type);
204 return -EINVAL;
205 }
206
207 bank = ADP5588_BANK(gpio);
208 bit = ADP5588_BIT(gpio);
209
210 if (type & IRQ_TYPE_LEVEL_HIGH)
211 dev->int_lvl[bank] |= bit;
212 else if (type & IRQ_TYPE_LEVEL_LOW)
213 dev->int_lvl[bank] &= ~bit;
214 else
215 return -EINVAL;
216
217 adp5588_gpio_direction_input(&dev->gpio_chip, gpio);
218 adp5588_gpio_write(dev->client, GPIO_INT_LVL1 + bank,
219 dev->int_lvl[bank]);
220
221 return 0;
222}
223
224static struct irq_chip adp5588_irq_chip = {
225 .name = "adp5588",
226 .irq_mask = adp5588_irq_mask,
227 .irq_unmask = adp5588_irq_unmask,
228 .irq_bus_lock = adp5588_irq_bus_lock,
229 .irq_bus_sync_unlock = adp5588_irq_bus_sync_unlock,
230 .irq_set_type = adp5588_irq_set_type,
231};
232
233static int adp5588_gpio_read_intstat(struct i2c_client *client, u8 *buf)
234{
235 int ret = i2c_smbus_read_i2c_block_data(client, GPIO_INT_STAT1, 3, buf);
236
237 if (ret < 0)
238 dev_err(&client->dev, "Read INT_STAT Error\n");
239
240 return ret;
241}
242
243static irqreturn_t adp5588_irq_handler(int irq, void *devid)
244{
245 struct adp5588_gpio *dev = devid;
246 unsigned status, bank, bit, pending;
247 int ret;
248 status = adp5588_gpio_read(dev->client, INT_STAT);
249
250 if (status & ADP5588_GPI_INT) {
251 ret = adp5588_gpio_read_intstat(dev->client, dev->irq_stat);
252 if (ret < 0)
253 memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
254
255 for (bank = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
256 bank++, bit = 0) {
257 pending = dev->irq_stat[bank] & dev->irq_mask[bank];
258
259 while (pending) {
260 if (pending & (1 << bit)) {
261 handle_nested_irq(dev->irq_base +
262 (bank << 3) + bit);
263 pending &= ~(1 << bit);
264
265 }
266 bit++;
267 }
268 }
269 }
270
271 adp5588_gpio_write(dev->client, INT_STAT, status); /* Status is W1C */
272
273 return IRQ_HANDLED;
274}
275
276static int adp5588_irq_setup(struct adp5588_gpio *dev)
277{
278 struct i2c_client *client = dev->client;
279 struct adp5588_gpio_platform_data *pdata = client->dev.platform_data;
280 unsigned gpio;
281 int ret;
282
283 adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC);
284 adp5588_gpio_write(client, INT_STAT, -1); /* status is W1C */
285 adp5588_gpio_read_intstat(client, dev->irq_stat); /* read to clear */
286
287 dev->irq_base = pdata->irq_base;
288 mutex_init(&dev->irq_lock);
289
290 for (gpio = 0; gpio < dev->gpio_chip.ngpio; gpio++) {
291 int irq = gpio + dev->irq_base;
292 irq_set_chip_data(irq, dev);
293 irq_set_chip_and_handler(irq, &adp5588_irq_chip,
294 handle_level_irq);
295 irq_set_nested_thread(irq, 1);
296#ifdef CONFIG_ARM
297 /*
298 * ARM needs us to explicitly flag the IRQ as VALID,
299 * once we do so, it will also set the noprobe.
300 */
301 set_irq_flags(irq, IRQF_VALID);
302#else
303 irq_set_noprobe(irq);
304#endif
305 }
306
307 ret = request_threaded_irq(client->irq,
308 NULL,
309 adp5588_irq_handler,
310 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
311 dev_name(&client->dev), dev);
312 if (ret) {
313 dev_err(&client->dev, "failed to request irq %d\n",
314 client->irq);
315 goto out;
316 }
317
318 dev->gpio_chip.to_irq = adp5588_gpio_to_irq;
319 adp5588_gpio_write(client, CFG,
320 ADP5588_AUTO_INC | ADP5588_INT_CFG | ADP5588_GPI_INT);
321
322 return 0;
323
324out:
325 dev->irq_base = 0;
326 return ret;
327}
328
329static void adp5588_irq_teardown(struct adp5588_gpio *dev)
330{
331 if (dev->irq_base)
332 free_irq(dev->client->irq, dev);
333}
334
335#else
336static int adp5588_irq_setup(struct adp5588_gpio *dev)
337{
338 struct i2c_client *client = dev->client;
339 dev_warn(&client->dev, "interrupt support not compiled in\n");
340
341 return 0;
342}
343
344static void adp5588_irq_teardown(struct adp5588_gpio *dev)
345{
346}
347#endif /* CONFIG_GPIO_ADP5588_IRQ */
348
128static int __devinit adp5588_gpio_probe(struct i2c_client *client, 349static int __devinit adp5588_gpio_probe(struct i2c_client *client,
129 const struct i2c_device_id *id) 350 const struct i2c_device_id *id)
130{ 351{
@@ -160,37 +381,46 @@ static int __devinit adp5588_gpio_probe(struct i2c_client *client,
160 gc->can_sleep = 1; 381 gc->can_sleep = 1;
161 382
162 gc->base = pdata->gpio_start; 383 gc->base = pdata->gpio_start;
163 gc->ngpio = MAXGPIO; 384 gc->ngpio = ADP5588_MAXGPIO;
164 gc->label = client->name; 385 gc->label = client->name;
165 gc->owner = THIS_MODULE; 386 gc->owner = THIS_MODULE;
166 387
167 mutex_init(&dev->lock); 388 mutex_init(&dev->lock);
168 389
169
170 ret = adp5588_gpio_read(dev->client, DEV_ID); 390 ret = adp5588_gpio_read(dev->client, DEV_ID);
171 if (ret < 0) 391 if (ret < 0)
172 goto err; 392 goto err;
173 393
174 revid = ret & ADP5588_DEVICE_ID_MASK; 394 revid = ret & ADP5588_DEVICE_ID_MASK;
175 395
176 for (i = 0, ret = 0; i <= ADP_BANK(MAXGPIO); i++) { 396 for (i = 0, ret = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) {
177 dev->dat_out[i] = adp5588_gpio_read(client, GPIO_DAT_OUT1 + i); 397 dev->dat_out[i] = adp5588_gpio_read(client, GPIO_DAT_OUT1 + i);
178 dev->dir[i] = adp5588_gpio_read(client, GPIO_DIR1 + i); 398 dev->dir[i] = adp5588_gpio_read(client, GPIO_DIR1 + i);
179 ret |= adp5588_gpio_write(client, KP_GPIO1 + i, 0); 399 ret |= adp5588_gpio_write(client, KP_GPIO1 + i, 0);
180 ret |= adp5588_gpio_write(client, GPIO_PULL1 + i, 400 ret |= adp5588_gpio_write(client, GPIO_PULL1 + i,
181 (pdata->pullup_dis_mask >> (8 * i)) & 0xFF); 401 (pdata->pullup_dis_mask >> (8 * i)) & 0xFF);
182 402 ret |= adp5588_gpio_write(client, GPIO_INT_EN1 + i, 0);
183 if (ret) 403 if (ret)
184 goto err; 404 goto err;
185 } 405 }
186 406
407 if (pdata->irq_base) {
408 if (WA_DELAYED_READOUT_REVID(revid)) {
409 dev_warn(&client->dev, "GPIO int not supported\n");
410 } else {
411 ret = adp5588_irq_setup(dev);
412 if (ret)
413 goto err;
414 }
415 }
416
187 ret = gpiochip_add(&dev->gpio_chip); 417 ret = gpiochip_add(&dev->gpio_chip);
188 if (ret) 418 if (ret)
189 goto err; 419 goto err_irq;
190 420
191 dev_info(&client->dev, "gpios %d..%d on a %s Rev. %d\n", 421 dev_info(&client->dev, "gpios %d..%d (IRQ Base %d) on a %s Rev. %d\n",
192 gc->base, gc->base + gc->ngpio - 1, 422 gc->base, gc->base + gc->ngpio - 1,
193 client->name, revid); 423 pdata->irq_base, client->name, revid);
194 424
195 if (pdata->setup) { 425 if (pdata->setup) {
196 ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context); 426 ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context);
@@ -199,8 +429,11 @@ static int __devinit adp5588_gpio_probe(struct i2c_client *client,
199 } 429 }
200 430
201 i2c_set_clientdata(client, dev); 431 i2c_set_clientdata(client, dev);
432
202 return 0; 433 return 0;
203 434
435err_irq:
436 adp5588_irq_teardown(dev);
204err: 437err:
205 kfree(dev); 438 kfree(dev);
206 return ret; 439 return ret;
@@ -222,6 +455,9 @@ static int __devexit adp5588_gpio_remove(struct i2c_client *client)
222 } 455 }
223 } 456 }
224 457
458 if (dev->irq_base)
459 free_irq(dev->client->irq, dev);
460
225 ret = gpiochip_remove(&dev->gpio_chip); 461 ret = gpiochip_remove(&dev->gpio_chip);
226 if (ret) { 462 if (ret) {
227 dev_err(&client->dev, "gpiochip_remove failed %d\n", ret); 463 dev_err(&client->dev, "gpiochip_remove failed %d\n", ret);
diff --git a/drivers/gpio/basic_mmio_gpio.c b/drivers/gpio/basic_mmio_gpio.c
new file mode 100644
index 000000000000..8152e9f516b0
--- /dev/null
+++ b/drivers/gpio/basic_mmio_gpio.c
@@ -0,0 +1,548 @@
1/*
2 * Driver for basic memory-mapped GPIO controllers.
3 *
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
13 * ...`` ```````..
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
17 * `````````
18 ___
19_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
23 * ```````
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
31 * . ^^
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
37 * |
38 * ^^ / \
39 *
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
44 * `.......````.```
45 */
46
47#include <linux/init.h>
48#include <linux/err.h>
49#include <linux/bug.h>
50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/spinlock.h>
53#include <linux/compiler.h>
54#include <linux/types.h>
55#include <linux/errno.h>
56#include <linux/log2.h>
57#include <linux/ioport.h>
58#include <linux/io.h>
59#include <linux/gpio.h>
60#include <linux/slab.h>
61#include <linux/platform_device.h>
62#include <linux/mod_devicetable.h>
63#include <linux/basic_mmio_gpio.h>
64
65static void bgpio_write8(void __iomem *reg, unsigned long data)
66{
67 writeb(data, reg);
68}
69
70static unsigned long bgpio_read8(void __iomem *reg)
71{
72 return readb(reg);
73}
74
75static void bgpio_write16(void __iomem *reg, unsigned long data)
76{
77 writew(data, reg);
78}
79
80static unsigned long bgpio_read16(void __iomem *reg)
81{
82 return readw(reg);
83}
84
85static void bgpio_write32(void __iomem *reg, unsigned long data)
86{
87 writel(data, reg);
88}
89
90static unsigned long bgpio_read32(void __iomem *reg)
91{
92 return readl(reg);
93}
94
95#if BITS_PER_LONG >= 64
96static void bgpio_write64(void __iomem *reg, unsigned long data)
97{
98 writeq(data, reg);
99}
100
101static unsigned long bgpio_read64(void __iomem *reg)
102{
103 return readq(reg);
104}
105#endif /* BITS_PER_LONG >= 64 */
106
107static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
108{
109 return 1 << pin;
110}
111
112static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
113 unsigned int pin)
114{
115 return 1 << (bgc->bits - 1 - pin);
116}
117
118static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
119{
120 struct bgpio_chip *bgc = to_bgpio_chip(gc);
121
122 return bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio);
123}
124
125static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
126{
127 struct bgpio_chip *bgc = to_bgpio_chip(gc);
128 unsigned long mask = bgc->pin2mask(bgc, gpio);
129 unsigned long flags;
130
131 spin_lock_irqsave(&bgc->lock, flags);
132
133 if (val)
134 bgc->data |= mask;
135 else
136 bgc->data &= ~mask;
137
138 bgc->write_reg(bgc->reg_dat, bgc->data);
139
140 spin_unlock_irqrestore(&bgc->lock, flags);
141}
142
143static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
144 int val)
145{
146 struct bgpio_chip *bgc = to_bgpio_chip(gc);
147 unsigned long mask = bgc->pin2mask(bgc, gpio);
148
149 if (val)
150 bgc->write_reg(bgc->reg_set, mask);
151 else
152 bgc->write_reg(bgc->reg_clr, mask);
153}
154
155static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
156{
157 struct bgpio_chip *bgc = to_bgpio_chip(gc);
158 unsigned long mask = bgc->pin2mask(bgc, gpio);
159 unsigned long flags;
160
161 spin_lock_irqsave(&bgc->lock, flags);
162
163 if (val)
164 bgc->data |= mask;
165 else
166 bgc->data &= ~mask;
167
168 bgc->write_reg(bgc->reg_set, bgc->data);
169
170 spin_unlock_irqrestore(&bgc->lock, flags);
171}
172
173static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
174{
175 return 0;
176}
177
178static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
179 int val)
180{
181 gc->set(gc, gpio, val);
182
183 return 0;
184}
185
186static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
187{
188 struct bgpio_chip *bgc = to_bgpio_chip(gc);
189 unsigned long flags;
190
191 spin_lock_irqsave(&bgc->lock, flags);
192
193 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
194 bgc->write_reg(bgc->reg_dir, bgc->dir);
195
196 spin_unlock_irqrestore(&bgc->lock, flags);
197
198 return 0;
199}
200
201static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
202{
203 struct bgpio_chip *bgc = to_bgpio_chip(gc);
204 unsigned long flags;
205
206 gc->set(gc, gpio, val);
207
208 spin_lock_irqsave(&bgc->lock, flags);
209
210 bgc->dir |= bgc->pin2mask(bgc, gpio);
211 bgc->write_reg(bgc->reg_dir, bgc->dir);
212
213 spin_unlock_irqrestore(&bgc->lock, flags);
214
215 return 0;
216}
217
218static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
219{
220 struct bgpio_chip *bgc = to_bgpio_chip(gc);
221 unsigned long flags;
222
223 spin_lock_irqsave(&bgc->lock, flags);
224
225 bgc->dir |= bgc->pin2mask(bgc, gpio);
226 bgc->write_reg(bgc->reg_dir, bgc->dir);
227
228 spin_unlock_irqrestore(&bgc->lock, flags);
229
230 return 0;
231}
232
233static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
234{
235 struct bgpio_chip *bgc = to_bgpio_chip(gc);
236 unsigned long flags;
237
238 gc->set(gc, gpio, val);
239
240 spin_lock_irqsave(&bgc->lock, flags);
241
242 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
243 bgc->write_reg(bgc->reg_dir, bgc->dir);
244
245 spin_unlock_irqrestore(&bgc->lock, flags);
246
247 return 0;
248}
249
250static int bgpio_setup_accessors(struct device *dev,
251 struct bgpio_chip *bgc,
252 bool be)
253{
254
255 switch (bgc->bits) {
256 case 8:
257 bgc->read_reg = bgpio_read8;
258 bgc->write_reg = bgpio_write8;
259 break;
260 case 16:
261 bgc->read_reg = bgpio_read16;
262 bgc->write_reg = bgpio_write16;
263 break;
264 case 32:
265 bgc->read_reg = bgpio_read32;
266 bgc->write_reg = bgpio_write32;
267 break;
268#if BITS_PER_LONG >= 64
269 case 64:
270 bgc->read_reg = bgpio_read64;
271 bgc->write_reg = bgpio_write64;
272 break;
273#endif /* BITS_PER_LONG >= 64 */
274 default:
275 dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
276 return -EINVAL;
277 }
278
279 bgc->pin2mask = be ? bgpio_pin2mask_be : bgpio_pin2mask;
280
281 return 0;
282}
283
284/*
285 * Create the device and allocate the resources. For setting GPIO's there are
286 * three supported configurations:
287 *
288 * - single input/output register resource (named "dat").
289 * - set/clear pair (named "set" and "clr").
290 * - single output register resource and single input resource ("set" and
291 * dat").
292 *
293 * For the single output register, this drives a 1 by setting a bit and a zero
294 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
295 * in the set register and clears it by setting a bit in the clear register.
296 * The configuration is detected by which resources are present.
297 *
298 * For setting the GPIO direction, there are three supported configurations:
299 *
300 * - simple bidirection GPIO that requires no configuration.
301 * - an output direction register (named "dirout") where a 1 bit
302 * indicates the GPIO is an output.
303 * - an input direction register (named "dirin") where a 1 bit indicates
304 * the GPIO is an input.
305 */
306static int bgpio_setup_io(struct bgpio_chip *bgc,
307 void __iomem *dat,
308 void __iomem *set,
309 void __iomem *clr)
310{
311
312 bgc->reg_dat = dat;
313 if (!bgc->reg_dat)
314 return -EINVAL;
315
316 if (set && clr) {
317 bgc->reg_set = set;
318 bgc->reg_clr = clr;
319 bgc->gc.set = bgpio_set_with_clear;
320 } else if (set && !clr) {
321 bgc->reg_set = set;
322 bgc->gc.set = bgpio_set_set;
323 } else {
324 bgc->gc.set = bgpio_set;
325 }
326
327 bgc->gc.get = bgpio_get;
328
329 return 0;
330}
331
332static int bgpio_setup_direction(struct bgpio_chip *bgc,
333 void __iomem *dirout,
334 void __iomem *dirin)
335{
336 if (dirout && dirin) {
337 return -EINVAL;
338 } else if (dirout) {
339 bgc->reg_dir = dirout;
340 bgc->gc.direction_output = bgpio_dir_out;
341 bgc->gc.direction_input = bgpio_dir_in;
342 } else if (dirin) {
343 bgc->reg_dir = dirin;
344 bgc->gc.direction_output = bgpio_dir_out_inv;
345 bgc->gc.direction_input = bgpio_dir_in_inv;
346 } else {
347 bgc->gc.direction_output = bgpio_simple_dir_out;
348 bgc->gc.direction_input = bgpio_simple_dir_in;
349 }
350
351 return 0;
352}
353
354int __devexit bgpio_remove(struct bgpio_chip *bgc)
355{
356 int err = gpiochip_remove(&bgc->gc);
357
358 kfree(bgc);
359
360 return err;
361}
362EXPORT_SYMBOL_GPL(bgpio_remove);
363
364int __devinit bgpio_init(struct bgpio_chip *bgc,
365 struct device *dev,
366 unsigned long sz,
367 void __iomem *dat,
368 void __iomem *set,
369 void __iomem *clr,
370 void __iomem *dirout,
371 void __iomem *dirin,
372 bool big_endian)
373{
374 int ret;
375
376 if (!is_power_of_2(sz))
377 return -EINVAL;
378
379 bgc->bits = sz * 8;
380 if (bgc->bits > BITS_PER_LONG)
381 return -EINVAL;
382
383 spin_lock_init(&bgc->lock);
384 bgc->gc.dev = dev;
385 bgc->gc.label = dev_name(dev);
386 bgc->gc.base = -1;
387 bgc->gc.ngpio = bgc->bits;
388
389 ret = bgpio_setup_io(bgc, dat, set, clr);
390 if (ret)
391 return ret;
392
393 ret = bgpio_setup_accessors(dev, bgc, big_endian);
394 if (ret)
395 return ret;
396
397 ret = bgpio_setup_direction(bgc, dirout, dirin);
398 if (ret)
399 return ret;
400
401 bgc->data = bgc->read_reg(bgc->reg_dat);
402
403 return ret;
404}
405EXPORT_SYMBOL_GPL(bgpio_init);
406
407#ifdef CONFIG_GPIO_BASIC_MMIO
408
409static void __iomem *bgpio_map(struct platform_device *pdev,
410 const char *name,
411 resource_size_t sane_sz,
412 int *err)
413{
414 struct device *dev = &pdev->dev;
415 struct resource *r;
416 resource_size_t start;
417 resource_size_t sz;
418 void __iomem *ret;
419
420 *err = 0;
421
422 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
423 if (!r)
424 return NULL;
425
426 sz = resource_size(r);
427 if (sz != sane_sz) {
428 *err = -EINVAL;
429 return NULL;
430 }
431
432 start = r->start;
433 if (!devm_request_mem_region(dev, start, sz, r->name)) {
434 *err = -EBUSY;
435 return NULL;
436 }
437
438 ret = devm_ioremap(dev, start, sz);
439 if (!ret) {
440 *err = -ENOMEM;
441 return NULL;
442 }
443
444 return ret;
445}
446
447static int __devinit bgpio_pdev_probe(struct platform_device *pdev)
448{
449 struct device *dev = &pdev->dev;
450 struct resource *r;
451 void __iomem *dat;
452 void __iomem *set;
453 void __iomem *clr;
454 void __iomem *dirout;
455 void __iomem *dirin;
456 unsigned long sz;
457 bool be;
458 int err;
459 struct bgpio_chip *bgc;
460 struct bgpio_pdata *pdata = dev_get_platdata(dev);
461
462 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
463 if (!r)
464 return -EINVAL;
465
466 sz = resource_size(r);
467
468 dat = bgpio_map(pdev, "dat", sz, &err);
469 if (!dat)
470 return err ? err : -EINVAL;
471
472 set = bgpio_map(pdev, "set", sz, &err);
473 if (err)
474 return err;
475
476 clr = bgpio_map(pdev, "clr", sz, &err);
477 if (err)
478 return err;
479
480 dirout = bgpio_map(pdev, "dirout", sz, &err);
481 if (err)
482 return err;
483
484 dirin = bgpio_map(pdev, "dirin", sz, &err);
485 if (err)
486 return err;
487
488 be = !strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be");
489
490 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
491 if (!bgc)
492 return -ENOMEM;
493
494 err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, be);
495 if (err)
496 return err;
497
498 if (pdata) {
499 bgc->gc.base = pdata->base;
500 if (pdata->ngpio > 0)
501 bgc->gc.ngpio = pdata->ngpio;
502 }
503
504 platform_set_drvdata(pdev, bgc);
505
506 return gpiochip_add(&bgc->gc);
507}
508
509static int __devexit bgpio_pdev_remove(struct platform_device *pdev)
510{
511 struct bgpio_chip *bgc = platform_get_drvdata(pdev);
512
513 return bgpio_remove(bgc);
514}
515
516static const struct platform_device_id bgpio_id_table[] = {
517 { "basic-mmio-gpio", },
518 { "basic-mmio-gpio-be", },
519 {},
520};
521MODULE_DEVICE_TABLE(platform, bgpio_id_table);
522
523static struct platform_driver bgpio_driver = {
524 .driver = {
525 .name = "basic-mmio-gpio",
526 },
527 .id_table = bgpio_id_table,
528 .probe = bgpio_pdev_probe,
529 .remove = __devexit_p(bgpio_pdev_remove),
530};
531
532static int __init bgpio_platform_init(void)
533{
534 return platform_driver_register(&bgpio_driver);
535}
536module_init(bgpio_platform_init);
537
538static void __exit bgpio_platform_exit(void)
539{
540 platform_driver_unregister(&bgpio_driver);
541}
542module_exit(bgpio_platform_exit);
543
544#endif /* CONFIG_GPIO_BASIC_MMIO */
545
546MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
547MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
548MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/cs5535-gpio.c b/drivers/gpio/cs5535-gpio.c
index e23c06893d19..6e16cba56ad2 100644
--- a/drivers/gpio/cs5535-gpio.c
+++ b/drivers/gpio/cs5535-gpio.c
@@ -11,13 +11,13 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pci.h> 14#include <linux/platform_device.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/cs5535.h> 17#include <linux/cs5535.h>
18#include <asm/msr.h>
18 19
19#define DRV_NAME "cs5535-gpio" 20#define DRV_NAME "cs5535-gpio"
20#define GPIO_BAR 1
21 21
22/* 22/*
23 * Some GPIO pins 23 * Some GPIO pins
@@ -46,7 +46,7 @@ static struct cs5535_gpio_chip {
46 struct gpio_chip chip; 46 struct gpio_chip chip;
47 resource_size_t base; 47 resource_size_t base;
48 48
49 struct pci_dev *pdev; 49 struct platform_device *pdev;
50 spinlock_t lock; 50 spinlock_t lock;
51} cs5535_gpio_chip; 51} cs5535_gpio_chip;
52 52
@@ -56,6 +56,29 @@ static struct cs5535_gpio_chip {
56 * registers, see include/linux/cs5535.h. 56 * registers, see include/linux/cs5535.h.
57 */ 57 */
58 58
59static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
60 unsigned int reg)
61{
62 unsigned long addr = chip->base + 0x80 + reg;
63
64 /*
65 * According to the CS5536 errata (#36), after suspend
66 * a write to the high bank GPIO register will clear all
67 * non-selected bits; the recommended workaround is a
68 * read-modify-write operation.
69 *
70 * Don't apply this errata to the edge status GPIOs, as writing
71 * to their lower bits will clear them.
72 */
73 if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
74 if (val & 0xffff)
75 val |= (inl(addr) & 0xffff); /* ignore the high bits */
76 else
77 val |= (inl(addr) ^ (val >> 16));
78 }
79 outl(val, addr);
80}
81
59static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset, 82static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
60 unsigned int reg) 83 unsigned int reg)
61{ 84{
@@ -64,7 +87,7 @@ static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
64 outl(1 << offset, chip->base + reg); 87 outl(1 << offset, chip->base + reg);
65 else 88 else
66 /* high bank register */ 89 /* high bank register */
67 outl(1 << (offset - 16), chip->base + 0x80 + reg); 90 errata_outl(chip, 1 << (offset - 16), reg);
68} 91}
69 92
70void cs5535_gpio_set(unsigned offset, unsigned int reg) 93void cs5535_gpio_set(unsigned offset, unsigned int reg)
@@ -86,7 +109,7 @@ static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
86 outl(1 << (offset + 16), chip->base + reg); 109 outl(1 << (offset + 16), chip->base + reg);
87 else 110 else
88 /* high bank register */ 111 /* high bank register */
89 outl(1 << offset, chip->base + 0x80 + reg); 112 errata_outl(chip, 1 << offset, reg);
90} 113}
91 114
92void cs5535_gpio_clear(unsigned offset, unsigned int reg) 115void cs5535_gpio_clear(unsigned offset, unsigned int reg)
@@ -121,6 +144,57 @@ int cs5535_gpio_isset(unsigned offset, unsigned int reg)
121} 144}
122EXPORT_SYMBOL_GPL(cs5535_gpio_isset); 145EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
123 146
147int cs5535_gpio_set_irq(unsigned group, unsigned irq)
148{
149 uint32_t lo, hi;
150
151 if (group > 7 || irq > 15)
152 return -EINVAL;
153
154 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
155
156 lo &= ~(0xF << (group * 4));
157 lo |= (irq & 0xF) << (group * 4);
158
159 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
160 return 0;
161}
162EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
163
164void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
165{
166 struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
167 uint32_t shift = (offset % 8) * 4;
168 unsigned long flags;
169 uint32_t val;
170
171 if (offset >= 24)
172 offset = GPIO_MAP_W;
173 else if (offset >= 16)
174 offset = GPIO_MAP_Z;
175 else if (offset >= 8)
176 offset = GPIO_MAP_Y;
177 else
178 offset = GPIO_MAP_X;
179
180 spin_lock_irqsave(&chip->lock, flags);
181 val = inl(chip->base + offset);
182
183 /* Clear whatever was there before */
184 val &= ~(0xF << shift);
185
186 /* Set the new value */
187 val |= ((pair & 7) << shift);
188
189 /* Set the PME bit if this is a PME event */
190 if (pme)
191 val |= (1 << (shift + 3));
192
193 outl(val, chip->base + offset);
194 spin_unlock_irqrestore(&chip->lock, flags);
195}
196EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
197
124/* 198/*
125 * Generic gpio_chip API support. 199 * Generic gpio_chip API support.
126 */ 200 */
@@ -226,10 +300,10 @@ static struct cs5535_gpio_chip cs5535_gpio_chip = {
226 }, 300 },
227}; 301};
228 302
229static int __init cs5535_gpio_probe(struct pci_dev *pdev, 303static int __devinit cs5535_gpio_probe(struct platform_device *pdev)
230 const struct pci_device_id *pci_id)
231{ 304{
232 int err; 305 struct resource *res;
306 int err = -EIO;
233 ulong mask_orig = mask; 307 ulong mask_orig = mask;
234 308
235 /* There are two ways to get the GPIO base address; one is by 309 /* There are two ways to get the GPIO base address; one is by
@@ -239,25 +313,23 @@ static int __init cs5535_gpio_probe(struct pci_dev *pdev,
239 * it turns out to be unreliable in the face of crappy BIOSes, we 313 * it turns out to be unreliable in the face of crappy BIOSes, we
240 * can always go back to using MSRs.. */ 314 * can always go back to using MSRs.. */
241 315
242 err = pci_enable_device_io(pdev); 316 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
243 if (err) { 317 if (!res) {
244 dev_err(&pdev->dev, "can't enable device IO\n"); 318 dev_err(&pdev->dev, "can't fetch device resource info\n");
245 goto done; 319 goto done;
246 } 320 }
247 321
248 err = pci_request_region(pdev, GPIO_BAR, DRV_NAME); 322 if (!request_region(res->start, resource_size(res), pdev->name)) {
249 if (err) { 323 dev_err(&pdev->dev, "can't request region\n");
250 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
251 goto done; 324 goto done;
252 } 325 }
253 326
254 /* set up the driver-specific struct */ 327 /* set up the driver-specific struct */
255 cs5535_gpio_chip.base = pci_resource_start(pdev, GPIO_BAR); 328 cs5535_gpio_chip.base = res->start;
256 cs5535_gpio_chip.pdev = pdev; 329 cs5535_gpio_chip.pdev = pdev;
257 spin_lock_init(&cs5535_gpio_chip.lock); 330 spin_lock_init(&cs5535_gpio_chip.lock);
258 331
259 dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", GPIO_BAR, 332 dev_info(&pdev->dev, "reserved resource region %pR\n", res);
260 (unsigned long long) cs5535_gpio_chip.base);
261 333
262 /* mask out reserved pins */ 334 /* mask out reserved pins */
263 mask &= 0x1F7FFFFF; 335 mask &= 0x1F7FFFFF;
@@ -275,78 +347,49 @@ static int __init cs5535_gpio_probe(struct pci_dev *pdev,
275 if (err) 347 if (err)
276 goto release_region; 348 goto release_region;
277 349
278 dev_info(&pdev->dev, DRV_NAME ": GPIO support successfully loaded.\n"); 350 dev_info(&pdev->dev, "GPIO support successfully loaded.\n");
279 return 0; 351 return 0;
280 352
281release_region: 353release_region:
282 pci_release_region(pdev, GPIO_BAR); 354 release_region(res->start, resource_size(res));
283done: 355done:
284 return err; 356 return err;
285} 357}
286 358
287static void __exit cs5535_gpio_remove(struct pci_dev *pdev) 359static int __devexit cs5535_gpio_remove(struct platform_device *pdev)
288{ 360{
361 struct resource *r;
289 int err; 362 int err;
290 363
291 err = gpiochip_remove(&cs5535_gpio_chip.chip); 364 err = gpiochip_remove(&cs5535_gpio_chip.chip);
292 if (err) { 365 if (err) {
293 /* uhh? */ 366 /* uhh? */
294 dev_err(&pdev->dev, "unable to remove gpio_chip?\n"); 367 dev_err(&pdev->dev, "unable to remove gpio_chip?\n");
368 return err;
295 } 369 }
296 pci_release_region(pdev, GPIO_BAR);
297}
298
299static struct pci_device_id cs5535_gpio_pci_tbl[] = {
300 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
301 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
302 { 0, },
303};
304MODULE_DEVICE_TABLE(pci, cs5535_gpio_pci_tbl);
305 370
306/* 371 r = platform_get_resource(pdev, IORESOURCE_IO, 0);
307 * We can't use the standard PCI driver registration stuff here, since 372 release_region(r->start, resource_size(r));
308 * that allows only one driver to bind to each PCI device (and we want 373 return 0;
309 * multiple drivers to be able to bind to the device). Instead, manually
310 * scan for the PCI device, request a single region, and keep track of the
311 * devices that we're using.
312 */
313
314static int __init cs5535_gpio_scan_pci(void)
315{
316 struct pci_dev *pdev;
317 int err = -ENODEV;
318 int i;
319
320 for (i = 0; i < ARRAY_SIZE(cs5535_gpio_pci_tbl); i++) {
321 pdev = pci_get_device(cs5535_gpio_pci_tbl[i].vendor,
322 cs5535_gpio_pci_tbl[i].device, NULL);
323 if (pdev) {
324 err = cs5535_gpio_probe(pdev, &cs5535_gpio_pci_tbl[i]);
325 if (err)
326 pci_dev_put(pdev);
327
328 /* we only support a single CS5535/6 southbridge */
329 break;
330 }
331 }
332
333 return err;
334} 374}
335 375
336static void __exit cs5535_gpio_free_pci(void) 376static struct platform_driver cs5535_gpio_driver = {
337{ 377 .driver = {
338 cs5535_gpio_remove(cs5535_gpio_chip.pdev); 378 .name = DRV_NAME,
339 pci_dev_put(cs5535_gpio_chip.pdev); 379 .owner = THIS_MODULE,
340} 380 },
381 .probe = cs5535_gpio_probe,
382 .remove = __devexit_p(cs5535_gpio_remove),
383};
341 384
342static int __init cs5535_gpio_init(void) 385static int __init cs5535_gpio_init(void)
343{ 386{
344 return cs5535_gpio_scan_pci(); 387 return platform_driver_register(&cs5535_gpio_driver);
345} 388}
346 389
347static void __exit cs5535_gpio_exit(void) 390static void __exit cs5535_gpio_exit(void)
348{ 391{
349 cs5535_gpio_free_pci(); 392 platform_driver_unregister(&cs5535_gpio_driver);
350} 393}
351 394
352module_init(cs5535_gpio_init); 395module_init(cs5535_gpio_init);
@@ -355,3 +398,4 @@ module_exit(cs5535_gpio_exit);
355MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>"); 398MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
356MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver"); 399MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
357MODULE_LICENSE("GPL"); 400MODULE_LICENSE("GPL");
401MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/gpio/gpio-exynos4.c b/drivers/gpio/gpio-exynos4.c
new file mode 100644
index 000000000000..9029835112e7
--- /dev/null
+++ b/drivers/gpio/gpio-exynos4.c
@@ -0,0 +1,386 @@
1/* linux/arch/arm/mach-exynos4/gpiolib.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24int s3c_gpio_setpull_exynos4(struct s3c_gpio_chip *chip,
25 unsigned int off, s3c_gpio_pull_t pull)
26{
27 if (pull == S3C_GPIO_PULL_UP)
28 pull = 3;
29
30 return s3c_gpio_setpull_updown(chip, off, pull);
31}
32
33s3c_gpio_pull_t s3c_gpio_getpull_exynos4(struct s3c_gpio_chip *chip,
34 unsigned int off)
35{
36 s3c_gpio_pull_t pull;
37
38 pull = s3c_gpio_getpull_updown(chip, off);
39 if (pull == 3)
40 pull = S3C_GPIO_PULL_UP;
41
42 return pull;
43}
44
45static struct s3c_gpio_cfg gpio_cfg = {
46 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
47 .set_pull = s3c_gpio_setpull_exynos4,
48 .get_pull = s3c_gpio_getpull_exynos4,
49};
50
51static struct s3c_gpio_cfg gpio_cfg_noint = {
52 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
53 .set_pull = s3c_gpio_setpull_exynos4,
54 .get_pull = s3c_gpio_getpull_exynos4,
55};
56
57/*
58 * Following are the gpio banks in v310.
59 *
60 * The 'config' member when left to NULL, is initialized to the default
61 * structure gpio_cfg in the init function below.
62 *
63 * The 'base' member is also initialized in the init function below.
64 * Note: The initialization of 'base' member of s3c_gpio_chip structure
65 * uses the above macro and depends on the banks being listed in order here.
66 */
67static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
68 {
69 .chip = {
70 .base = EXYNOS4_GPA0(0),
71 .ngpio = EXYNOS4_GPIO_A0_NR,
72 .label = "GPA0",
73 },
74 }, {
75 .chip = {
76 .base = EXYNOS4_GPA1(0),
77 .ngpio = EXYNOS4_GPIO_A1_NR,
78 .label = "GPA1",
79 },
80 }, {
81 .chip = {
82 .base = EXYNOS4_GPB(0),
83 .ngpio = EXYNOS4_GPIO_B_NR,
84 .label = "GPB",
85 },
86 }, {
87 .chip = {
88 .base = EXYNOS4_GPC0(0),
89 .ngpio = EXYNOS4_GPIO_C0_NR,
90 .label = "GPC0",
91 },
92 }, {
93 .chip = {
94 .base = EXYNOS4_GPC1(0),
95 .ngpio = EXYNOS4_GPIO_C1_NR,
96 .label = "GPC1",
97 },
98 }, {
99 .chip = {
100 .base = EXYNOS4_GPD0(0),
101 .ngpio = EXYNOS4_GPIO_D0_NR,
102 .label = "GPD0",
103 },
104 }, {
105 .chip = {
106 .base = EXYNOS4_GPD1(0),
107 .ngpio = EXYNOS4_GPIO_D1_NR,
108 .label = "GPD1",
109 },
110 }, {
111 .chip = {
112 .base = EXYNOS4_GPE0(0),
113 .ngpio = EXYNOS4_GPIO_E0_NR,
114 .label = "GPE0",
115 },
116 }, {
117 .chip = {
118 .base = EXYNOS4_GPE1(0),
119 .ngpio = EXYNOS4_GPIO_E1_NR,
120 .label = "GPE1",
121 },
122 }, {
123 .chip = {
124 .base = EXYNOS4_GPE2(0),
125 .ngpio = EXYNOS4_GPIO_E2_NR,
126 .label = "GPE2",
127 },
128 }, {
129 .chip = {
130 .base = EXYNOS4_GPE3(0),
131 .ngpio = EXYNOS4_GPIO_E3_NR,
132 .label = "GPE3",
133 },
134 }, {
135 .chip = {
136 .base = EXYNOS4_GPE4(0),
137 .ngpio = EXYNOS4_GPIO_E4_NR,
138 .label = "GPE4",
139 },
140 }, {
141 .chip = {
142 .base = EXYNOS4_GPF0(0),
143 .ngpio = EXYNOS4_GPIO_F0_NR,
144 .label = "GPF0",
145 },
146 }, {
147 .chip = {
148 .base = EXYNOS4_GPF1(0),
149 .ngpio = EXYNOS4_GPIO_F1_NR,
150 .label = "GPF1",
151 },
152 }, {
153 .chip = {
154 .base = EXYNOS4_GPF2(0),
155 .ngpio = EXYNOS4_GPIO_F2_NR,
156 .label = "GPF2",
157 },
158 }, {
159 .chip = {
160 .base = EXYNOS4_GPF3(0),
161 .ngpio = EXYNOS4_GPIO_F3_NR,
162 .label = "GPF3",
163 },
164 },
165};
166
167static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
168 {
169 .chip = {
170 .base = EXYNOS4_GPJ0(0),
171 .ngpio = EXYNOS4_GPIO_J0_NR,
172 .label = "GPJ0",
173 },
174 }, {
175 .chip = {
176 .base = EXYNOS4_GPJ1(0),
177 .ngpio = EXYNOS4_GPIO_J1_NR,
178 .label = "GPJ1",
179 },
180 }, {
181 .chip = {
182 .base = EXYNOS4_GPK0(0),
183 .ngpio = EXYNOS4_GPIO_K0_NR,
184 .label = "GPK0",
185 },
186 }, {
187 .chip = {
188 .base = EXYNOS4_GPK1(0),
189 .ngpio = EXYNOS4_GPIO_K1_NR,
190 .label = "GPK1",
191 },
192 }, {
193 .chip = {
194 .base = EXYNOS4_GPK2(0),
195 .ngpio = EXYNOS4_GPIO_K2_NR,
196 .label = "GPK2",
197 },
198 }, {
199 .chip = {
200 .base = EXYNOS4_GPK3(0),
201 .ngpio = EXYNOS4_GPIO_K3_NR,
202 .label = "GPK3",
203 },
204 }, {
205 .chip = {
206 .base = EXYNOS4_GPL0(0),
207 .ngpio = EXYNOS4_GPIO_L0_NR,
208 .label = "GPL0",
209 },
210 }, {
211 .chip = {
212 .base = EXYNOS4_GPL1(0),
213 .ngpio = EXYNOS4_GPIO_L1_NR,
214 .label = "GPL1",
215 },
216 }, {
217 .chip = {
218 .base = EXYNOS4_GPL2(0),
219 .ngpio = EXYNOS4_GPIO_L2_NR,
220 .label = "GPL2",
221 },
222 }, {
223 .config = &gpio_cfg_noint,
224 .chip = {
225 .base = EXYNOS4_GPY0(0),
226 .ngpio = EXYNOS4_GPIO_Y0_NR,
227 .label = "GPY0",
228 },
229 }, {
230 .config = &gpio_cfg_noint,
231 .chip = {
232 .base = EXYNOS4_GPY1(0),
233 .ngpio = EXYNOS4_GPIO_Y1_NR,
234 .label = "GPY1",
235 },
236 }, {
237 .config = &gpio_cfg_noint,
238 .chip = {
239 .base = EXYNOS4_GPY2(0),
240 .ngpio = EXYNOS4_GPIO_Y2_NR,
241 .label = "GPY2",
242 },
243 }, {
244 .config = &gpio_cfg_noint,
245 .chip = {
246 .base = EXYNOS4_GPY3(0),
247 .ngpio = EXYNOS4_GPIO_Y3_NR,
248 .label = "GPY3",
249 },
250 }, {
251 .config = &gpio_cfg_noint,
252 .chip = {
253 .base = EXYNOS4_GPY4(0),
254 .ngpio = EXYNOS4_GPIO_Y4_NR,
255 .label = "GPY4",
256 },
257 }, {
258 .config = &gpio_cfg_noint,
259 .chip = {
260 .base = EXYNOS4_GPY5(0),
261 .ngpio = EXYNOS4_GPIO_Y5_NR,
262 .label = "GPY5",
263 },
264 }, {
265 .config = &gpio_cfg_noint,
266 .chip = {
267 .base = EXYNOS4_GPY6(0),
268 .ngpio = EXYNOS4_GPIO_Y6_NR,
269 .label = "GPY6",
270 },
271 }, {
272 .base = (S5P_VA_GPIO2 + 0xC00),
273 .config = &gpio_cfg_noint,
274 .irq_base = IRQ_EINT(0),
275 .chip = {
276 .base = EXYNOS4_GPX0(0),
277 .ngpio = EXYNOS4_GPIO_X0_NR,
278 .label = "GPX0",
279 .to_irq = samsung_gpiolib_to_irq,
280 },
281 }, {
282 .base = (S5P_VA_GPIO2 + 0xC20),
283 .config = &gpio_cfg_noint,
284 .irq_base = IRQ_EINT(8),
285 .chip = {
286 .base = EXYNOS4_GPX1(0),
287 .ngpio = EXYNOS4_GPIO_X1_NR,
288 .label = "GPX1",
289 .to_irq = samsung_gpiolib_to_irq,
290 },
291 }, {
292 .base = (S5P_VA_GPIO2 + 0xC40),
293 .config = &gpio_cfg_noint,
294 .irq_base = IRQ_EINT(16),
295 .chip = {
296 .base = EXYNOS4_GPX2(0),
297 .ngpio = EXYNOS4_GPIO_X2_NR,
298 .label = "GPX2",
299 .to_irq = samsung_gpiolib_to_irq,
300 },
301 }, {
302 .base = (S5P_VA_GPIO2 + 0xC60),
303 .config = &gpio_cfg_noint,
304 .irq_base = IRQ_EINT(24),
305 .chip = {
306 .base = EXYNOS4_GPX3(0),
307 .ngpio = EXYNOS4_GPIO_X3_NR,
308 .label = "GPX3",
309 .to_irq = samsung_gpiolib_to_irq,
310 },
311 },
312};
313
314static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
315 {
316 .chip = {
317 .base = EXYNOS4_GPZ(0),
318 .ngpio = EXYNOS4_GPIO_Z_NR,
319 .label = "GPZ",
320 },
321 },
322};
323
324static __init int exynos4_gpiolib_init(void)
325{
326 struct s3c_gpio_chip *chip;
327 int i;
328 int group = 0;
329 int nr_chips;
330
331 /* GPIO part 1 */
332
333 chip = exynos4_gpio_part1_4bit;
334 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
335
336 for (i = 0; i < nr_chips; i++, chip++) {
337 if (chip->config == NULL) {
338 chip->config = &gpio_cfg;
339 /* Assign the GPIO interrupt group */
340 chip->group = group++;
341 }
342 if (chip->base == NULL)
343 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
344 }
345
346 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
347
348 /* GPIO part 2 */
349
350 chip = exynos4_gpio_part2_4bit;
351 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
352
353 for (i = 0; i < nr_chips; i++, chip++) {
354 if (chip->config == NULL) {
355 chip->config = &gpio_cfg;
356 /* Assign the GPIO interrupt group */
357 chip->group = group++;
358 }
359 if (chip->base == NULL)
360 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
361 }
362
363 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
364
365 /* GPIO part 3 */
366
367 chip = exynos4_gpio_part3_4bit;
368 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
369
370 for (i = 0; i < nr_chips; i++, chip++) {
371 if (chip->config == NULL) {
372 chip->config = &gpio_cfg;
373 /* Assign the GPIO interrupt group */
374 chip->group = group++;
375 }
376 if (chip->base == NULL)
377 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
378 }
379
380 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
381 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
382 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
383
384 return 0;
385}
386core_initcall(exynos4_gpiolib_init);
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c
new file mode 100644
index 000000000000..2c212c732d76
--- /dev/null
+++ b/drivers/gpio/gpio-nomadik.c
@@ -0,0 +1,1087 @@
1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/gpio.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/slab.h>
26
27#include <asm/mach/irq.h>
28
29#include <plat/pincfg.h>
30#include <mach/hardware.h>
31#include <mach/gpio.h>
32
33/*
34 * The GPIO module in the Nomadik family of Systems-on-Chip is an
35 * AMBA device, managing 32 pins and alternate functions. The logic block
36 * is currently used in the Nomadik and ux500.
37 *
38 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
39 */
40
41#define NMK_GPIO_PER_CHIP 32
42
43struct nmk_gpio_chip {
44 struct gpio_chip chip;
45 void __iomem *addr;
46 struct clk *clk;
47 unsigned int bank;
48 unsigned int parent_irq;
49 int secondary_parent_irq;
50 u32 (*get_secondary_status)(unsigned int bank);
51 void (*set_ioforce)(bool enable);
52 spinlock_t lock;
53 bool sleepmode;
54 /* Keep track of configured edges */
55 u32 edge_rising;
56 u32 edge_falling;
57 u32 real_wake;
58 u32 rwimsc;
59 u32 fwimsc;
60 u32 slpm;
61 u32 enabled;
62 u32 pull_up;
63};
64
65static struct nmk_gpio_chip *
66nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
67
68static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
69
70#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
71
72static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
73 unsigned offset, int gpio_mode)
74{
75 u32 bit = 1 << offset;
76 u32 afunc, bfunc;
77
78 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
79 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
80 if (gpio_mode & NMK_GPIO_ALT_A)
81 afunc |= bit;
82 if (gpio_mode & NMK_GPIO_ALT_B)
83 bfunc |= bit;
84 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
85 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
86}
87
88static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
89 unsigned offset, enum nmk_gpio_slpm mode)
90{
91 u32 bit = 1 << offset;
92 u32 slpm;
93
94 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
95 if (mode == NMK_GPIO_SLPM_NOCHANGE)
96 slpm |= bit;
97 else
98 slpm &= ~bit;
99 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
100}
101
102static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
103 unsigned offset, enum nmk_gpio_pull pull)
104{
105 u32 bit = 1 << offset;
106 u32 pdis;
107
108 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
109 if (pull == NMK_GPIO_PULL_NONE) {
110 pdis |= bit;
111 nmk_chip->pull_up &= ~bit;
112 } else {
113 pdis &= ~bit;
114 }
115
116 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
117
118 if (pull == NMK_GPIO_PULL_UP) {
119 nmk_chip->pull_up |= bit;
120 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
121 } else if (pull == NMK_GPIO_PULL_DOWN) {
122 nmk_chip->pull_up &= ~bit;
123 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
124 }
125}
126
127static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
128 unsigned offset)
129{
130 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
131}
132
133static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
134 unsigned offset, int val)
135{
136 if (val)
137 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
138 else
139 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
140}
141
142static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
143 unsigned offset, int val)
144{
145 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
146 __nmk_gpio_set_output(nmk_chip, offset, val);
147}
148
149static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
150 unsigned offset, int gpio_mode,
151 bool glitch)
152{
153 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
154 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
155
156 if (glitch && nmk_chip->set_ioforce) {
157 u32 bit = BIT(offset);
158
159 /* Prevent spurious wakeups */
160 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
161 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
162
163 nmk_chip->set_ioforce(true);
164 }
165
166 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
167
168 if (glitch && nmk_chip->set_ioforce) {
169 nmk_chip->set_ioforce(false);
170
171 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
172 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
173 }
174}
175
176static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
177 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
178{
179 static const char *afnames[] = {
180 [NMK_GPIO_ALT_GPIO] = "GPIO",
181 [NMK_GPIO_ALT_A] = "A",
182 [NMK_GPIO_ALT_B] = "B",
183 [NMK_GPIO_ALT_C] = "C"
184 };
185 static const char *pullnames[] = {
186 [NMK_GPIO_PULL_NONE] = "none",
187 [NMK_GPIO_PULL_UP] = "up",
188 [NMK_GPIO_PULL_DOWN] = "down",
189 [3] /* illegal */ = "??"
190 };
191 static const char *slpmnames[] = {
192 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
193 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
194 };
195
196 int pin = PIN_NUM(cfg);
197 int pull = PIN_PULL(cfg);
198 int af = PIN_ALT(cfg);
199 int slpm = PIN_SLPM(cfg);
200 int output = PIN_DIR(cfg);
201 int val = PIN_VAL(cfg);
202 bool glitch = af == NMK_GPIO_ALT_C;
203
204 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
205 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
206 output ? "output " : "input",
207 output ? (val ? "high" : "low") : "");
208
209 if (sleep) {
210 int slpm_pull = PIN_SLPM_PULL(cfg);
211 int slpm_output = PIN_SLPM_DIR(cfg);
212 int slpm_val = PIN_SLPM_VAL(cfg);
213
214 af = NMK_GPIO_ALT_GPIO;
215
216 /*
217 * The SLPM_* values are normal values + 1 to allow zero to
218 * mean "same as normal".
219 */
220 if (slpm_pull)
221 pull = slpm_pull - 1;
222 if (slpm_output)
223 output = slpm_output - 1;
224 if (slpm_val)
225 val = slpm_val - 1;
226
227 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
228 pin,
229 slpm_pull ? pullnames[pull] : "same",
230 slpm_output ? (output ? "output" : "input") : "same",
231 slpm_val ? (val ? "high" : "low") : "same");
232 }
233
234 if (output)
235 __nmk_gpio_make_output(nmk_chip, offset, val);
236 else {
237 __nmk_gpio_make_input(nmk_chip, offset);
238 __nmk_gpio_set_pull(nmk_chip, offset, pull);
239 }
240
241 /*
242 * If we've backed up the SLPM registers (glitch workaround), modify
243 * the backups since they will be restored.
244 */
245 if (slpmregs) {
246 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
247 slpmregs[nmk_chip->bank] |= BIT(offset);
248 else
249 slpmregs[nmk_chip->bank] &= ~BIT(offset);
250 } else
251 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
252
253 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
254}
255
256/*
257 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
258 * - Save SLPM registers
259 * - Set SLPM=0 for the IOs you want to switch and others to 1
260 * - Configure the GPIO registers for the IOs that are being switched
261 * - Set IOFORCE=1
262 * - Modify the AFLSA/B registers for the IOs that are being switched
263 * - Set IOFORCE=0
264 * - Restore SLPM registers
265 * - Any spurious wake up event during switch sequence to be ignored and
266 * cleared
267 */
268static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
269{
270 int i;
271
272 for (i = 0; i < NUM_BANKS; i++) {
273 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
274 unsigned int temp = slpm[i];
275
276 if (!chip)
277 break;
278
279 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
280 writel(temp, chip->addr + NMK_GPIO_SLPC);
281 }
282}
283
284static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
285{
286 int i;
287
288 for (i = 0; i < NUM_BANKS; i++) {
289 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
290
291 if (!chip)
292 break;
293
294 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
295 }
296}
297
298static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
299{
300 static unsigned int slpm[NUM_BANKS];
301 unsigned long flags;
302 bool glitch = false;
303 int ret = 0;
304 int i;
305
306 for (i = 0; i < num; i++) {
307 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
308 glitch = true;
309 break;
310 }
311 }
312
313 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
314
315 if (glitch) {
316 memset(slpm, 0xff, sizeof(slpm));
317
318 for (i = 0; i < num; i++) {
319 int pin = PIN_NUM(cfgs[i]);
320 int offset = pin % NMK_GPIO_PER_CHIP;
321
322 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
323 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
324 }
325
326 nmk_gpio_glitch_slpm_init(slpm);
327 }
328
329 for (i = 0; i < num; i++) {
330 struct nmk_gpio_chip *nmk_chip;
331 int pin = PIN_NUM(cfgs[i]);
332
333 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
334 if (!nmk_chip) {
335 ret = -EINVAL;
336 break;
337 }
338
339 spin_lock(&nmk_chip->lock);
340 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
341 cfgs[i], sleep, glitch ? slpm : NULL);
342 spin_unlock(&nmk_chip->lock);
343 }
344
345 if (glitch)
346 nmk_gpio_glitch_slpm_restore(slpm);
347
348 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
349
350 return ret;
351}
352
353/**
354 * nmk_config_pin - configure a pin's mux attributes
355 * @cfg: pin confguration
356 *
357 * Configures a pin's mode (alternate function or GPIO), its pull up status,
358 * and its sleep mode based on the specified configuration. The @cfg is
359 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
360 * are constructed using, and can be further enhanced with, the macros in
361 * plat/pincfg.h.
362 *
363 * If a pin's mode is set to GPIO, it is configured as an input to avoid
364 * side-effects. The gpio can be manipulated later using standard GPIO API
365 * calls.
366 */
367int nmk_config_pin(pin_cfg_t cfg, bool sleep)
368{
369 return __nmk_config_pins(&cfg, 1, sleep);
370}
371EXPORT_SYMBOL(nmk_config_pin);
372
373/**
374 * nmk_config_pins - configure several pins at once
375 * @cfgs: array of pin configurations
376 * @num: number of elments in the array
377 *
378 * Configures several pins using nmk_config_pin(). Refer to that function for
379 * further information.
380 */
381int nmk_config_pins(pin_cfg_t *cfgs, int num)
382{
383 return __nmk_config_pins(cfgs, num, false);
384}
385EXPORT_SYMBOL(nmk_config_pins);
386
387int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
388{
389 return __nmk_config_pins(cfgs, num, true);
390}
391EXPORT_SYMBOL(nmk_config_pins_sleep);
392
393/**
394 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
395 * @gpio: pin number
396 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
397 *
398 * This register is actually in the pinmux layer, not the GPIO block itself.
399 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
400 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
401 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
402 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
403 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
404 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
405 *
406 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
407 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
408 * entered) regardless of the altfunction selected. Also wake-up detection is
409 * ENABLED.
410 *
411 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
412 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
413 * (for altfunction GPIO) or respective on-chip peripherals (for other
414 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
415 *
416 * Note that enable_irq_wake() will automatically enable wakeup detection.
417 */
418int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
419{
420 struct nmk_gpio_chip *nmk_chip;
421 unsigned long flags;
422
423 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
424 if (!nmk_chip)
425 return -EINVAL;
426
427 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
428 spin_lock(&nmk_chip->lock);
429
430 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
431
432 spin_unlock(&nmk_chip->lock);
433 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
434
435 return 0;
436}
437
438/**
439 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
440 * @gpio: pin number
441 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
442 *
443 * Enables/disables pull up/down on a specified pin. This only takes effect if
444 * the pin is configured as an input (either explicitly or by the alternate
445 * function).
446 *
447 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
448 * configured as an input. Otherwise, due to the way the controller registers
449 * work, this function will change the value output on the pin.
450 */
451int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
452{
453 struct nmk_gpio_chip *nmk_chip;
454 unsigned long flags;
455
456 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
457 if (!nmk_chip)
458 return -EINVAL;
459
460 spin_lock_irqsave(&nmk_chip->lock, flags);
461 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
462 spin_unlock_irqrestore(&nmk_chip->lock, flags);
463
464 return 0;
465}
466
467/* Mode functions */
468/**
469 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
470 * @gpio: pin number
471 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
472 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
473 *
474 * Sets the mode of the specified pin to one of the alternate functions or
475 * plain GPIO.
476 */
477int nmk_gpio_set_mode(int gpio, int gpio_mode)
478{
479 struct nmk_gpio_chip *nmk_chip;
480 unsigned long flags;
481
482 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
483 if (!nmk_chip)
484 return -EINVAL;
485
486 spin_lock_irqsave(&nmk_chip->lock, flags);
487 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
488 spin_unlock_irqrestore(&nmk_chip->lock, flags);
489
490 return 0;
491}
492EXPORT_SYMBOL(nmk_gpio_set_mode);
493
494int nmk_gpio_get_mode(int gpio)
495{
496 struct nmk_gpio_chip *nmk_chip;
497 u32 afunc, bfunc, bit;
498
499 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
500 if (!nmk_chip)
501 return -EINVAL;
502
503 bit = 1 << (gpio - nmk_chip->chip.base);
504
505 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
506 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
507
508 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
509}
510EXPORT_SYMBOL(nmk_gpio_get_mode);
511
512
513/* IRQ functions */
514static inline int nmk_gpio_get_bitmask(int gpio)
515{
516 return 1 << (gpio % 32);
517}
518
519static void nmk_gpio_irq_ack(struct irq_data *d)
520{
521 int gpio;
522 struct nmk_gpio_chip *nmk_chip;
523
524 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
525 nmk_chip = irq_data_get_irq_chip_data(d);
526 if (!nmk_chip)
527 return;
528 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
529}
530
531enum nmk_gpio_irq_type {
532 NORMAL,
533 WAKE,
534};
535
536static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
537 int gpio, enum nmk_gpio_irq_type which,
538 bool enable)
539{
540 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
541 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
542 u32 bitmask = nmk_gpio_get_bitmask(gpio);
543 u32 reg;
544
545 /* we must individually set/clear the two edges */
546 if (nmk_chip->edge_rising & bitmask) {
547 reg = readl(nmk_chip->addr + rimsc);
548 if (enable)
549 reg |= bitmask;
550 else
551 reg &= ~bitmask;
552 writel(reg, nmk_chip->addr + rimsc);
553 }
554 if (nmk_chip->edge_falling & bitmask) {
555 reg = readl(nmk_chip->addr + fimsc);
556 if (enable)
557 reg |= bitmask;
558 else
559 reg &= ~bitmask;
560 writel(reg, nmk_chip->addr + fimsc);
561 }
562}
563
564static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
565 int gpio, bool on)
566{
567 if (nmk_chip->sleepmode) {
568 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
569 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
570 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
571 }
572
573 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
574}
575
576static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
577{
578 int gpio;
579 struct nmk_gpio_chip *nmk_chip;
580 unsigned long flags;
581 u32 bitmask;
582
583 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
584 nmk_chip = irq_data_get_irq_chip_data(d);
585 bitmask = nmk_gpio_get_bitmask(gpio);
586 if (!nmk_chip)
587 return -EINVAL;
588
589 if (enable)
590 nmk_chip->enabled |= bitmask;
591 else
592 nmk_chip->enabled &= ~bitmask;
593
594 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
595 spin_lock(&nmk_chip->lock);
596
597 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
598
599 if (!(nmk_chip->real_wake & bitmask))
600 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
601
602 spin_unlock(&nmk_chip->lock);
603 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
604
605 return 0;
606}
607
608static void nmk_gpio_irq_mask(struct irq_data *d)
609{
610 nmk_gpio_irq_maskunmask(d, false);
611}
612
613static void nmk_gpio_irq_unmask(struct irq_data *d)
614{
615 nmk_gpio_irq_maskunmask(d, true);
616}
617
618static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
619{
620 struct nmk_gpio_chip *nmk_chip;
621 unsigned long flags;
622 u32 bitmask;
623 int gpio;
624
625 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
626 nmk_chip = irq_data_get_irq_chip_data(d);
627 if (!nmk_chip)
628 return -EINVAL;
629 bitmask = nmk_gpio_get_bitmask(gpio);
630
631 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
632 spin_lock(&nmk_chip->lock);
633
634 if (!(nmk_chip->enabled & bitmask))
635 __nmk_gpio_set_wake(nmk_chip, gpio, on);
636
637 if (on)
638 nmk_chip->real_wake |= bitmask;
639 else
640 nmk_chip->real_wake &= ~bitmask;
641
642 spin_unlock(&nmk_chip->lock);
643 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
644
645 return 0;
646}
647
648static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
649{
650 bool enabled, wake = irqd_is_wakeup_set(d);
651 int gpio;
652 struct nmk_gpio_chip *nmk_chip;
653 unsigned long flags;
654 u32 bitmask;
655
656 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
657 nmk_chip = irq_data_get_irq_chip_data(d);
658 bitmask = nmk_gpio_get_bitmask(gpio);
659 if (!nmk_chip)
660 return -EINVAL;
661
662 if (type & IRQ_TYPE_LEVEL_HIGH)
663 return -EINVAL;
664 if (type & IRQ_TYPE_LEVEL_LOW)
665 return -EINVAL;
666
667 enabled = nmk_chip->enabled & bitmask;
668
669 spin_lock_irqsave(&nmk_chip->lock, flags);
670
671 if (enabled)
672 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
673
674 if (enabled || wake)
675 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
676
677 nmk_chip->edge_rising &= ~bitmask;
678 if (type & IRQ_TYPE_EDGE_RISING)
679 nmk_chip->edge_rising |= bitmask;
680
681 nmk_chip->edge_falling &= ~bitmask;
682 if (type & IRQ_TYPE_EDGE_FALLING)
683 nmk_chip->edge_falling |= bitmask;
684
685 if (enabled)
686 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
687
688 if (enabled || wake)
689 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
690
691 spin_unlock_irqrestore(&nmk_chip->lock, flags);
692
693 return 0;
694}
695
696static struct irq_chip nmk_gpio_irq_chip = {
697 .name = "Nomadik-GPIO",
698 .irq_ack = nmk_gpio_irq_ack,
699 .irq_mask = nmk_gpio_irq_mask,
700 .irq_unmask = nmk_gpio_irq_unmask,
701 .irq_set_type = nmk_gpio_irq_set_type,
702 .irq_set_wake = nmk_gpio_irq_set_wake,
703};
704
705static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
706 u32 status)
707{
708 struct nmk_gpio_chip *nmk_chip;
709 struct irq_chip *host_chip = irq_get_chip(irq);
710 unsigned int first_irq;
711
712 chained_irq_enter(host_chip, desc);
713
714 nmk_chip = irq_get_handler_data(irq);
715 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
716 while (status) {
717 int bit = __ffs(status);
718
719 generic_handle_irq(first_irq + bit);
720 status &= ~BIT(bit);
721 }
722
723 chained_irq_exit(host_chip, desc);
724}
725
726static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
727{
728 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
729 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
730
731 __nmk_gpio_irq_handler(irq, desc, status);
732}
733
734static void nmk_gpio_secondary_irq_handler(unsigned int irq,
735 struct irq_desc *desc)
736{
737 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
738 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
739
740 __nmk_gpio_irq_handler(irq, desc, status);
741}
742
743static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
744{
745 unsigned int first_irq;
746 int i;
747
748 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
749 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
750 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
751 handle_edge_irq);
752 set_irq_flags(i, IRQF_VALID);
753 irq_set_chip_data(i, nmk_chip);
754 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
755 }
756
757 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
758 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
759
760 if (nmk_chip->secondary_parent_irq >= 0) {
761 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
762 nmk_gpio_secondary_irq_handler);
763 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
764 }
765
766 return 0;
767}
768
769/* I/O Functions */
770static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
771{
772 struct nmk_gpio_chip *nmk_chip =
773 container_of(chip, struct nmk_gpio_chip, chip);
774
775 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
776 return 0;
777}
778
779static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
780{
781 struct nmk_gpio_chip *nmk_chip =
782 container_of(chip, struct nmk_gpio_chip, chip);
783 u32 bit = 1 << offset;
784
785 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
786}
787
788static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
789 int val)
790{
791 struct nmk_gpio_chip *nmk_chip =
792 container_of(chip, struct nmk_gpio_chip, chip);
793
794 __nmk_gpio_set_output(nmk_chip, offset, val);
795}
796
797static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
798 int val)
799{
800 struct nmk_gpio_chip *nmk_chip =
801 container_of(chip, struct nmk_gpio_chip, chip);
802
803 __nmk_gpio_make_output(nmk_chip, offset, val);
804
805 return 0;
806}
807
808static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
809{
810 struct nmk_gpio_chip *nmk_chip =
811 container_of(chip, struct nmk_gpio_chip, chip);
812
813 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
814}
815
816#ifdef CONFIG_DEBUG_FS
817
818#include <linux/seq_file.h>
819
820static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
821{
822 int mode;
823 unsigned i;
824 unsigned gpio = chip->base;
825 int is_out;
826 struct nmk_gpio_chip *nmk_chip =
827 container_of(chip, struct nmk_gpio_chip, chip);
828 const char *modes[] = {
829 [NMK_GPIO_ALT_GPIO] = "gpio",
830 [NMK_GPIO_ALT_A] = "altA",
831 [NMK_GPIO_ALT_B] = "altB",
832 [NMK_GPIO_ALT_C] = "altC",
833 };
834
835 for (i = 0; i < chip->ngpio; i++, gpio++) {
836 const char *label = gpiochip_is_requested(chip, i);
837 bool pull;
838 u32 bit = 1 << i;
839
840 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
841 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
842 mode = nmk_gpio_get_mode(gpio);
843 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
844 gpio, label ?: "(none)",
845 is_out ? "out" : "in ",
846 chip->get
847 ? (chip->get(chip, i) ? "hi" : "lo")
848 : "? ",
849 (mode < 0) ? "unknown" : modes[mode],
850 pull ? "pull" : "none");
851
852 if (label && !is_out) {
853 int irq = gpio_to_irq(gpio);
854 struct irq_desc *desc = irq_to_desc(irq);
855
856 /* This races with request_irq(), set_irq_type(),
857 * and set_irq_wake() ... but those are "rare".
858 */
859 if (irq >= 0 && desc->action) {
860 char *trigger;
861 u32 bitmask = nmk_gpio_get_bitmask(gpio);
862
863 if (nmk_chip->edge_rising & bitmask)
864 trigger = "edge-rising";
865 else if (nmk_chip->edge_falling & bitmask)
866 trigger = "edge-falling";
867 else
868 trigger = "edge-undefined";
869
870 seq_printf(s, " irq-%d %s%s",
871 irq, trigger,
872 irqd_is_wakeup_set(&desc->irq_data)
873 ? " wakeup" : "");
874 }
875 }
876
877 seq_printf(s, "\n");
878 }
879}
880
881#else
882#define nmk_gpio_dbg_show NULL
883#endif
884
885/* This structure is replicated for each GPIO block allocated at probe time */
886static struct gpio_chip nmk_gpio_template = {
887 .direction_input = nmk_gpio_make_input,
888 .get = nmk_gpio_get_input,
889 .direction_output = nmk_gpio_make_output,
890 .set = nmk_gpio_set_output,
891 .to_irq = nmk_gpio_to_irq,
892 .dbg_show = nmk_gpio_dbg_show,
893 .can_sleep = 0,
894};
895
896/*
897 * Called from the suspend/resume path to only keep the real wakeup interrupts
898 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
899 * and not the rest of the interrupts which we needed to have as wakeups for
900 * cpuidle.
901 *
902 * PM ops are not used since this needs to be done at the end, after all the
903 * other drivers are done with their suspend callbacks.
904 */
905void nmk_gpio_wakeups_suspend(void)
906{
907 int i;
908
909 for (i = 0; i < NUM_BANKS; i++) {
910 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
911
912 if (!chip)
913 break;
914
915 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
916 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
917
918 writel(chip->rwimsc & chip->real_wake,
919 chip->addr + NMK_GPIO_RWIMSC);
920 writel(chip->fwimsc & chip->real_wake,
921 chip->addr + NMK_GPIO_FWIMSC);
922
923 if (chip->sleepmode) {
924 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
925
926 /* 0 -> wakeup enable */
927 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
928 }
929 }
930}
931
932void nmk_gpio_wakeups_resume(void)
933{
934 int i;
935
936 for (i = 0; i < NUM_BANKS; i++) {
937 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
938
939 if (!chip)
940 break;
941
942 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
943 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
944
945 if (chip->sleepmode)
946 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
947 }
948}
949
950/*
951 * Read the pull up/pull down status.
952 * A bit set in 'pull_up' means that pull up
953 * is selected if pull is enabled in PDIS register.
954 * Note: only pull up/down set via this driver can
955 * be detected due to HW limitations.
956 */
957void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
958{
959 if (gpio_bank < NUM_BANKS) {
960 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
961
962 if (!chip)
963 return;
964
965 *pull_up = chip->pull_up;
966 }
967}
968
969static int __devinit nmk_gpio_probe(struct platform_device *dev)
970{
971 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
972 struct nmk_gpio_chip *nmk_chip;
973 struct gpio_chip *chip;
974 struct resource *res;
975 struct clk *clk;
976 int secondary_irq;
977 int irq;
978 int ret;
979
980 if (!pdata)
981 return -ENODEV;
982
983 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
984 if (!res) {
985 ret = -ENOENT;
986 goto out;
987 }
988
989 irq = platform_get_irq(dev, 0);
990 if (irq < 0) {
991 ret = irq;
992 goto out;
993 }
994
995 secondary_irq = platform_get_irq(dev, 1);
996 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
997 ret = -EINVAL;
998 goto out;
999 }
1000
1001 if (request_mem_region(res->start, resource_size(res),
1002 dev_name(&dev->dev)) == NULL) {
1003 ret = -EBUSY;
1004 goto out;
1005 }
1006
1007 clk = clk_get(&dev->dev, NULL);
1008 if (IS_ERR(clk)) {
1009 ret = PTR_ERR(clk);
1010 goto out_release;
1011 }
1012
1013 clk_enable(clk);
1014
1015 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1016 if (!nmk_chip) {
1017 ret = -ENOMEM;
1018 goto out_clk;
1019 }
1020 /*
1021 * The virt address in nmk_chip->addr is in the nomadik register space,
1022 * so we can simply convert the resource address, without remapping
1023 */
1024 nmk_chip->bank = dev->id;
1025 nmk_chip->clk = clk;
1026 nmk_chip->addr = io_p2v(res->start);
1027 nmk_chip->chip = nmk_gpio_template;
1028 nmk_chip->parent_irq = irq;
1029 nmk_chip->secondary_parent_irq = secondary_irq;
1030 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1031 nmk_chip->set_ioforce = pdata->set_ioforce;
1032 nmk_chip->sleepmode = pdata->supports_sleepmode;
1033 spin_lock_init(&nmk_chip->lock);
1034
1035 chip = &nmk_chip->chip;
1036 chip->base = pdata->first_gpio;
1037 chip->ngpio = pdata->num_gpio;
1038 chip->label = pdata->name ?: dev_name(&dev->dev);
1039 chip->dev = &dev->dev;
1040 chip->owner = THIS_MODULE;
1041
1042 ret = gpiochip_add(&nmk_chip->chip);
1043 if (ret)
1044 goto out_free;
1045
1046 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1047
1048 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1049 platform_set_drvdata(dev, nmk_chip);
1050
1051 nmk_gpio_init_irq(nmk_chip);
1052
1053 dev_info(&dev->dev, "Bits %i-%i at address %p\n",
1054 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
1055 return 0;
1056
1057out_free:
1058 kfree(nmk_chip);
1059out_clk:
1060 clk_disable(clk);
1061 clk_put(clk);
1062out_release:
1063 release_mem_region(res->start, resource_size(res));
1064out:
1065 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1066 pdata->first_gpio, pdata->first_gpio+31);
1067 return ret;
1068}
1069
1070static struct platform_driver nmk_gpio_driver = {
1071 .driver = {
1072 .owner = THIS_MODULE,
1073 .name = "gpio",
1074 },
1075 .probe = nmk_gpio_probe,
1076};
1077
1078static int __init nmk_gpio_init(void)
1079{
1080 return platform_driver_register(&nmk_gpio_driver);
1081}
1082
1083core_initcall(nmk_gpio_init);
1084
1085MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1086MODULE_DESCRIPTION("Nomadik GPIO Driver");
1087MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
new file mode 100644
index 000000000000..35bebde23e83
--- /dev/null
+++ b/drivers/gpio/gpio-omap.c
@@ -0,0 +1,2009 @@
1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <mach/irqs.h>
28#include <mach/gpio.h>
29#include <asm/mach/irq.h>
30
31struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup;
39 u32 saved_wakeup;
40#endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57};
58
59#ifdef CONFIG_ARCH_OMAP3
60struct omap3_gpio_regs {
61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
71};
72
73static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
74#endif
75
76/*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80static struct gpio_bank *gpio_bank;
81
82static int bank_width;
83
84/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count;
86
87static inline struct gpio_bank *get_gpio_bank(int gpio)
88{
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110}
111
112static inline int get_gpio_index(int gpio)
113{
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{
159 void __iomem *reg = bank->base;
160 u32 l;
161
162 switch (bank->method) {
163#ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177#endif
178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182#endif
183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187#endif
188#if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192#endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203}
204
205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206{
207 void __iomem *reg = bank->base;
208 u32 l = 0;
209
210 switch (bank->method) {
211#ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239#endif
240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258#endif
259#ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267#endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg);
273}
274
275static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
276{
277 void __iomem *reg;
278
279 if (check_gpio(gpio) < 0)
280 return -EINVAL;
281 reg = bank->base;
282 switch (bank->method) {
283#ifdef CONFIG_ARCH_OMAP1
284 case METHOD_MPUIO:
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302#endif
303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307#endif
308#ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312#endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318}
319
320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321{
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329#ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348#endif
349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358#endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364}
365
366#define MOD_REG_BIT(reg, bit_mask, set) \
367do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372} while(0)
373
374/**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385{
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
390 if (!bank->dbck_flag)
391 return;
392
393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
419 clk_enable(bank->dbck);
420 } else {
421 val &= ~l;
422 clk_disable(bank->dbck);
423 }
424 bank->dbck_enable_mask = val;
425
426 __raw_writel(val, reg);
427}
428
429#ifdef CONFIG_ARCH_OMAP2PLUS
430static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
432{
433 void __iomem *base = bank->base;
434 u32 gpio_bit = 1 << gpio;
435
436 if (cpu_is_omap44xx()) {
437 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
438 trigger & IRQ_TYPE_LEVEL_LOW);
439 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
440 trigger & IRQ_TYPE_LEVEL_HIGH);
441 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
442 trigger & IRQ_TYPE_EDGE_RISING);
443 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
444 trigger & IRQ_TYPE_EDGE_FALLING);
445 } else {
446 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
447 trigger & IRQ_TYPE_LEVEL_LOW);
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
449 trigger & IRQ_TYPE_LEVEL_HIGH);
450 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
451 trigger & IRQ_TYPE_EDGE_RISING);
452 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
453 trigger & IRQ_TYPE_EDGE_FALLING);
454 }
455 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
456 if (cpu_is_omap44xx()) {
457 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
458 trigger != 0);
459 } else {
460 /*
461 * GPIO wakeup request can only be generated on edge
462 * transitions
463 */
464 if (trigger & IRQ_TYPE_EDGE_BOTH)
465 __raw_writel(1 << gpio, bank->base
466 + OMAP24XX_GPIO_SETWKUENA);
467 else
468 __raw_writel(1 << gpio, bank->base
469 + OMAP24XX_GPIO_CLEARWKUENA);
470 }
471 }
472 /* This part needs to be executed always for OMAP{34xx, 44xx} */
473 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
474 (bank->non_wakeup_gpios & gpio_bit)) {
475 /*
476 * Log the edge gpio and manually trigger the IRQ
477 * after resume if the input level changes
478 * to avoid irq lost during PER RET/OFF mode
479 * Applies for omap2 non-wakeup gpio and all omap3 gpios
480 */
481 if (trigger & IRQ_TYPE_EDGE_BOTH)
482 bank->enabled_non_wakeup_gpios |= gpio_bit;
483 else
484 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
485 }
486
487 if (cpu_is_omap44xx()) {
488 bank->level_mask =
489 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
490 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
491 } else {
492 bank->level_mask =
493 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
494 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
495 }
496}
497#endif
498
499#ifdef CONFIG_ARCH_OMAP1
500/*
501 * This only applies to chips that can't do both rising and falling edge
502 * detection at once. For all other chips, this function is a noop.
503 */
504static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
505{
506 void __iomem *reg = bank->base;
507 u32 l = 0;
508
509 switch (bank->method) {
510 case METHOD_MPUIO:
511 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
512 break;
513#ifdef CONFIG_ARCH_OMAP15XX
514 case METHOD_GPIO_1510:
515 reg += OMAP1510_GPIO_INT_CONTROL;
516 break;
517#endif
518#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
519 case METHOD_GPIO_7XX:
520 reg += OMAP7XX_GPIO_INT_CONTROL;
521 break;
522#endif
523 default:
524 return;
525 }
526
527 l = __raw_readl(reg);
528 if ((l >> gpio) & 1)
529 l &= ~(1 << gpio);
530 else
531 l |= 1 << gpio;
532
533 __raw_writel(l, reg);
534}
535#endif
536
537static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
538{
539 void __iomem *reg = bank->base;
540 u32 l = 0;
541
542 switch (bank->method) {
543#ifdef CONFIG_ARCH_OMAP1
544 case METHOD_MPUIO:
545 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
546 l = __raw_readl(reg);
547 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
548 bank->toggle_mask |= 1 << gpio;
549 if (trigger & IRQ_TYPE_EDGE_RISING)
550 l |= 1 << gpio;
551 else if (trigger & IRQ_TYPE_EDGE_FALLING)
552 l &= ~(1 << gpio);
553 else
554 goto bad;
555 break;
556#endif
557#ifdef CONFIG_ARCH_OMAP15XX
558 case METHOD_GPIO_1510:
559 reg += OMAP1510_GPIO_INT_CONTROL;
560 l = __raw_readl(reg);
561 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
562 bank->toggle_mask |= 1 << gpio;
563 if (trigger & IRQ_TYPE_EDGE_RISING)
564 l |= 1 << gpio;
565 else if (trigger & IRQ_TYPE_EDGE_FALLING)
566 l &= ~(1 << gpio);
567 else
568 goto bad;
569 break;
570#endif
571#ifdef CONFIG_ARCH_OMAP16XX
572 case METHOD_GPIO_1610:
573 if (gpio & 0x08)
574 reg += OMAP1610_GPIO_EDGE_CTRL2;
575 else
576 reg += OMAP1610_GPIO_EDGE_CTRL1;
577 gpio &= 0x07;
578 l = __raw_readl(reg);
579 l &= ~(3 << (gpio << 1));
580 if (trigger & IRQ_TYPE_EDGE_RISING)
581 l |= 2 << (gpio << 1);
582 if (trigger & IRQ_TYPE_EDGE_FALLING)
583 l |= 1 << (gpio << 1);
584 if (trigger)
585 /* Enable wake-up during idle for dynamic tick */
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
587 else
588 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
589 break;
590#endif
591#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
592 case METHOD_GPIO_7XX:
593 reg += OMAP7XX_GPIO_INT_CONTROL;
594 l = __raw_readl(reg);
595 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
596 bank->toggle_mask |= 1 << gpio;
597 if (trigger & IRQ_TYPE_EDGE_RISING)
598 l |= 1 << gpio;
599 else if (trigger & IRQ_TYPE_EDGE_FALLING)
600 l &= ~(1 << gpio);
601 else
602 goto bad;
603 break;
604#endif
605#ifdef CONFIG_ARCH_OMAP2PLUS
606 case METHOD_GPIO_24XX:
607 case METHOD_GPIO_44XX:
608 set_24xx_gpio_triggering(bank, gpio, trigger);
609 return 0;
610#endif
611 default:
612 goto bad;
613 }
614 __raw_writel(l, reg);
615 return 0;
616bad:
617 return -EINVAL;
618}
619
620static int gpio_irq_type(struct irq_data *d, unsigned type)
621{
622 struct gpio_bank *bank;
623 unsigned gpio;
624 int retval;
625 unsigned long flags;
626
627 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
628 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
629 else
630 gpio = d->irq - IH_GPIO_BASE;
631
632 if (check_gpio(gpio) < 0)
633 return -EINVAL;
634
635 if (type & ~IRQ_TYPE_SENSE_MASK)
636 return -EINVAL;
637
638 /* OMAP1 allows only only edge triggering */
639 if (!cpu_class_is_omap2()
640 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
641 return -EINVAL;
642
643 bank = irq_data_get_irq_chip_data(d);
644 spin_lock_irqsave(&bank->lock, flags);
645 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
646 spin_unlock_irqrestore(&bank->lock, flags);
647
648 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
649 __irq_set_handler_locked(d->irq, handle_level_irq);
650 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
651 __irq_set_handler_locked(d->irq, handle_edge_irq);
652
653 return retval;
654}
655
656static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657{
658 void __iomem *reg = bank->base;
659
660 switch (bank->method) {
661#ifdef CONFIG_ARCH_OMAP1
662 case METHOD_MPUIO:
663 /* MPUIO irqstatus is reset by reading the status register,
664 * so do nothing here */
665 return;
666#endif
667#ifdef CONFIG_ARCH_OMAP15XX
668 case METHOD_GPIO_1510:
669 reg += OMAP1510_GPIO_INT_STATUS;
670 break;
671#endif
672#ifdef CONFIG_ARCH_OMAP16XX
673 case METHOD_GPIO_1610:
674 reg += OMAP1610_GPIO_IRQSTATUS1;
675 break;
676#endif
677#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
678 case METHOD_GPIO_7XX:
679 reg += OMAP7XX_GPIO_INT_STATUS;
680 break;
681#endif
682#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
683 case METHOD_GPIO_24XX:
684 reg += OMAP24XX_GPIO_IRQSTATUS1;
685 break;
686#endif
687#if defined(CONFIG_ARCH_OMAP4)
688 case METHOD_GPIO_44XX:
689 reg += OMAP4_GPIO_IRQSTATUS0;
690 break;
691#endif
692 default:
693 WARN_ON(1);
694 return;
695 }
696 __raw_writel(gpio_mask, reg);
697
698 /* Workaround for clearing DSP GPIO interrupts to allow retention */
699 if (cpu_is_omap24xx() || cpu_is_omap34xx())
700 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
701 else if (cpu_is_omap44xx())
702 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
703
704 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
705 __raw_writel(gpio_mask, reg);
706
707 /* Flush posted write for the irq status to avoid spurious interrupts */
708 __raw_readl(reg);
709 }
710}
711
712static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
713{
714 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
715}
716
717static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
718{
719 void __iomem *reg = bank->base;
720 int inv = 0;
721 u32 l;
722 u32 mask;
723
724 switch (bank->method) {
725#ifdef CONFIG_ARCH_OMAP1
726 case METHOD_MPUIO:
727 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
728 mask = 0xffff;
729 inv = 1;
730 break;
731#endif
732#ifdef CONFIG_ARCH_OMAP15XX
733 case METHOD_GPIO_1510:
734 reg += OMAP1510_GPIO_INT_MASK;
735 mask = 0xffff;
736 inv = 1;
737 break;
738#endif
739#ifdef CONFIG_ARCH_OMAP16XX
740 case METHOD_GPIO_1610:
741 reg += OMAP1610_GPIO_IRQENABLE1;
742 mask = 0xffff;
743 break;
744#endif
745#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
746 case METHOD_GPIO_7XX:
747 reg += OMAP7XX_GPIO_INT_MASK;
748 mask = 0xffffffff;
749 inv = 1;
750 break;
751#endif
752#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
753 case METHOD_GPIO_24XX:
754 reg += OMAP24XX_GPIO_IRQENABLE1;
755 mask = 0xffffffff;
756 break;
757#endif
758#if defined(CONFIG_ARCH_OMAP4)
759 case METHOD_GPIO_44XX:
760 reg += OMAP4_GPIO_IRQSTATUSSET0;
761 mask = 0xffffffff;
762 break;
763#endif
764 default:
765 WARN_ON(1);
766 return 0;
767 }
768
769 l = __raw_readl(reg);
770 if (inv)
771 l = ~l;
772 l &= mask;
773 return l;
774}
775
776static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
777{
778 void __iomem *reg = bank->base;
779 u32 l;
780
781 switch (bank->method) {
782#ifdef CONFIG_ARCH_OMAP1
783 case METHOD_MPUIO:
784 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
785 l = __raw_readl(reg);
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
791#endif
792#ifdef CONFIG_ARCH_OMAP15XX
793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_MASK;
795 l = __raw_readl(reg);
796 if (enable)
797 l &= ~(gpio_mask);
798 else
799 l |= gpio_mask;
800 break;
801#endif
802#ifdef CONFIG_ARCH_OMAP16XX
803 case METHOD_GPIO_1610:
804 if (enable)
805 reg += OMAP1610_GPIO_SET_IRQENABLE1;
806 else
807 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
808 l = gpio_mask;
809 break;
810#endif
811#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
812 case METHOD_GPIO_7XX:
813 reg += OMAP7XX_GPIO_INT_MASK;
814 l = __raw_readl(reg);
815 if (enable)
816 l &= ~(gpio_mask);
817 else
818 l |= gpio_mask;
819 break;
820#endif
821#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
822 case METHOD_GPIO_24XX:
823 if (enable)
824 reg += OMAP24XX_GPIO_SETIRQENABLE1;
825 else
826 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
827 l = gpio_mask;
828 break;
829#endif
830#ifdef CONFIG_ARCH_OMAP4
831 case METHOD_GPIO_44XX:
832 if (enable)
833 reg += OMAP4_GPIO_IRQSTATUSSET0;
834 else
835 reg += OMAP4_GPIO_IRQSTATUSCLR0;
836 l = gpio_mask;
837 break;
838#endif
839 default:
840 WARN_ON(1);
841 return;
842 }
843 __raw_writel(l, reg);
844}
845
846static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
847{
848 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
849}
850
851/*
852 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
853 * 1510 does not seem to have a wake-up register. If JTAG is connected
854 * to the target, system will wake up always on GPIO events. While
855 * system is running all registered GPIO interrupts need to have wake-up
856 * enabled. When system is suspended, only selected GPIO interrupts need
857 * to have wake-up enabled.
858 */
859static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
860{
861 unsigned long uninitialized_var(flags);
862
863 switch (bank->method) {
864#ifdef CONFIG_ARCH_OMAP16XX
865 case METHOD_MPUIO:
866 case METHOD_GPIO_1610:
867 spin_lock_irqsave(&bank->lock, flags);
868 if (enable)
869 bank->suspend_wakeup |= (1 << gpio);
870 else
871 bank->suspend_wakeup &= ~(1 << gpio);
872 spin_unlock_irqrestore(&bank->lock, flags);
873 return 0;
874#endif
875#ifdef CONFIG_ARCH_OMAP2PLUS
876 case METHOD_GPIO_24XX:
877 case METHOD_GPIO_44XX:
878 if (bank->non_wakeup_gpios & (1 << gpio)) {
879 printk(KERN_ERR "Unable to modify wakeup on "
880 "non-wakeup GPIO%d\n",
881 (bank - gpio_bank) * 32 + gpio);
882 return -EINVAL;
883 }
884 spin_lock_irqsave(&bank->lock, flags);
885 if (enable)
886 bank->suspend_wakeup |= (1 << gpio);
887 else
888 bank->suspend_wakeup &= ~(1 << gpio);
889 spin_unlock_irqrestore(&bank->lock, flags);
890 return 0;
891#endif
892 default:
893 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
894 bank->method);
895 return -EINVAL;
896 }
897}
898
899static void _reset_gpio(struct gpio_bank *bank, int gpio)
900{
901 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
902 _set_gpio_irqenable(bank, gpio, 0);
903 _clear_gpio_irqstatus(bank, gpio);
904 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
905}
906
907/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
908static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
909{
910 unsigned int gpio = d->irq - IH_GPIO_BASE;
911 struct gpio_bank *bank;
912 int retval;
913
914 if (check_gpio(gpio) < 0)
915 return -ENODEV;
916 bank = irq_data_get_irq_chip_data(d);
917 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
918
919 return retval;
920}
921
922static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
923{
924 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
925 unsigned long flags;
926
927 spin_lock_irqsave(&bank->lock, flags);
928
929 /* Set trigger to none. You need to enable the desired trigger with
930 * request_irq() or set_irq_type().
931 */
932 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
933
934#ifdef CONFIG_ARCH_OMAP15XX
935 if (bank->method == METHOD_GPIO_1510) {
936 void __iomem *reg;
937
938 /* Claim the pin for MPU */
939 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
940 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
941 }
942#endif
943 if (!cpu_class_is_omap1()) {
944 if (!bank->mod_usage) {
945 void __iomem *reg = bank->base;
946 u32 ctrl;
947
948 if (cpu_is_omap24xx() || cpu_is_omap34xx())
949 reg += OMAP24XX_GPIO_CTRL;
950 else if (cpu_is_omap44xx())
951 reg += OMAP4_GPIO_CTRL;
952 ctrl = __raw_readl(reg);
953 /* Module is enabled, clocks are not gated */
954 ctrl &= 0xFFFFFFFE;
955 __raw_writel(ctrl, reg);
956 }
957 bank->mod_usage |= 1 << offset;
958 }
959 spin_unlock_irqrestore(&bank->lock, flags);
960
961 return 0;
962}
963
964static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
965{
966 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
967 unsigned long flags;
968
969 spin_lock_irqsave(&bank->lock, flags);
970#ifdef CONFIG_ARCH_OMAP16XX
971 if (bank->method == METHOD_GPIO_1610) {
972 /* Disable wake-up during idle for dynamic tick */
973 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
974 __raw_writel(1 << offset, reg);
975 }
976#endif
977#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
978 if (bank->method == METHOD_GPIO_24XX) {
979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
981 __raw_writel(1 << offset, reg);
982 }
983#endif
984#ifdef CONFIG_ARCH_OMAP4
985 if (bank->method == METHOD_GPIO_44XX) {
986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
988 __raw_writel(1 << offset, reg);
989 }
990#endif
991 if (!cpu_class_is_omap1()) {
992 bank->mod_usage &= ~(1 << offset);
993 if (!bank->mod_usage) {
994 void __iomem *reg = bank->base;
995 u32 ctrl;
996
997 if (cpu_is_omap24xx() || cpu_is_omap34xx())
998 reg += OMAP24XX_GPIO_CTRL;
999 else if (cpu_is_omap44xx())
1000 reg += OMAP4_GPIO_CTRL;
1001 ctrl = __raw_readl(reg);
1002 /* Module is disabled, clocks are gated */
1003 ctrl |= 1;
1004 __raw_writel(ctrl, reg);
1005 }
1006 }
1007 _reset_gpio(bank, bank->chip.base + offset);
1008 spin_unlock_irqrestore(&bank->lock, flags);
1009}
1010
1011/*
1012 * We need to unmask the GPIO bank interrupt as soon as possible to
1013 * avoid missing GPIO interrupts for other lines in the bank.
1014 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1015 * in the bank to avoid missing nested interrupts for a GPIO line.
1016 * If we wait to unmask individual GPIO lines in the bank after the
1017 * line's interrupt handler has been run, we may miss some nested
1018 * interrupts.
1019 */
1020static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1021{
1022 void __iomem *isr_reg = NULL;
1023 u32 isr;
1024 unsigned int gpio_irq, gpio_index;
1025 struct gpio_bank *bank;
1026 u32 retrigger = 0;
1027 int unmasked = 0;
1028 struct irq_chip *chip = irq_desc_get_chip(desc);
1029
1030 chained_irq_enter(chip, desc);
1031
1032 bank = irq_get_handler_data(irq);
1033#ifdef CONFIG_ARCH_OMAP1
1034 if (bank->method == METHOD_MPUIO)
1035 isr_reg = bank->base +
1036 OMAP_MPUIO_GPIO_INT / bank->stride;
1037#endif
1038#ifdef CONFIG_ARCH_OMAP15XX
1039 if (bank->method == METHOD_GPIO_1510)
1040 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1041#endif
1042#if defined(CONFIG_ARCH_OMAP16XX)
1043 if (bank->method == METHOD_GPIO_1610)
1044 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1045#endif
1046#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1047 if (bank->method == METHOD_GPIO_7XX)
1048 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1049#endif
1050#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1051 if (bank->method == METHOD_GPIO_24XX)
1052 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1053#endif
1054#if defined(CONFIG_ARCH_OMAP4)
1055 if (bank->method == METHOD_GPIO_44XX)
1056 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1057#endif
1058
1059 if (WARN_ON(!isr_reg))
1060 goto exit;
1061
1062 while(1) {
1063 u32 isr_saved, level_mask = 0;
1064 u32 enabled;
1065
1066 enabled = _get_gpio_irqbank_mask(bank);
1067 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1068
1069 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1070 isr &= 0x0000ffff;
1071
1072 if (cpu_class_is_omap2()) {
1073 level_mask = bank->level_mask & enabled;
1074 }
1075
1076 /* clear edge sensitive interrupts before handler(s) are
1077 called so that we don't miss any interrupt occurred while
1078 executing them */
1079 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1080 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1081 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1082
1083 /* if there is only edge sensitive GPIO pin interrupts
1084 configured, we could unmask GPIO bank interrupt immediately */
1085 if (!level_mask && !unmasked) {
1086 unmasked = 1;
1087 chained_irq_exit(chip, desc);
1088 }
1089
1090 isr |= retrigger;
1091 retrigger = 0;
1092 if (!isr)
1093 break;
1094
1095 gpio_irq = bank->virtual_irq_start;
1096 for (; isr != 0; isr >>= 1, gpio_irq++) {
1097 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1098
1099 if (!(isr & 1))
1100 continue;
1101
1102#ifdef CONFIG_ARCH_OMAP1
1103 /*
1104 * Some chips can't respond to both rising and falling
1105 * at the same time. If this irq was requested with
1106 * both flags, we need to flip the ICR data for the IRQ
1107 * to respond to the IRQ for the opposite direction.
1108 * This will be indicated in the bank toggle_mask.
1109 */
1110 if (bank->toggle_mask & (1 << gpio_index))
1111 _toggle_gpio_edge_triggering(bank, gpio_index);
1112#endif
1113
1114 generic_handle_irq(gpio_irq);
1115 }
1116 }
1117 /* if bank has any level sensitive GPIO pin interrupt
1118 configured, we must unmask the bank interrupt only after
1119 handler(s) are executed in order to avoid spurious bank
1120 interrupt */
1121exit:
1122 if (!unmasked)
1123 chained_irq_exit(chip, desc);
1124}
1125
1126static void gpio_irq_shutdown(struct irq_data *d)
1127{
1128 unsigned int gpio = d->irq - IH_GPIO_BASE;
1129 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&bank->lock, flags);
1133 _reset_gpio(bank, gpio);
1134 spin_unlock_irqrestore(&bank->lock, flags);
1135}
1136
1137static void gpio_ack_irq(struct irq_data *d)
1138{
1139 unsigned int gpio = d->irq - IH_GPIO_BASE;
1140 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1141
1142 _clear_gpio_irqstatus(bank, gpio);
1143}
1144
1145static void gpio_mask_irq(struct irq_data *d)
1146{
1147 unsigned int gpio = d->irq - IH_GPIO_BASE;
1148 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1149 unsigned long flags;
1150
1151 spin_lock_irqsave(&bank->lock, flags);
1152 _set_gpio_irqenable(bank, gpio, 0);
1153 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1154 spin_unlock_irqrestore(&bank->lock, flags);
1155}
1156
1157static void gpio_unmask_irq(struct irq_data *d)
1158{
1159 unsigned int gpio = d->irq - IH_GPIO_BASE;
1160 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1161 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1162 u32 trigger = irqd_get_trigger_type(d);
1163 unsigned long flags;
1164
1165 spin_lock_irqsave(&bank->lock, flags);
1166 if (trigger)
1167 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1168
1169 /* For level-triggered GPIOs, the clearing must be done after
1170 * the HW source is cleared, thus after the handler has run */
1171 if (bank->level_mask & irq_mask) {
1172 _set_gpio_irqenable(bank, gpio, 0);
1173 _clear_gpio_irqstatus(bank, gpio);
1174 }
1175
1176 _set_gpio_irqenable(bank, gpio, 1);
1177 spin_unlock_irqrestore(&bank->lock, flags);
1178}
1179
1180static struct irq_chip gpio_irq_chip = {
1181 .name = "GPIO",
1182 .irq_shutdown = gpio_irq_shutdown,
1183 .irq_ack = gpio_ack_irq,
1184 .irq_mask = gpio_mask_irq,
1185 .irq_unmask = gpio_unmask_irq,
1186 .irq_set_type = gpio_irq_type,
1187 .irq_set_wake = gpio_wake_enable,
1188};
1189
1190/*---------------------------------------------------------------------*/
1191
1192#ifdef CONFIG_ARCH_OMAP1
1193
1194/* MPUIO uses the always-on 32k clock */
1195
1196static void mpuio_ack_irq(struct irq_data *d)
1197{
1198 /* The ISR is reset automatically, so do nothing here. */
1199}
1200
1201static void mpuio_mask_irq(struct irq_data *d)
1202{
1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1205
1206 _set_gpio_irqenable(bank, gpio, 0);
1207}
1208
1209static void mpuio_unmask_irq(struct irq_data *d)
1210{
1211 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1212 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1213
1214 _set_gpio_irqenable(bank, gpio, 1);
1215}
1216
1217static struct irq_chip mpuio_irq_chip = {
1218 .name = "MPUIO",
1219 .irq_ack = mpuio_ack_irq,
1220 .irq_mask = mpuio_mask_irq,
1221 .irq_unmask = mpuio_unmask_irq,
1222 .irq_set_type = gpio_irq_type,
1223#ifdef CONFIG_ARCH_OMAP16XX
1224 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1225 .irq_set_wake = gpio_wake_enable,
1226#endif
1227};
1228
1229
1230#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231
1232
1233#ifdef CONFIG_ARCH_OMAP16XX
1234
1235#include <linux/platform_device.h>
1236
1237static int omap_mpuio_suspend_noirq(struct device *dev)
1238{
1239 struct platform_device *pdev = to_platform_device(dev);
1240 struct gpio_bank *bank = platform_get_drvdata(pdev);
1241 void __iomem *mask_reg = bank->base +
1242 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1243 unsigned long flags;
1244
1245 spin_lock_irqsave(&bank->lock, flags);
1246 bank->saved_wakeup = __raw_readl(mask_reg);
1247 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1248 spin_unlock_irqrestore(&bank->lock, flags);
1249
1250 return 0;
1251}
1252
1253static int omap_mpuio_resume_noirq(struct device *dev)
1254{
1255 struct platform_device *pdev = to_platform_device(dev);
1256 struct gpio_bank *bank = platform_get_drvdata(pdev);
1257 void __iomem *mask_reg = bank->base +
1258 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&bank->lock, flags);
1262 __raw_writel(bank->saved_wakeup, mask_reg);
1263 spin_unlock_irqrestore(&bank->lock, flags);
1264
1265 return 0;
1266}
1267
1268static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1269 .suspend_noirq = omap_mpuio_suspend_noirq,
1270 .resume_noirq = omap_mpuio_resume_noirq,
1271};
1272
1273/* use platform_driver for this. */
1274static struct platform_driver omap_mpuio_driver = {
1275 .driver = {
1276 .name = "mpuio",
1277 .pm = &omap_mpuio_dev_pm_ops,
1278 },
1279};
1280
1281static struct platform_device omap_mpuio_device = {
1282 .name = "mpuio",
1283 .id = -1,
1284 .dev = {
1285 .driver = &omap_mpuio_driver.driver,
1286 }
1287 /* could list the /proc/iomem resources */
1288};
1289
1290static inline void mpuio_init(void)
1291{
1292 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1293 platform_set_drvdata(&omap_mpuio_device, bank);
1294
1295 if (platform_driver_register(&omap_mpuio_driver) == 0)
1296 (void) platform_device_register(&omap_mpuio_device);
1297}
1298
1299#else
1300static inline void mpuio_init(void) {}
1301#endif /* 16xx */
1302
1303#else
1304
1305extern struct irq_chip mpuio_irq_chip;
1306
1307#define bank_is_mpuio(bank) 0
1308static inline void mpuio_init(void) {}
1309
1310#endif
1311
1312/*---------------------------------------------------------------------*/
1313
1314/* REVISIT these are stupid implementations! replace by ones that
1315 * don't switch on METHOD_* and which mostly avoid spinlocks
1316 */
1317
1318static int gpio_input(struct gpio_chip *chip, unsigned offset)
1319{
1320 struct gpio_bank *bank;
1321 unsigned long flags;
1322
1323 bank = container_of(chip, struct gpio_bank, chip);
1324 spin_lock_irqsave(&bank->lock, flags);
1325 _set_gpio_direction(bank, offset, 1);
1326 spin_unlock_irqrestore(&bank->lock, flags);
1327 return 0;
1328}
1329
1330static int gpio_is_input(struct gpio_bank *bank, int mask)
1331{
1332 void __iomem *reg = bank->base;
1333
1334 switch (bank->method) {
1335 case METHOD_MPUIO:
1336 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1337 break;
1338 case METHOD_GPIO_1510:
1339 reg += OMAP1510_GPIO_DIR_CONTROL;
1340 break;
1341 case METHOD_GPIO_1610:
1342 reg += OMAP1610_GPIO_DIRECTION;
1343 break;
1344 case METHOD_GPIO_7XX:
1345 reg += OMAP7XX_GPIO_DIR_CONTROL;
1346 break;
1347 case METHOD_GPIO_24XX:
1348 reg += OMAP24XX_GPIO_OE;
1349 break;
1350 case METHOD_GPIO_44XX:
1351 reg += OMAP4_GPIO_OE;
1352 break;
1353 default:
1354 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return -EINVAL;
1356 }
1357 return __raw_readl(reg) & mask;
1358}
1359
1360static int gpio_get(struct gpio_chip *chip, unsigned offset)
1361{
1362 struct gpio_bank *bank;
1363 void __iomem *reg;
1364 int gpio;
1365 u32 mask;
1366
1367 gpio = chip->base + offset;
1368 bank = get_gpio_bank(gpio);
1369 reg = bank->base;
1370 mask = 1 << get_gpio_index(gpio);
1371
1372 if (gpio_is_input(bank, mask))
1373 return _get_gpio_datain(bank, gpio);
1374 else
1375 return _get_gpio_dataout(bank, gpio);
1376}
1377
1378static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1379{
1380 struct gpio_bank *bank;
1381 unsigned long flags;
1382
1383 bank = container_of(chip, struct gpio_bank, chip);
1384 spin_lock_irqsave(&bank->lock, flags);
1385 _set_gpio_dataout(bank, offset, value);
1386 _set_gpio_direction(bank, offset, 0);
1387 spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0;
1389}
1390
1391static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1392 unsigned debounce)
1393{
1394 struct gpio_bank *bank;
1395 unsigned long flags;
1396
1397 bank = container_of(chip, struct gpio_bank, chip);
1398
1399 if (!bank->dbck) {
1400 bank->dbck = clk_get(bank->dev, "dbclk");
1401 if (IS_ERR(bank->dbck))
1402 dev_err(bank->dev, "Could not get gpio dbck\n");
1403 }
1404
1405 spin_lock_irqsave(&bank->lock, flags);
1406 _set_gpio_debounce(bank, offset, debounce);
1407 spin_unlock_irqrestore(&bank->lock, flags);
1408
1409 return 0;
1410}
1411
1412static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1413{
1414 struct gpio_bank *bank;
1415 unsigned long flags;
1416
1417 bank = container_of(chip, struct gpio_bank, chip);
1418 spin_lock_irqsave(&bank->lock, flags);
1419 _set_gpio_dataout(bank, offset, value);
1420 spin_unlock_irqrestore(&bank->lock, flags);
1421}
1422
1423static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1424{
1425 struct gpio_bank *bank;
1426
1427 bank = container_of(chip, struct gpio_bank, chip);
1428 return bank->virtual_irq_start + offset;
1429}
1430
1431/*---------------------------------------------------------------------*/
1432
1433static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1434{
1435 u32 rev;
1436
1437 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1438 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1439 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1440 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1441 else if (cpu_is_omap44xx())
1442 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1443 else
1444 return;
1445
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f);
1448}
1449
1450/* This lock class tells lockdep that GPIO irqs are in a different
1451 * category than their parents, so it won't report false recursion.
1452 */
1453static struct lock_class_key gpio_lock_class;
1454
1455static inline int init_gpio_info(struct platform_device *pdev)
1456{
1457 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1458 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1459 GFP_KERNEL);
1460 if (!gpio_bank) {
1461 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1462 return -ENOMEM;
1463 }
1464 return 0;
1465}
1466
1467/* TODO: Cleanup cpu_is_* checks */
1468static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1469{
1470 if (cpu_class_is_omap2()) {
1471 if (cpu_is_omap44xx()) {
1472 __raw_writel(0xffffffff, bank->base +
1473 OMAP4_GPIO_IRQSTATUSCLR0);
1474 __raw_writel(0x00000000, bank->base +
1475 OMAP4_GPIO_DEBOUNCENABLE);
1476 /* Initialize interface clk ungated, module enabled */
1477 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1478 } else if (cpu_is_omap34xx()) {
1479 __raw_writel(0x00000000, bank->base +
1480 OMAP24XX_GPIO_IRQENABLE1);
1481 __raw_writel(0xffffffff, bank->base +
1482 OMAP24XX_GPIO_IRQSTATUS1);
1483 __raw_writel(0x00000000, bank->base +
1484 OMAP24XX_GPIO_DEBOUNCE_EN);
1485
1486 /* Initialize interface clk ungated, module enabled */
1487 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1488 } else if (cpu_is_omap24xx()) {
1489 static const u32 non_wakeup_gpios[] = {
1490 0xe203ffc0, 0x08700040
1491 };
1492 if (id < ARRAY_SIZE(non_wakeup_gpios))
1493 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1494 }
1495 } else if (cpu_class_is_omap1()) {
1496 if (bank_is_mpuio(bank))
1497 __raw_writew(0xffff, bank->base +
1498 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1499 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1500 __raw_writew(0xffff, bank->base
1501 + OMAP1510_GPIO_INT_MASK);
1502 __raw_writew(0x0000, bank->base
1503 + OMAP1510_GPIO_INT_STATUS);
1504 }
1505 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1506 __raw_writew(0x0000, bank->base
1507 + OMAP1610_GPIO_IRQENABLE1);
1508 __raw_writew(0xffff, bank->base
1509 + OMAP1610_GPIO_IRQSTATUS1);
1510 __raw_writew(0x0014, bank->base
1511 + OMAP1610_GPIO_SYSCONFIG);
1512
1513 /*
1514 * Enable system clock for GPIO module.
1515 * The CAM_CLK_CTRL *is* really the right place.
1516 */
1517 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1518 ULPD_CAM_CLK_CTRL);
1519 }
1520 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1521 __raw_writel(0xffffffff, bank->base
1522 + OMAP7XX_GPIO_INT_MASK);
1523 __raw_writel(0x00000000, bank->base
1524 + OMAP7XX_GPIO_INT_STATUS);
1525 }
1526 }
1527}
1528
1529static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1530{
1531 int j;
1532 static int gpio;
1533
1534 bank->mod_usage = 0;
1535 /*
1536 * REVISIT eventually switch from OMAP-specific gpio structs
1537 * over to the generic ones
1538 */
1539 bank->chip.request = omap_gpio_request;
1540 bank->chip.free = omap_gpio_free;
1541 bank->chip.direction_input = gpio_input;
1542 bank->chip.get = gpio_get;
1543 bank->chip.direction_output = gpio_output;
1544 bank->chip.set_debounce = gpio_debounce;
1545 bank->chip.set = gpio_set;
1546 bank->chip.to_irq = gpio_2irq;
1547 if (bank_is_mpuio(bank)) {
1548 bank->chip.label = "mpuio";
1549#ifdef CONFIG_ARCH_OMAP16XX
1550 bank->chip.dev = &omap_mpuio_device.dev;
1551#endif
1552 bank->chip.base = OMAP_MPUIO(0);
1553 } else {
1554 bank->chip.label = "gpio";
1555 bank->chip.base = gpio;
1556 gpio += bank_width;
1557 }
1558 bank->chip.ngpio = bank_width;
1559
1560 gpiochip_add(&bank->chip);
1561
1562 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + bank_width; j++) {
1564 irq_set_lockdep_class(j, &gpio_lock_class);
1565 irq_set_chip_data(j, bank);
1566 if (bank_is_mpuio(bank))
1567 irq_set_chip(j, &mpuio_irq_chip);
1568 else
1569 irq_set_chip(j, &gpio_irq_chip);
1570 irq_set_handler(j, handle_simple_irq);
1571 set_irq_flags(j, IRQF_VALID);
1572 }
1573 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1574 irq_set_handler_data(bank->irq, bank);
1575}
1576
1577static int __devinit omap_gpio_probe(struct platform_device *pdev)
1578{
1579 static int gpio_init_done;
1580 struct omap_gpio_platform_data *pdata;
1581 struct resource *res;
1582 int id;
1583 struct gpio_bank *bank;
1584
1585 if (!pdev->dev.platform_data)
1586 return -EINVAL;
1587
1588 pdata = pdev->dev.platform_data;
1589
1590 if (!gpio_init_done) {
1591 int ret;
1592
1593 ret = init_gpio_info(pdev);
1594 if (ret)
1595 return ret;
1596 }
1597
1598 id = pdev->id;
1599 bank = &gpio_bank[id];
1600
1601 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1602 if (unlikely(!res)) {
1603 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1604 return -ENODEV;
1605 }
1606
1607 bank->irq = res->start;
1608 bank->virtual_irq_start = pdata->virtual_irq_start;
1609 bank->method = pdata->bank_type;
1610 bank->dev = &pdev->dev;
1611 bank->dbck_flag = pdata->dbck_flag;
1612 bank->stride = pdata->bank_stride;
1613 bank_width = pdata->bank_width;
1614
1615 spin_lock_init(&bank->lock);
1616
1617 /* Static mapping, never released */
1618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1619 if (unlikely(!res)) {
1620 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1621 return -ENODEV;
1622 }
1623
1624 bank->base = ioremap(res->start, resource_size(res));
1625 if (!bank->base) {
1626 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1627 return -ENOMEM;
1628 }
1629
1630 pm_runtime_enable(bank->dev);
1631 pm_runtime_get_sync(bank->dev);
1632
1633 omap_gpio_mod_init(bank, id);
1634 omap_gpio_chip_init(bank);
1635 omap_gpio_show_rev(bank);
1636
1637 if (!gpio_init_done)
1638 gpio_init_done = 1;
1639
1640 return 0;
1641}
1642
1643#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1644static int omap_gpio_suspend(void)
1645{
1646 int i;
1647
1648 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1649 return 0;
1650
1651 for (i = 0; i < gpio_bank_count; i++) {
1652 struct gpio_bank *bank = &gpio_bank[i];
1653 void __iomem *wake_status;
1654 void __iomem *wake_clear;
1655 void __iomem *wake_set;
1656 unsigned long flags;
1657
1658 switch (bank->method) {
1659#ifdef CONFIG_ARCH_OMAP16XX
1660 case METHOD_GPIO_1610:
1661 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1662 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1663 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1664 break;
1665#endif
1666#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1667 case METHOD_GPIO_24XX:
1668 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1669 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1670 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1671 break;
1672#endif
1673#ifdef CONFIG_ARCH_OMAP4
1674 case METHOD_GPIO_44XX:
1675 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1677 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1678 break;
1679#endif
1680 default:
1681 continue;
1682 }
1683
1684 spin_lock_irqsave(&bank->lock, flags);
1685 bank->saved_wakeup = __raw_readl(wake_status);
1686 __raw_writel(0xffffffff, wake_clear);
1687 __raw_writel(bank->suspend_wakeup, wake_set);
1688 spin_unlock_irqrestore(&bank->lock, flags);
1689 }
1690
1691 return 0;
1692}
1693
1694static void omap_gpio_resume(void)
1695{
1696 int i;
1697
1698 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1699 return;
1700
1701 for (i = 0; i < gpio_bank_count; i++) {
1702 struct gpio_bank *bank = &gpio_bank[i];
1703 void __iomem *wake_clear;
1704 void __iomem *wake_set;
1705 unsigned long flags;
1706
1707 switch (bank->method) {
1708#ifdef CONFIG_ARCH_OMAP16XX
1709 case METHOD_GPIO_1610:
1710 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1711 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1712 break;
1713#endif
1714#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1715 case METHOD_GPIO_24XX:
1716 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1717 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1718 break;
1719#endif
1720#ifdef CONFIG_ARCH_OMAP4
1721 case METHOD_GPIO_44XX:
1722 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1723 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1724 break;
1725#endif
1726 default:
1727 continue;
1728 }
1729
1730 spin_lock_irqsave(&bank->lock, flags);
1731 __raw_writel(0xffffffff, wake_clear);
1732 __raw_writel(bank->saved_wakeup, wake_set);
1733 spin_unlock_irqrestore(&bank->lock, flags);
1734 }
1735}
1736
1737static struct syscore_ops omap_gpio_syscore_ops = {
1738 .suspend = omap_gpio_suspend,
1739 .resume = omap_gpio_resume,
1740};
1741
1742#endif
1743
1744#ifdef CONFIG_ARCH_OMAP2PLUS
1745
1746static int workaround_enabled;
1747
1748void omap2_gpio_prepare_for_idle(int off_mode)
1749{
1750 int i, c = 0;
1751 int min = 0;
1752
1753 if (cpu_is_omap34xx())
1754 min = 1;
1755
1756 for (i = min; i < gpio_bank_count; i++) {
1757 struct gpio_bank *bank = &gpio_bank[i];
1758 u32 l1 = 0, l2 = 0;
1759 int j;
1760
1761 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1762 clk_disable(bank->dbck);
1763
1764 if (!off_mode)
1765 continue;
1766
1767 /* If going to OFF, remove triggering for all
1768 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1769 * generated. See OMAP2420 Errata item 1.101. */
1770 if (!(bank->enabled_non_wakeup_gpios))
1771 continue;
1772
1773 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1774 bank->saved_datain = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_DATAIN);
1776 l1 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_FALLINGDETECT);
1778 l2 = __raw_readl(bank->base +
1779 OMAP24XX_GPIO_RISINGDETECT);
1780 }
1781
1782 if (cpu_is_omap44xx()) {
1783 bank->saved_datain = __raw_readl(bank->base +
1784 OMAP4_GPIO_DATAIN);
1785 l1 = __raw_readl(bank->base +
1786 OMAP4_GPIO_FALLINGDETECT);
1787 l2 = __raw_readl(bank->base +
1788 OMAP4_GPIO_RISINGDETECT);
1789 }
1790
1791 bank->saved_fallingdetect = l1;
1792 bank->saved_risingdetect = l2;
1793 l1 &= ~bank->enabled_non_wakeup_gpios;
1794 l2 &= ~bank->enabled_non_wakeup_gpios;
1795
1796 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1797 __raw_writel(l1, bank->base +
1798 OMAP24XX_GPIO_FALLINGDETECT);
1799 __raw_writel(l2, bank->base +
1800 OMAP24XX_GPIO_RISINGDETECT);
1801 }
1802
1803 if (cpu_is_omap44xx()) {
1804 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1805 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1806 }
1807
1808 c++;
1809 }
1810 if (!c) {
1811 workaround_enabled = 0;
1812 return;
1813 }
1814 workaround_enabled = 1;
1815}
1816
1817void omap2_gpio_resume_after_idle(void)
1818{
1819 int i;
1820 int min = 0;
1821
1822 if (cpu_is_omap34xx())
1823 min = 1;
1824 for (i = min; i < gpio_bank_count; i++) {
1825 struct gpio_bank *bank = &gpio_bank[i];
1826 u32 l = 0, gen, gen0, gen1;
1827 int j;
1828
1829 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1830 clk_enable(bank->dbck);
1831
1832 if (!workaround_enabled)
1833 continue;
1834
1835 if (!(bank->enabled_non_wakeup_gpios))
1836 continue;
1837
1838 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1839 __raw_writel(bank->saved_fallingdetect,
1840 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1841 __raw_writel(bank->saved_risingdetect,
1842 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1843 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1844 }
1845
1846 if (cpu_is_omap44xx()) {
1847 __raw_writel(bank->saved_fallingdetect,
1848 bank->base + OMAP4_GPIO_FALLINGDETECT);
1849 __raw_writel(bank->saved_risingdetect,
1850 bank->base + OMAP4_GPIO_RISINGDETECT);
1851 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1852 }
1853
1854 /* Check if any of the non-wakeup interrupt GPIOs have changed
1855 * state. If so, generate an IRQ by software. This is
1856 * horribly racy, but it's the best we can do to work around
1857 * this silicon bug. */
1858 l ^= bank->saved_datain;
1859 l &= bank->enabled_non_wakeup_gpios;
1860
1861 /*
1862 * No need to generate IRQs for the rising edge for gpio IRQs
1863 * configured with falling edge only; and vice versa.
1864 */
1865 gen0 = l & bank->saved_fallingdetect;
1866 gen0 &= bank->saved_datain;
1867
1868 gen1 = l & bank->saved_risingdetect;
1869 gen1 &= ~(bank->saved_datain);
1870
1871 /* FIXME: Consider GPIO IRQs with level detections properly! */
1872 gen = l & (~(bank->saved_fallingdetect) &
1873 ~(bank->saved_risingdetect));
1874 /* Consider all GPIO IRQs needed to be updated */
1875 gen |= gen0 | gen1;
1876
1877 if (gen) {
1878 u32 old0, old1;
1879
1880 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1881 old0 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT0);
1883 old1 = __raw_readl(bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT1);
1885 __raw_writel(old0 | gen, bank->base +
1886 OMAP24XX_GPIO_LEVELDETECT0);
1887 __raw_writel(old1 | gen, bank->base +
1888 OMAP24XX_GPIO_LEVELDETECT1);
1889 __raw_writel(old0, bank->base +
1890 OMAP24XX_GPIO_LEVELDETECT0);
1891 __raw_writel(old1, bank->base +
1892 OMAP24XX_GPIO_LEVELDETECT1);
1893 }
1894
1895 if (cpu_is_omap44xx()) {
1896 old0 = __raw_readl(bank->base +
1897 OMAP4_GPIO_LEVELDETECT0);
1898 old1 = __raw_readl(bank->base +
1899 OMAP4_GPIO_LEVELDETECT1);
1900 __raw_writel(old0 | l, bank->base +
1901 OMAP4_GPIO_LEVELDETECT0);
1902 __raw_writel(old1 | l, bank->base +
1903 OMAP4_GPIO_LEVELDETECT1);
1904 __raw_writel(old0, bank->base +
1905 OMAP4_GPIO_LEVELDETECT0);
1906 __raw_writel(old1, bank->base +
1907 OMAP4_GPIO_LEVELDETECT1);
1908 }
1909 }
1910 }
1911
1912}
1913
1914#endif
1915
1916#ifdef CONFIG_ARCH_OMAP3
1917/* save the registers of bank 2-6 */
1918void omap_gpio_save_context(void)
1919{
1920 int i;
1921
1922 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1923 for (i = 1; i < gpio_bank_count; i++) {
1924 struct gpio_bank *bank = &gpio_bank[i];
1925 gpio_context[i].irqenable1 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1927 gpio_context[i].irqenable2 =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1929 gpio_context[i].wake_en =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1931 gpio_context[i].ctrl =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1933 gpio_context[i].oe =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1935 gpio_context[i].leveldetect0 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1937 gpio_context[i].leveldetect1 =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1939 gpio_context[i].risingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1941 gpio_context[i].fallingdetect =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1943 gpio_context[i].dataout =
1944 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1945 }
1946}
1947
1948/* restore the required registers of bank 2-6 */
1949void omap_gpio_restore_context(void)
1950{
1951 int i;
1952
1953 for (i = 1; i < gpio_bank_count; i++) {
1954 struct gpio_bank *bank = &gpio_bank[i];
1955 __raw_writel(gpio_context[i].irqenable1,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1957 __raw_writel(gpio_context[i].irqenable2,
1958 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1959 __raw_writel(gpio_context[i].wake_en,
1960 bank->base + OMAP24XX_GPIO_WAKE_EN);
1961 __raw_writel(gpio_context[i].ctrl,
1962 bank->base + OMAP24XX_GPIO_CTRL);
1963 __raw_writel(gpio_context[i].oe,
1964 bank->base + OMAP24XX_GPIO_OE);
1965 __raw_writel(gpio_context[i].leveldetect0,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1967 __raw_writel(gpio_context[i].leveldetect1,
1968 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1969 __raw_writel(gpio_context[i].risingdetect,
1970 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1971 __raw_writel(gpio_context[i].fallingdetect,
1972 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1973 __raw_writel(gpio_context[i].dataout,
1974 bank->base + OMAP24XX_GPIO_DATAOUT);
1975 }
1976}
1977#endif
1978
1979static struct platform_driver omap_gpio_driver = {
1980 .probe = omap_gpio_probe,
1981 .driver = {
1982 .name = "omap_gpio",
1983 },
1984};
1985
1986/*
1987 * gpio driver register needs to be done before
1988 * machine_init functions access gpio APIs.
1989 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1990 */
1991static int __init omap_gpio_drv_reg(void)
1992{
1993 return platform_driver_register(&omap_gpio_driver);
1994}
1995postcore_initcall(omap_gpio_drv_reg);
1996
1997static int __init omap_gpio_sysinit(void)
1998{
1999 mpuio_init();
2000
2001#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2002 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2003 register_syscore_ops(&omap_gpio_syscore_ops);
2004#endif
2005
2006 return 0;
2007}
2008
2009arch_initcall(omap_gpio_sysinit);
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c
new file mode 100644
index 000000000000..ea37c0461788
--- /dev/null
+++ b/drivers/gpio/gpio-plat-samsung.c
@@ -0,0 +1,206 @@
1/* arch/arm/plat-samsung/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com/
10 *
11 * SAMSUNG - GPIOlib support
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/kernel.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25
26#ifndef DEBUG_GPIO
27#define gpio_dbg(x...) do { } while (0)
28#else
29#define gpio_dbg(x...) printk(KERN_DEBUG x)
30#endif
31
32/* The samsung_gpiolib_4bit routines are to control the gpio banks where
33 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
34 * following example:
35 *
36 * base + 0x00: Control register, 4 bits per gpio
37 * gpio n: 4 bits starting at (4*n)
38 * 0000 = input, 0001 = output, others mean special-function
39 * base + 0x04: Data register, 1 bit per gpio
40 * bit n: data bit n
41 *
42 * Note, since the data register is one bit per gpio and is at base + 0x4
43 * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
44 * the output.
45*/
46
47static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
48 unsigned int offset)
49{
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 unsigned long con;
53
54 con = __raw_readl(base + GPIOCON_OFF);
55 con &= ~(0xf << con_4bit_shift(offset));
56 __raw_writel(con, base + GPIOCON_OFF);
57
58 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
59
60 return 0;
61}
62
63static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
64 unsigned int offset, int value)
65{
66 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
67 void __iomem *base = ourchip->base;
68 unsigned long con;
69 unsigned long dat;
70
71 con = __raw_readl(base + GPIOCON_OFF);
72 con &= ~(0xf << con_4bit_shift(offset));
73 con |= 0x1 << con_4bit_shift(offset);
74
75 dat = __raw_readl(base + GPIODAT_OFF);
76
77 if (value)
78 dat |= 1 << offset;
79 else
80 dat &= ~(1 << offset);
81
82 __raw_writel(dat, base + GPIODAT_OFF);
83 __raw_writel(con, base + GPIOCON_OFF);
84 __raw_writel(dat, base + GPIODAT_OFF);
85
86 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
87
88 return 0;
89}
90
91/* The next set of routines are for the case where the GPIO configuration
92 * registers are 4 bits per GPIO but there is more than one register (the
93 * bank has more than 8 GPIOs.
94 *
95 * This case is the similar to the 4 bit case, but the registers are as
96 * follows:
97 *
98 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
99 * gpio n: 4 bits starting at (4*n)
100 * 0000 = input, 0001 = output, others mean special-function
101 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
102 * gpio n: 4 bits starting at (4*n)
103 * 0000 = input, 0001 = output, others mean special-function
104 * base + 0x08: Data register, 1 bit per gpio
105 * bit n: data bit n
106 *
107 * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
108 * store the 'base + 0x4' address so that these routines see the data
109 * register at ourchip->base + 0x04.
110 */
111
112static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
113 unsigned int offset)
114{
115 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
116 void __iomem *base = ourchip->base;
117 void __iomem *regcon = base;
118 unsigned long con;
119
120 if (offset > 7)
121 offset -= 8;
122 else
123 regcon -= 4;
124
125 con = __raw_readl(regcon);
126 con &= ~(0xf << con_4bit_shift(offset));
127 __raw_writel(con, regcon);
128
129 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
130
131 return 0;
132}
133
134static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
135 unsigned int offset, int value)
136{
137 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
138 void __iomem *base = ourchip->base;
139 void __iomem *regcon = base;
140 unsigned long con;
141 unsigned long dat;
142 unsigned con_offset = offset;
143
144 if (con_offset > 7)
145 con_offset -= 8;
146 else
147 regcon -= 4;
148
149 con = __raw_readl(regcon);
150 con &= ~(0xf << con_4bit_shift(con_offset));
151 con |= 0x1 << con_4bit_shift(con_offset);
152
153 dat = __raw_readl(base + GPIODAT_OFF);
154
155 if (value)
156 dat |= 1 << offset;
157 else
158 dat &= ~(1 << offset);
159
160 __raw_writel(dat, base + GPIODAT_OFF);
161 __raw_writel(con, regcon);
162 __raw_writel(dat, base + GPIODAT_OFF);
163
164 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
165
166 return 0;
167}
168
169void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
170{
171 chip->chip.direction_input = samsung_gpiolib_4bit_input;
172 chip->chip.direction_output = samsung_gpiolib_4bit_output;
173 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
174}
175
176void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
177{
178 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
179 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
180 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
181}
182
183void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
184 int nr_chips)
185{
186 for (; nr_chips > 0; nr_chips--, chip++) {
187 samsung_gpiolib_add_4bit(chip);
188 s3c_gpiolib_add(chip);
189 }
190}
191
192void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
193 int nr_chips)
194{
195 for (; nr_chips > 0; nr_chips--, chip++) {
196 samsung_gpiolib_add_4bit2(chip);
197 s3c_gpiolib_add(chip);
198 }
199}
200
201void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
202 int nr_chips)
203{
204 for (; nr_chips > 0; nr_chips--, chip++)
205 s3c_gpiolib_add(chip);
206}
diff --git a/drivers/gpio/gpio-s5pc100.c b/drivers/gpio/gpio-s5pc100.c
new file mode 100644
index 000000000000..2842394b28b5
--- /dev/null
+++ b/drivers/gpio/gpio-s5pc100.c
@@ -0,0 +1,355 @@
1/* linux/arch/arm/mach-s5pc100/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2009 Samsung Electronics Co
7 * Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * S5PC100 - GPIOlib support
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20
21#include <mach/map.h>
22#include <mach/regs-gpio.h>
23
24#include <plat/gpio-core.h>
25#include <plat/gpio-cfg.h>
26#include <plat/gpio-cfg-helpers.h>
27
28/* S5PC100 GPIO bank summary:
29 *
30 * Bank GPIOs Style INT Type
31 * A0 8 4Bit GPIO_INT0
32 * A1 5 4Bit GPIO_INT1
33 * B 8 4Bit GPIO_INT2
34 * C 5 4Bit GPIO_INT3
35 * D 7 4Bit GPIO_INT4
36 * E0 8 4Bit GPIO_INT5
37 * E1 6 4Bit GPIO_INT6
38 * F0 8 4Bit GPIO_INT7
39 * F1 8 4Bit GPIO_INT8
40 * F2 8 4Bit GPIO_INT9
41 * F3 4 4Bit GPIO_INT10
42 * G0 8 4Bit GPIO_INT11
43 * G1 3 4Bit GPIO_INT12
44 * G2 7 4Bit GPIO_INT13
45 * G3 7 4Bit GPIO_INT14
46 * H0 8 4Bit WKUP_INT
47 * H1 8 4Bit WKUP_INT
48 * H2 8 4Bit WKUP_INT
49 * H3 8 4Bit WKUP_INT
50 * I 8 4Bit GPIO_INT15
51 * J0 8 4Bit GPIO_INT16
52 * J1 5 4Bit GPIO_INT17
53 * J2 8 4Bit GPIO_INT18
54 * J3 8 4Bit GPIO_INT19
55 * J4 4 4Bit GPIO_INT20
56 * K0 8 4Bit None
57 * K1 6 4Bit None
58 * K2 8 4Bit None
59 * K3 8 4Bit None
60 * L0 8 4Bit None
61 * L1 8 4Bit None
62 * L2 8 4Bit None
63 * L3 8 4Bit None
64 */
65
66static struct s3c_gpio_cfg gpio_cfg = {
67 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
68 .set_pull = s3c_gpio_setpull_updown,
69 .get_pull = s3c_gpio_getpull_updown,
70};
71
72static struct s3c_gpio_cfg gpio_cfg_eint = {
73 .cfg_eint = 0xf,
74 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
75 .set_pull = s3c_gpio_setpull_updown,
76 .get_pull = s3c_gpio_getpull_updown,
77};
78
79static struct s3c_gpio_cfg gpio_cfg_noint = {
80 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
81 .set_pull = s3c_gpio_setpull_updown,
82 .get_pull = s3c_gpio_getpull_updown,
83};
84
85/*
86 * GPIO bank's base address given the index of the bank in the
87 * list of all gpio banks.
88 */
89#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
90
91/*
92 * Following are the gpio banks in S5PC100.
93 *
94 * The 'config' member when left to NULL, is initialized to the default
95 * structure gpio_cfg in the init function below.
96 *
97 * The 'base' member is also initialized in the init function below.
98 * Note: The initialization of 'base' member of s3c_gpio_chip structure
99 * uses the above macro and depends on the banks being listed in order here.
100 */
101static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
102 {
103 .chip = {
104 .base = S5PC100_GPA0(0),
105 .ngpio = S5PC100_GPIO_A0_NR,
106 .label = "GPA0",
107 },
108 }, {
109 .chip = {
110 .base = S5PC100_GPA1(0),
111 .ngpio = S5PC100_GPIO_A1_NR,
112 .label = "GPA1",
113 },
114 }, {
115 .chip = {
116 .base = S5PC100_GPB(0),
117 .ngpio = S5PC100_GPIO_B_NR,
118 .label = "GPB",
119 },
120 }, {
121 .chip = {
122 .base = S5PC100_GPC(0),
123 .ngpio = S5PC100_GPIO_C_NR,
124 .label = "GPC",
125 },
126 }, {
127 .chip = {
128 .base = S5PC100_GPD(0),
129 .ngpio = S5PC100_GPIO_D_NR,
130 .label = "GPD",
131 },
132 }, {
133 .chip = {
134 .base = S5PC100_GPE0(0),
135 .ngpio = S5PC100_GPIO_E0_NR,
136 .label = "GPE0",
137 },
138 }, {
139 .chip = {
140 .base = S5PC100_GPE1(0),
141 .ngpio = S5PC100_GPIO_E1_NR,
142 .label = "GPE1",
143 },
144 }, {
145 .chip = {
146 .base = S5PC100_GPF0(0),
147 .ngpio = S5PC100_GPIO_F0_NR,
148 .label = "GPF0",
149 },
150 }, {
151 .chip = {
152 .base = S5PC100_GPF1(0),
153 .ngpio = S5PC100_GPIO_F1_NR,
154 .label = "GPF1",
155 },
156 }, {
157 .chip = {
158 .base = S5PC100_GPF2(0),
159 .ngpio = S5PC100_GPIO_F2_NR,
160 .label = "GPF2",
161 },
162 }, {
163 .chip = {
164 .base = S5PC100_GPF3(0),
165 .ngpio = S5PC100_GPIO_F3_NR,
166 .label = "GPF3",
167 },
168 }, {
169 .chip = {
170 .base = S5PC100_GPG0(0),
171 .ngpio = S5PC100_GPIO_G0_NR,
172 .label = "GPG0",
173 },
174 }, {
175 .chip = {
176 .base = S5PC100_GPG1(0),
177 .ngpio = S5PC100_GPIO_G1_NR,
178 .label = "GPG1",
179 },
180 }, {
181 .chip = {
182 .base = S5PC100_GPG2(0),
183 .ngpio = S5PC100_GPIO_G2_NR,
184 .label = "GPG2",
185 },
186 }, {
187 .chip = {
188 .base = S5PC100_GPG3(0),
189 .ngpio = S5PC100_GPIO_G3_NR,
190 .label = "GPG3",
191 },
192 }, {
193 .chip = {
194 .base = S5PC100_GPI(0),
195 .ngpio = S5PC100_GPIO_I_NR,
196 .label = "GPI",
197 },
198 }, {
199 .chip = {
200 .base = S5PC100_GPJ0(0),
201 .ngpio = S5PC100_GPIO_J0_NR,
202 .label = "GPJ0",
203 },
204 }, {
205 .chip = {
206 .base = S5PC100_GPJ1(0),
207 .ngpio = S5PC100_GPIO_J1_NR,
208 .label = "GPJ1",
209 },
210 }, {
211 .chip = {
212 .base = S5PC100_GPJ2(0),
213 .ngpio = S5PC100_GPIO_J2_NR,
214 .label = "GPJ2",
215 },
216 }, {
217 .chip = {
218 .base = S5PC100_GPJ3(0),
219 .ngpio = S5PC100_GPIO_J3_NR,
220 .label = "GPJ3",
221 },
222 }, {
223 .chip = {
224 .base = S5PC100_GPJ4(0),
225 .ngpio = S5PC100_GPIO_J4_NR,
226 .label = "GPJ4",
227 },
228 }, {
229 .config = &gpio_cfg_noint,
230 .chip = {
231 .base = S5PC100_GPK0(0),
232 .ngpio = S5PC100_GPIO_K0_NR,
233 .label = "GPK0",
234 },
235 }, {
236 .config = &gpio_cfg_noint,
237 .chip = {
238 .base = S5PC100_GPK1(0),
239 .ngpio = S5PC100_GPIO_K1_NR,
240 .label = "GPK1",
241 },
242 }, {
243 .config = &gpio_cfg_noint,
244 .chip = {
245 .base = S5PC100_GPK2(0),
246 .ngpio = S5PC100_GPIO_K2_NR,
247 .label = "GPK2",
248 },
249 }, {
250 .config = &gpio_cfg_noint,
251 .chip = {
252 .base = S5PC100_GPK3(0),
253 .ngpio = S5PC100_GPIO_K3_NR,
254 .label = "GPK3",
255 },
256 }, {
257 .config = &gpio_cfg_noint,
258 .chip = {
259 .base = S5PC100_GPL0(0),
260 .ngpio = S5PC100_GPIO_L0_NR,
261 .label = "GPL0",
262 },
263 }, {
264 .config = &gpio_cfg_noint,
265 .chip = {
266 .base = S5PC100_GPL1(0),
267 .ngpio = S5PC100_GPIO_L1_NR,
268 .label = "GPL1",
269 },
270 }, {
271 .config = &gpio_cfg_noint,
272 .chip = {
273 .base = S5PC100_GPL2(0),
274 .ngpio = S5PC100_GPIO_L2_NR,
275 .label = "GPL2",
276 },
277 }, {
278 .config = &gpio_cfg_noint,
279 .chip = {
280 .base = S5PC100_GPL3(0),
281 .ngpio = S5PC100_GPIO_L3_NR,
282 .label = "GPL3",
283 },
284 }, {
285 .config = &gpio_cfg_noint,
286 .chip = {
287 .base = S5PC100_GPL4(0),
288 .ngpio = S5PC100_GPIO_L4_NR,
289 .label = "GPL4",
290 },
291 }, {
292 .base = (S5P_VA_GPIO + 0xC00),
293 .config = &gpio_cfg_eint,
294 .irq_base = IRQ_EINT(0),
295 .chip = {
296 .base = S5PC100_GPH0(0),
297 .ngpio = S5PC100_GPIO_H0_NR,
298 .label = "GPH0",
299 .to_irq = samsung_gpiolib_to_irq,
300 },
301 }, {
302 .base = (S5P_VA_GPIO + 0xC20),
303 .config = &gpio_cfg_eint,
304 .irq_base = IRQ_EINT(8),
305 .chip = {
306 .base = S5PC100_GPH1(0),
307 .ngpio = S5PC100_GPIO_H1_NR,
308 .label = "GPH1",
309 .to_irq = samsung_gpiolib_to_irq,
310 },
311 }, {
312 .base = (S5P_VA_GPIO + 0xC40),
313 .config = &gpio_cfg_eint,
314 .irq_base = IRQ_EINT(16),
315 .chip = {
316 .base = S5PC100_GPH2(0),
317 .ngpio = S5PC100_GPIO_H2_NR,
318 .label = "GPH2",
319 .to_irq = samsung_gpiolib_to_irq,
320 },
321 }, {
322 .base = (S5P_VA_GPIO + 0xC60),
323 .config = &gpio_cfg_eint,
324 .irq_base = IRQ_EINT(24),
325 .chip = {
326 .base = S5PC100_GPH3(0),
327 .ngpio = S5PC100_GPIO_H3_NR,
328 .label = "GPH3",
329 .to_irq = samsung_gpiolib_to_irq,
330 },
331 },
332};
333
334static __init int s5pc100_gpiolib_init(void)
335{
336 struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
337 int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
338 int gpioint_group = 0;
339 int i;
340
341 for (i = 0; i < nr_chips; i++, chip++) {
342 if (chip->config == NULL) {
343 chip->config = &gpio_cfg;
344 chip->group = gpioint_group++;
345 }
346 if (chip->base == NULL)
347 chip->base = S5PC100_BANK_BASE(i);
348 }
349
350 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
351 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
352
353 return 0;
354}
355core_initcall(s5pc100_gpiolib_init);
diff --git a/drivers/gpio/gpio-s5pv210.c b/drivers/gpio/gpio-s5pv210.c
new file mode 100644
index 000000000000..1ba20a703e05
--- /dev/null
+++ b/drivers/gpio/gpio-s5pv210.c
@@ -0,0 +1,288 @@
1/* linux/arch/arm/mach-s5pv210/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17#include <plat/gpio-core.h>
18#include <plat/gpio-cfg.h>
19#include <plat/gpio-cfg-helpers.h>
20#include <mach/map.h>
21
22static struct s3c_gpio_cfg gpio_cfg = {
23 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
24 .set_pull = s3c_gpio_setpull_updown,
25 .get_pull = s3c_gpio_getpull_updown,
26};
27
28static struct s3c_gpio_cfg gpio_cfg_noint = {
29 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
30 .set_pull = s3c_gpio_setpull_updown,
31 .get_pull = s3c_gpio_getpull_updown,
32};
33
34/* GPIO bank's base address given the index of the bank in the
35 * list of all gpio banks.
36 */
37#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
38
39/*
40 * Following are the gpio banks in v210.
41 *
42 * The 'config' member when left to NULL, is initialized to the default
43 * structure gpio_cfg in the init function below.
44 *
45 * The 'base' member is also initialized in the init function below.
46 * Note: The initialization of 'base' member of s3c_gpio_chip structure
47 * uses the above macro and depends on the banks being listed in order here.
48 */
49static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
50 {
51 .chip = {
52 .base = S5PV210_GPA0(0),
53 .ngpio = S5PV210_GPIO_A0_NR,
54 .label = "GPA0",
55 },
56 }, {
57 .chip = {
58 .base = S5PV210_GPA1(0),
59 .ngpio = S5PV210_GPIO_A1_NR,
60 .label = "GPA1",
61 },
62 }, {
63 .chip = {
64 .base = S5PV210_GPB(0),
65 .ngpio = S5PV210_GPIO_B_NR,
66 .label = "GPB",
67 },
68 }, {
69 .chip = {
70 .base = S5PV210_GPC0(0),
71 .ngpio = S5PV210_GPIO_C0_NR,
72 .label = "GPC0",
73 },
74 }, {
75 .chip = {
76 .base = S5PV210_GPC1(0),
77 .ngpio = S5PV210_GPIO_C1_NR,
78 .label = "GPC1",
79 },
80 }, {
81 .chip = {
82 .base = S5PV210_GPD0(0),
83 .ngpio = S5PV210_GPIO_D0_NR,
84 .label = "GPD0",
85 },
86 }, {
87 .chip = {
88 .base = S5PV210_GPD1(0),
89 .ngpio = S5PV210_GPIO_D1_NR,
90 .label = "GPD1",
91 },
92 }, {
93 .chip = {
94 .base = S5PV210_GPE0(0),
95 .ngpio = S5PV210_GPIO_E0_NR,
96 .label = "GPE0",
97 },
98 }, {
99 .chip = {
100 .base = S5PV210_GPE1(0),
101 .ngpio = S5PV210_GPIO_E1_NR,
102 .label = "GPE1",
103 },
104 }, {
105 .chip = {
106 .base = S5PV210_GPF0(0),
107 .ngpio = S5PV210_GPIO_F0_NR,
108 .label = "GPF0",
109 },
110 }, {
111 .chip = {
112 .base = S5PV210_GPF1(0),
113 .ngpio = S5PV210_GPIO_F1_NR,
114 .label = "GPF1",
115 },
116 }, {
117 .chip = {
118 .base = S5PV210_GPF2(0),
119 .ngpio = S5PV210_GPIO_F2_NR,
120 .label = "GPF2",
121 },
122 }, {
123 .chip = {
124 .base = S5PV210_GPF3(0),
125 .ngpio = S5PV210_GPIO_F3_NR,
126 .label = "GPF3",
127 },
128 }, {
129 .chip = {
130 .base = S5PV210_GPG0(0),
131 .ngpio = S5PV210_GPIO_G0_NR,
132 .label = "GPG0",
133 },
134 }, {
135 .chip = {
136 .base = S5PV210_GPG1(0),
137 .ngpio = S5PV210_GPIO_G1_NR,
138 .label = "GPG1",
139 },
140 }, {
141 .chip = {
142 .base = S5PV210_GPG2(0),
143 .ngpio = S5PV210_GPIO_G2_NR,
144 .label = "GPG2",
145 },
146 }, {
147 .chip = {
148 .base = S5PV210_GPG3(0),
149 .ngpio = S5PV210_GPIO_G3_NR,
150 .label = "GPG3",
151 },
152 }, {
153 .config = &gpio_cfg_noint,
154 .chip = {
155 .base = S5PV210_GPI(0),
156 .ngpio = S5PV210_GPIO_I_NR,
157 .label = "GPI",
158 },
159 }, {
160 .chip = {
161 .base = S5PV210_GPJ0(0),
162 .ngpio = S5PV210_GPIO_J0_NR,
163 .label = "GPJ0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV210_GPJ1(0),
168 .ngpio = S5PV210_GPIO_J1_NR,
169 .label = "GPJ1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV210_GPJ2(0),
174 .ngpio = S5PV210_GPIO_J2_NR,
175 .label = "GPJ2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV210_GPJ3(0),
180 .ngpio = S5PV210_GPIO_J3_NR,
181 .label = "GPJ3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV210_GPJ4(0),
186 .ngpio = S5PV210_GPIO_J4_NR,
187 .label = "GPJ4",
188 },
189 }, {
190 .config = &gpio_cfg_noint,
191 .chip = {
192 .base = S5PV210_MP01(0),
193 .ngpio = S5PV210_GPIO_MP01_NR,
194 .label = "MP01",
195 },
196 }, {
197 .config = &gpio_cfg_noint,
198 .chip = {
199 .base = S5PV210_MP02(0),
200 .ngpio = S5PV210_GPIO_MP02_NR,
201 .label = "MP02",
202 },
203 }, {
204 .config = &gpio_cfg_noint,
205 .chip = {
206 .base = S5PV210_MP03(0),
207 .ngpio = S5PV210_GPIO_MP03_NR,
208 .label = "MP03",
209 },
210 }, {
211 .config = &gpio_cfg_noint,
212 .chip = {
213 .base = S5PV210_MP04(0),
214 .ngpio = S5PV210_GPIO_MP04_NR,
215 .label = "MP04",
216 },
217 }, {
218 .config = &gpio_cfg_noint,
219 .chip = {
220 .base = S5PV210_MP05(0),
221 .ngpio = S5PV210_GPIO_MP05_NR,
222 .label = "MP05",
223 },
224 }, {
225 .base = (S5P_VA_GPIO + 0xC00),
226 .config = &gpio_cfg_noint,
227 .irq_base = IRQ_EINT(0),
228 .chip = {
229 .base = S5PV210_GPH0(0),
230 .ngpio = S5PV210_GPIO_H0_NR,
231 .label = "GPH0",
232 .to_irq = samsung_gpiolib_to_irq,
233 },
234 }, {
235 .base = (S5P_VA_GPIO + 0xC20),
236 .config = &gpio_cfg_noint,
237 .irq_base = IRQ_EINT(8),
238 .chip = {
239 .base = S5PV210_GPH1(0),
240 .ngpio = S5PV210_GPIO_H1_NR,
241 .label = "GPH1",
242 .to_irq = samsung_gpiolib_to_irq,
243 },
244 }, {
245 .base = (S5P_VA_GPIO + 0xC40),
246 .config = &gpio_cfg_noint,
247 .irq_base = IRQ_EINT(16),
248 .chip = {
249 .base = S5PV210_GPH2(0),
250 .ngpio = S5PV210_GPIO_H2_NR,
251 .label = "GPH2",
252 .to_irq = samsung_gpiolib_to_irq,
253 },
254 }, {
255 .base = (S5P_VA_GPIO + 0xC60),
256 .config = &gpio_cfg_noint,
257 .irq_base = IRQ_EINT(24),
258 .chip = {
259 .base = S5PV210_GPH3(0),
260 .ngpio = S5PV210_GPIO_H3_NR,
261 .label = "GPH3",
262 .to_irq = samsung_gpiolib_to_irq,
263 },
264 },
265};
266
267static __init int s5pv210_gpiolib_init(void)
268{
269 struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
270 int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
271 int gpioint_group = 0;
272 int i = 0;
273
274 for (i = 0; i < nr_chips; i++, chip++) {
275 if (chip->config == NULL) {
276 chip->config = &gpio_cfg;
277 chip->group = gpioint_group++;
278 }
279 if (chip->base == NULL)
280 chip->base = S5PV210_BANK_BASE(i);
281 }
282
283 samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
284 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
285
286 return 0;
287}
288core_initcall(s5pv210_gpiolib_init);
diff --git a/drivers/gpio/gpio-u300.c b/drivers/gpio/gpio-u300.c
new file mode 100644
index 000000000000..d92790140fe5
--- /dev/null
+++ b/drivers/gpio/gpio-u300.c
@@ -0,0 +1,700 @@
1/*
2 *
3 * arch/arm/mach-u300/gpio.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 GPIO module.
9 * This can driver either of the two basic GPIO cores
10 * available in the U300 platforms:
11 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
12 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
13 * Notice that you also have inline macros in <asm-arch/gpio.h>
14 * Author: Linus Walleij <linus.walleij@stericsson.com>
15 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
16 *
17 */
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27
28/* Reference to GPIO block clock */
29static struct clk *clk;
30
31/* Memory resource */
32static struct resource *memres;
33static void __iomem *virtbase;
34static struct device *gpiodev;
35
36struct u300_gpio_port {
37 const char *name;
38 int irq;
39 int number;
40};
41
42
43static struct u300_gpio_port gpio_ports[] = {
44 {
45 .name = "gpio0",
46 .number = 0,
47 },
48 {
49 .name = "gpio1",
50 .number = 1,
51 },
52 {
53 .name = "gpio2",
54 .number = 2,
55 },
56#ifdef U300_COH901571_3
57 {
58 .name = "gpio3",
59 .number = 3,
60 },
61 {
62 .name = "gpio4",
63 .number = 4,
64 },
65#ifdef CONFIG_MACH_U300_BS335
66 {
67 .name = "gpio5",
68 .number = 5,
69 },
70 {
71 .name = "gpio6",
72 .number = 6,
73 },
74#endif
75#endif
76
77};
78
79
80#ifdef U300_COH901571_3
81
82/* Default input value */
83#define DEFAULT_OUTPUT_LOW 0
84#define DEFAULT_OUTPUT_HIGH 1
85
86/* GPIO Pull-Up status */
87#define DISABLE_PULL_UP 0
88#define ENABLE_PULL_UP 1
89
90#define GPIO_NOT_USED 0
91#define GPIO_IN 1
92#define GPIO_OUT 2
93
94struct u300_gpio_configuration_data {
95 unsigned char pin_usage;
96 unsigned char default_output_value;
97 unsigned char pull_up;
98};
99
100/* Initial configuration */
101const struct u300_gpio_configuration_data
102u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
103#ifdef CONFIG_MACH_U300_BS335
104 /* Port 0, pins 0-7 */
105 {
106 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
107 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
108 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
109 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
110 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
111 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
112 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
113 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
114 },
115 /* Port 1, pins 0-7 */
116 {
117 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
118 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
119 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
120 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
121 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
122 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
123 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
124 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
125 },
126 /* Port 2, pins 0-7 */
127 {
128 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
129 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
130 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
131 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
132 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
133 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
134 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
135 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
136 },
137 /* Port 3, pins 0-7 */
138 {
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
140 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
141 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
142 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
144 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
145 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
146 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
147 },
148 /* Port 4, pins 0-7 */
149 {
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
152 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
153 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
155 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
156 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
157 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
158 },
159 /* Port 5, pins 0-7 */
160 {
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
163 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
164 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
166 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
167 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
168 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
169 },
170 /* Port 6, pind 0-7 */
171 {
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
174 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
175 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
177 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
178 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
179 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
180 }
181#endif
182
183#ifdef CONFIG_MACH_U300_BS365
184 /* Port 0, pins 0-7 */
185 {
186 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
187 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
188 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
189 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
190 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
191 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
192 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
193 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
194 },
195 /* Port 1, pins 0-7 */
196 {
197 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
199 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
200 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
201 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
202 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
203 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
204 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
205 },
206 /* Port 2, pins 0-7 */
207 {
208 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
209 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
210 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
211 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
213 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
214 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
215 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
216 },
217 /* Port 3, pins 0-7 */
218 {
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
221 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
222 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
224 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
225 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
226 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
227 },
228 /* Port 4, pins 0-7 */
229 {
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
231 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
232 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
233 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
234 /* These 4 pins doesn't exist on DB3210 */
235 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
236 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
237 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
238 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
239 }
240#endif
241};
242#endif
243
244
245/* No users == we can power down GPIO */
246static int gpio_users;
247
248struct gpio_struct {
249 int (*callback)(void *);
250 void *data;
251 int users;
252};
253
254static struct gpio_struct gpio_pin[U300_GPIO_MAX];
255
256/*
257 * Let drivers register callback in order to get notified when there is
258 * an interrupt on the gpio pin
259 */
260int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
261{
262 if (gpio_pin[gpio].callback)
263 dev_warn(gpiodev, "%s: WARNING: callback already "
264 "registered for gpio pin#%d\n", __func__, gpio);
265 gpio_pin[gpio].callback = func;
266 gpio_pin[gpio].data = data;
267
268 return 0;
269}
270EXPORT_SYMBOL(gpio_register_callback);
271
272int gpio_unregister_callback(unsigned gpio)
273{
274 if (!gpio_pin[gpio].callback)
275 dev_warn(gpiodev, "%s: WARNING: callback already "
276 "unregistered for gpio pin#%d\n", __func__, gpio);
277 gpio_pin[gpio].callback = NULL;
278 gpio_pin[gpio].data = NULL;
279
280 return 0;
281}
282EXPORT_SYMBOL(gpio_unregister_callback);
283
284/* Non-zero means valid */
285int gpio_is_valid(int number)
286{
287 if (number >= 0 &&
288 number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT))
289 return 1;
290 return 0;
291}
292EXPORT_SYMBOL(gpio_is_valid);
293
294int gpio_request(unsigned gpio, const char *label)
295{
296 if (gpio_pin[gpio].users)
297 return -EINVAL;
298 else
299 gpio_pin[gpio].users++;
300
301 gpio_users++;
302
303 return 0;
304}
305EXPORT_SYMBOL(gpio_request);
306
307void gpio_free(unsigned gpio)
308{
309 gpio_users--;
310 gpio_pin[gpio].users--;
311 if (unlikely(gpio_pin[gpio].users < 0)) {
312 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
313 gpio);
314 gpio_pin[gpio].users = 0;
315 }
316
317 return;
318}
319EXPORT_SYMBOL(gpio_free);
320
321/* This returns zero or nonzero */
322int gpio_get_value(unsigned gpio)
323{
324 return readl(virtbase + U300_GPIO_PXPDIR +
325 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
326}
327EXPORT_SYMBOL(gpio_get_value);
328
329/*
330 * We hope that the compiler will optimize away the unused branch
331 * in case "value" is a constant
332 */
333void gpio_set_value(unsigned gpio, int value)
334{
335 u32 val;
336 unsigned long flags;
337
338 local_irq_save(flags);
339 if (value) {
340 /* set */
341 val = readl(virtbase + U300_GPIO_PXPDOR +
342 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
343 & (1 << (gpio & 0x07));
344 writel(val | (1 << (gpio & 0x07)), virtbase +
345 U300_GPIO_PXPDOR +
346 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
347 } else {
348 /* clear */
349 val = readl(virtbase + U300_GPIO_PXPDOR +
350 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
351 & (1 << (gpio & 0x07));
352 writel(val & ~(1 << (gpio & 0x07)), virtbase +
353 U300_GPIO_PXPDOR +
354 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
355 }
356 local_irq_restore(flags);
357}
358EXPORT_SYMBOL(gpio_set_value);
359
360int gpio_direction_input(unsigned gpio)
361{
362 unsigned long flags;
363 u32 val;
364
365 if (gpio > U300_GPIO_MAX)
366 return -EINVAL;
367
368 local_irq_save(flags);
369 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
370 U300_GPIO_PORTX_SPACING);
371 /* Mask out this pin*/
372 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
373 /* This is not needed since it sets the bits to zero.*/
374 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
375 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
376 U300_GPIO_PORTX_SPACING);
377 local_irq_restore(flags);
378 return 0;
379}
380EXPORT_SYMBOL(gpio_direction_input);
381
382int gpio_direction_output(unsigned gpio, int value)
383{
384 unsigned long flags;
385 u32 val;
386
387 if (gpio > U300_GPIO_MAX)
388 return -EINVAL;
389
390 local_irq_save(flags);
391 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
392 U300_GPIO_PORTX_SPACING);
393 /* Mask out this pin */
394 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
395 /*
396 * FIXME: configure for push/pull, open drain or open source per pin
397 * in setup. The current driver will only support push/pull.
398 */
399 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
400 << ((gpio & 0x07) << 1));
401 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
402 U300_GPIO_PORTX_SPACING);
403 gpio_set_value(gpio, value);
404 local_irq_restore(flags);
405 return 0;
406}
407EXPORT_SYMBOL(gpio_direction_output);
408
409/*
410 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
411 */
412void enable_irq_on_gpio_pin(unsigned gpio, int edge)
413{
414 u32 val;
415 unsigned long flags;
416 local_irq_save(flags);
417
418 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
419 U300_GPIO_PORTX_SPACING);
420 val |= (1 << (gpio & 0x07));
421 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
422 U300_GPIO_PORTX_SPACING);
423 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
424 U300_GPIO_PORTX_SPACING);
425 if (edge)
426 val |= (1 << (gpio & 0x07));
427 else
428 val &= ~(1 << (gpio & 0x07));
429 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
430 U300_GPIO_PORTX_SPACING);
431 local_irq_restore(flags);
432}
433EXPORT_SYMBOL(enable_irq_on_gpio_pin);
434
435void disable_irq_on_gpio_pin(unsigned gpio)
436{
437 u32 val;
438 unsigned long flags;
439
440 local_irq_save(flags);
441 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
442 U300_GPIO_PORTX_SPACING);
443 val &= ~(1 << (gpio & 0x07));
444 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
445 U300_GPIO_PORTX_SPACING);
446 local_irq_restore(flags);
447}
448EXPORT_SYMBOL(disable_irq_on_gpio_pin);
449
450/* Enable (value == 0) or disable (value == 1) internal pullup */
451void gpio_pullup(unsigned gpio, int value)
452{
453 u32 val;
454 unsigned long flags;
455
456 local_irq_save(flags);
457 if (value) {
458 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
459 U300_GPIO_PORTX_SPACING);
460 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
461 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
462 } else {
463 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
464 U300_GPIO_PORTX_SPACING);
465 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
466 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
467 }
468 local_irq_restore(flags);
469}
470EXPORT_SYMBOL(gpio_pullup);
471
472static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
473{
474 struct u300_gpio_port *port = dev_id;
475 u32 val;
476 int pin;
477
478 /* Read event register */
479 val = readl(virtbase + U300_GPIO_PXIEV + port->number *
480 U300_GPIO_PORTX_SPACING);
481 /* Mask with enable register */
482 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
483 U300_GPIO_PORTX_SPACING);
484 /* Mask relevant bits */
485 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
486 /* ACK IRQ (clear event) */
487 writel(val, virtbase + U300_GPIO_PXIEV + port->number *
488 U300_GPIO_PORTX_SPACING);
489 /* Print message */
490 while (val != 0) {
491 unsigned gpio;
492
493 pin = __ffs(val);
494 /* mask off this pin */
495 val &= ~(1 << pin);
496 gpio = (port->number << 3) + pin;
497
498 if (gpio_pin[gpio].callback)
499 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
500 else
501 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
502 gpio);
503 }
504 return IRQ_HANDLED;
505}
506
507static void gpio_set_initial_values(void)
508{
509#ifdef U300_COH901571_3
510 int i, j;
511 unsigned long flags;
512 u32 val;
513
514 /* Write default values to all pins */
515 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
516 val = 0;
517 for (j = 0; j < 8; j++)
518 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
519 local_irq_save(flags);
520 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
521 local_irq_restore(flags);
522 }
523
524 /*
525 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
526 * to output and 'GPIO_IN' to input for each port. And initialize
527 * default value on outputs.
528 */
529 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
530 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
531 local_irq_save(flags);
532 val = readl(virtbase + U300_GPIO_PXPCR +
533 i * U300_GPIO_PORTX_SPACING);
534 /* Mask out this pin */
535 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
536
537 if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
538 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
539 writel(val, virtbase + U300_GPIO_PXPCR +
540 i * U300_GPIO_PORTX_SPACING);
541 local_irq_restore(flags);
542 }
543 }
544
545 /* Enable or disable the internal pull-ups in the GPIO ASIC block */
546 for (i = 0; i < U300_GPIO_MAX; i++) {
547 val = 0;
548 for (j = 0; j < 8; j++)
549 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
550 local_irq_save(flags);
551 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
552 local_irq_restore(flags);
553 }
554#endif
555}
556
557static int __init gpio_probe(struct platform_device *pdev)
558{
559 u32 val;
560 int err = 0;
561 int i;
562 int num_irqs;
563
564 gpiodev = &pdev->dev;
565 memset(gpio_pin, 0, sizeof(gpio_pin));
566
567 /* Get GPIO clock */
568 clk = clk_get(&pdev->dev, NULL);
569 if (IS_ERR(clk)) {
570 err = PTR_ERR(clk);
571 dev_err(gpiodev, "could not get GPIO clock\n");
572 goto err_no_clk;
573 }
574 err = clk_enable(clk);
575 if (err) {
576 dev_err(gpiodev, "could not enable GPIO clock\n");
577 goto err_no_clk_enable;
578 }
579
580 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 if (!memres)
582 goto err_no_resource;
583
584 if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
585 == NULL) {
586 err = -ENODEV;
587 goto err_no_ioregion;
588 }
589
590 virtbase = ioremap(memres->start, resource_size(memres));
591 if (!virtbase) {
592 err = -ENOMEM;
593 goto err_no_ioremap;
594 }
595 dev_info(gpiodev, "remapped 0x%08x to %p\n",
596 memres->start, virtbase);
597
598#ifdef U300_COH901335
599 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
600 /* Turn on the GPIO block */
601 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
602#endif
603
604#ifdef U300_COH901571_3
605 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
606 val = readl(virtbase + U300_GPIO_CR);
607 dev_info(gpiodev, "COH901571/3 block version: %d, " \
608 "number of cores: %d\n",
609 ((val & 0x0000FE00) >> 9),
610 ((val & 0x000001FC) >> 2));
611 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
612#endif
613
614 gpio_set_initial_values();
615
616 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
617
618 gpio_ports[num_irqs].irq =
619 platform_get_irq_byname(pdev,
620 gpio_ports[num_irqs].name);
621
622 err = request_irq(gpio_ports[num_irqs].irq,
623 gpio_irq_handler, IRQF_DISABLED,
624 gpio_ports[num_irqs].name,
625 &gpio_ports[num_irqs]);
626 if (err) {
627 dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
628 gpio_ports[num_irqs].name);
629 goto err_no_irq;
630 }
631 /* Turns off PortX_irq_force */
632 writel(0x0, virtbase + U300_GPIO_PXIFR +
633 num_irqs * U300_GPIO_PORTX_SPACING);
634 }
635
636 return 0;
637
638 err_no_irq:
639 for (i = 0; i < num_irqs; i++)
640 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
641 iounmap(virtbase);
642 err_no_ioremap:
643 release_mem_region(memres->start, memres->end - memres->start);
644 err_no_ioregion:
645 err_no_resource:
646 clk_disable(clk);
647 err_no_clk_enable:
648 clk_put(clk);
649 err_no_clk:
650 dev_info(gpiodev, "module ERROR:%d\n", err);
651 return err;
652}
653
654static int __exit gpio_remove(struct platform_device *pdev)
655{
656 int i;
657
658 /* Turn off the GPIO block */
659 writel(0x00000000U, virtbase + U300_GPIO_CR);
660 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
661 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
662 iounmap(virtbase);
663 release_mem_region(memres->start, memres->end - memres->start);
664 clk_disable(clk);
665 clk_put(clk);
666 return 0;
667}
668
669static struct platform_driver gpio_driver = {
670 .driver = {
671 .name = "u300-gpio",
672 },
673 .remove = __exit_p(gpio_remove),
674};
675
676
677static int __init u300_gpio_init(void)
678{
679 return platform_driver_probe(&gpio_driver, gpio_probe);
680}
681
682static void __exit u300_gpio_exit(void)
683{
684 platform_driver_unregister(&gpio_driver);
685}
686
687arch_initcall(u300_gpio_init);
688module_exit(u300_gpio_exit);
689
690MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
691
692#ifdef U300_COH901571_3
693MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
694#endif
695
696#ifdef U300_COH901335
697MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
698#endif
699
700MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 21da9c19a0cb..a971e3d043ba 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -12,6 +12,8 @@
12#include <linux/idr.h> 12#include <linux/idr.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14 14
15#define CREATE_TRACE_POINTS
16#include <trace/events/gpio.h>
15 17
16/* Optional implementation infrastructure for GPIO interfaces. 18/* Optional implementation infrastructure for GPIO interfaces.
17 * 19 *
@@ -1165,6 +1167,7 @@ struct gpio_chip *gpiochip_find(void *data,
1165 1167
1166 return chip; 1168 return chip;
1167} 1169}
1170EXPORT_SYMBOL_GPL(gpiochip_find);
1168 1171
1169/* These "optional" allocation calls help prevent drivers from stomping 1172/* These "optional" allocation calls help prevent drivers from stomping
1170 * on each other, and help provide better diagnostics in debugfs. 1173 * on each other, and help provide better diagnostics in debugfs.
@@ -1281,6 +1284,9 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
1281 err = gpio_direction_output(gpio, 1284 err = gpio_direction_output(gpio,
1282 (flags & GPIOF_INIT_HIGH) ? 1 : 0); 1285 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
1283 1286
1287 if (err)
1288 gpio_free(gpio);
1289
1284 return err; 1290 return err;
1285} 1291}
1286EXPORT_SYMBOL_GPL(gpio_request_one); 1292EXPORT_SYMBOL_GPL(gpio_request_one);
@@ -1290,7 +1296,7 @@ EXPORT_SYMBOL_GPL(gpio_request_one);
1290 * @array: array of the 'struct gpio' 1296 * @array: array of the 'struct gpio'
1291 * @num: how many GPIOs in the array 1297 * @num: how many GPIOs in the array
1292 */ 1298 */
1293int gpio_request_array(struct gpio *array, size_t num) 1299int gpio_request_array(const struct gpio *array, size_t num)
1294{ 1300{
1295 int i, err; 1301 int i, err;
1296 1302
@@ -1313,7 +1319,7 @@ EXPORT_SYMBOL_GPL(gpio_request_array);
1313 * @array: array of the 'struct gpio' 1319 * @array: array of the 'struct gpio'
1314 * @num: how many GPIOs in the array 1320 * @num: how many GPIOs in the array
1315 */ 1321 */
1316void gpio_free_array(struct gpio *array, size_t num) 1322void gpio_free_array(const struct gpio *array, size_t num)
1317{ 1323{
1318 while (num--) 1324 while (num--)
1319 gpio_free((array++)->gpio); 1325 gpio_free((array++)->gpio);
@@ -1401,6 +1407,8 @@ int gpio_direction_input(unsigned gpio)
1401 status = chip->direction_input(chip, gpio); 1407 status = chip->direction_input(chip, gpio);
1402 if (status == 0) 1408 if (status == 0)
1403 clear_bit(FLAG_IS_OUT, &desc->flags); 1409 clear_bit(FLAG_IS_OUT, &desc->flags);
1410
1411 trace_gpio_direction(chip->base + gpio, 1, status);
1404lose: 1412lose:
1405 return status; 1413 return status;
1406fail: 1414fail:
@@ -1454,6 +1462,8 @@ int gpio_direction_output(unsigned gpio, int value)
1454 status = chip->direction_output(chip, gpio, value); 1462 status = chip->direction_output(chip, gpio, value);
1455 if (status == 0) 1463 if (status == 0)
1456 set_bit(FLAG_IS_OUT, &desc->flags); 1464 set_bit(FLAG_IS_OUT, &desc->flags);
1465 trace_gpio_value(chip->base + gpio, 0, value);
1466 trace_gpio_direction(chip->base + gpio, 0, status);
1457lose: 1467lose:
1458 return status; 1468 return status;
1459fail: 1469fail:
@@ -1543,10 +1553,13 @@ EXPORT_SYMBOL_GPL(gpio_set_debounce);
1543int __gpio_get_value(unsigned gpio) 1553int __gpio_get_value(unsigned gpio)
1544{ 1554{
1545 struct gpio_chip *chip; 1555 struct gpio_chip *chip;
1556 int value;
1546 1557
1547 chip = gpio_to_chip(gpio); 1558 chip = gpio_to_chip(gpio);
1548 WARN_ON(chip->can_sleep); 1559 WARN_ON(chip->can_sleep);
1549 return chip->get ? chip->get(chip, gpio - chip->base) : 0; 1560 value = chip->get ? chip->get(chip, gpio - chip->base) : 0;
1561 trace_gpio_value(gpio, 1, value);
1562 return value;
1550} 1563}
1551EXPORT_SYMBOL_GPL(__gpio_get_value); 1564EXPORT_SYMBOL_GPL(__gpio_get_value);
1552 1565
@@ -1565,6 +1578,7 @@ void __gpio_set_value(unsigned gpio, int value)
1565 1578
1566 chip = gpio_to_chip(gpio); 1579 chip = gpio_to_chip(gpio);
1567 WARN_ON(chip->can_sleep); 1580 WARN_ON(chip->can_sleep);
1581 trace_gpio_value(gpio, 0, value);
1568 chip->set(chip, gpio - chip->base, value); 1582 chip->set(chip, gpio - chip->base, value);
1569} 1583}
1570EXPORT_SYMBOL_GPL(__gpio_set_value); 1584EXPORT_SYMBOL_GPL(__gpio_set_value);
@@ -1615,10 +1629,13 @@ EXPORT_SYMBOL_GPL(__gpio_to_irq);
1615int gpio_get_value_cansleep(unsigned gpio) 1629int gpio_get_value_cansleep(unsigned gpio)
1616{ 1630{
1617 struct gpio_chip *chip; 1631 struct gpio_chip *chip;
1632 int value;
1618 1633
1619 might_sleep_if(extra_checks); 1634 might_sleep_if(extra_checks);
1620 chip = gpio_to_chip(gpio); 1635 chip = gpio_to_chip(gpio);
1621 return chip->get ? chip->get(chip, gpio - chip->base) : 0; 1636 value = chip->get ? chip->get(chip, gpio - chip->base) : 0;
1637 trace_gpio_value(gpio, 1, value);
1638 return value;
1622} 1639}
1623EXPORT_SYMBOL_GPL(gpio_get_value_cansleep); 1640EXPORT_SYMBOL_GPL(gpio_get_value_cansleep);
1624 1641
@@ -1628,6 +1645,7 @@ void gpio_set_value_cansleep(unsigned gpio, int value)
1628 1645
1629 might_sleep_if(extra_checks); 1646 might_sleep_if(extra_checks);
1630 chip = gpio_to_chip(gpio); 1647 chip = gpio_to_chip(gpio);
1648 trace_gpio_value(gpio, 0, value);
1631 chip->set(chip, gpio - chip->base, value); 1649 chip->set(chip, gpio - chip->base, value);
1632} 1650}
1633EXPORT_SYMBOL_GPL(gpio_set_value_cansleep); 1651EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
@@ -1653,51 +1671,6 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1653 chip->get 1671 chip->get
1654 ? (chip->get(chip, i) ? "hi" : "lo") 1672 ? (chip->get(chip, i) ? "hi" : "lo")
1655 : "? "); 1673 : "? ");
1656
1657 if (!is_out) {
1658 int irq = gpio_to_irq(gpio);
1659 struct irq_desc *desc = irq_to_desc(irq);
1660
1661 /* This races with request_irq(), set_irq_type(),
1662 * and set_irq_wake() ... but those are "rare".
1663 *
1664 * More significantly, trigger type flags aren't
1665 * currently maintained by genirq.
1666 */
1667 if (irq >= 0 && desc->action) {
1668 char *trigger;
1669
1670 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
1671 case IRQ_TYPE_NONE:
1672 trigger = "(default)";
1673 break;
1674 case IRQ_TYPE_EDGE_FALLING:
1675 trigger = "edge-falling";
1676 break;
1677 case IRQ_TYPE_EDGE_RISING:
1678 trigger = "edge-rising";
1679 break;
1680 case IRQ_TYPE_EDGE_BOTH:
1681 trigger = "edge-both";
1682 break;
1683 case IRQ_TYPE_LEVEL_HIGH:
1684 trigger = "level-high";
1685 break;
1686 case IRQ_TYPE_LEVEL_LOW:
1687 trigger = "level-low";
1688 break;
1689 default:
1690 trigger = "?trigger?";
1691 break;
1692 }
1693
1694 seq_printf(s, " irq-%d %s%s",
1695 irq, trigger,
1696 (desc->status & IRQ_WAKEUP)
1697 ? " wakeup" : "");
1698 }
1699 }
1700
1701 seq_printf(s, "\n"); 1674 seq_printf(s, "\n");
1702 } 1675 }
1703} 1676}
diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/langwell_gpio.c
index 8383a8d7f994..644ba1255d3c 100644
--- a/drivers/gpio/langwell_gpio.c
+++ b/drivers/gpio/langwell_gpio.c
@@ -18,10 +18,12 @@
18/* Supports: 18/* Supports:
19 * Moorestown platform Langwell chip. 19 * Moorestown platform Langwell chip.
20 * Medfield platform Penwell chip. 20 * Medfield platform Penwell chip.
21 * Whitney point.
21 */ 22 */
22 23
23#include <linux/module.h> 24#include <linux/module.h>
24#include <linux/pci.h> 25#include <linux/pci.h>
26#include <linux/platform_device.h>
25#include <linux/kernel.h> 27#include <linux/kernel.h>
26#include <linux/delay.h> 28#include <linux/delay.h>
27#include <linux/stddef.h> 29#include <linux/stddef.h>
@@ -31,6 +33,7 @@
31#include <linux/io.h> 33#include <linux/io.h>
32#include <linux/gpio.h> 34#include <linux/gpio.h>
33#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
34 37
35/* 38/*
36 * Langwell chip has 64 pins and thus there are 2 32bit registers to control 39 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
@@ -61,6 +64,7 @@ struct lnw_gpio {
61 void *reg_base; 64 void *reg_base;
62 spinlock_t lock; 65 spinlock_t lock;
63 unsigned irq_base; 66 unsigned irq_base;
67 struct pci_dev *pdev;
64}; 68};
65 69
66static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, 70static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
@@ -102,11 +106,18 @@ static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
102 u32 value; 106 u32 value;
103 unsigned long flags; 107 unsigned long flags;
104 108
109 if (lnw->pdev)
110 pm_runtime_get(&lnw->pdev->dev);
111
105 spin_lock_irqsave(&lnw->lock, flags); 112 spin_lock_irqsave(&lnw->lock, flags);
106 value = readl(gpdr); 113 value = readl(gpdr);
107 value &= ~BIT(offset % 32); 114 value &= ~BIT(offset % 32);
108 writel(value, gpdr); 115 writel(value, gpdr);
109 spin_unlock_irqrestore(&lnw->lock, flags); 116 spin_unlock_irqrestore(&lnw->lock, flags);
117
118 if (lnw->pdev)
119 pm_runtime_put(&lnw->pdev->dev);
120
110 return 0; 121 return 0;
111} 122}
112 123
@@ -118,11 +129,19 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
118 unsigned long flags; 129 unsigned long flags;
119 130
120 lnw_gpio_set(chip, offset, value); 131 lnw_gpio_set(chip, offset, value);
132
133 if (lnw->pdev)
134 pm_runtime_get(&lnw->pdev->dev);
135
121 spin_lock_irqsave(&lnw->lock, flags); 136 spin_lock_irqsave(&lnw->lock, flags);
122 value = readl(gpdr); 137 value = readl(gpdr);
123 value |= BIT(offset % 32);; 138 value |= BIT(offset % 32);
124 writel(value, gpdr); 139 writel(value, gpdr);
125 spin_unlock_irqrestore(&lnw->lock, flags); 140 spin_unlock_irqrestore(&lnw->lock, flags);
141
142 if (lnw->pdev)
143 pm_runtime_put(&lnw->pdev->dev);
144
126 return 0; 145 return 0;
127} 146}
128 147
@@ -132,10 +151,10 @@ static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
132 return lnw->irq_base + offset; 151 return lnw->irq_base + offset;
133} 152}
134 153
135static int lnw_irq_type(unsigned irq, unsigned type) 154static int lnw_irq_type(struct irq_data *d, unsigned type)
136{ 155{
137 struct lnw_gpio *lnw = get_irq_chip_data(irq); 156 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
138 u32 gpio = irq - lnw->irq_base; 157 u32 gpio = d->irq - lnw->irq_base;
139 unsigned long flags; 158 unsigned long flags;
140 u32 value; 159 u32 value;
141 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER); 160 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
@@ -143,6 +162,10 @@ static int lnw_irq_type(unsigned irq, unsigned type)
143 162
144 if (gpio >= lnw->chip.ngpio) 163 if (gpio >= lnw->chip.ngpio)
145 return -EINVAL; 164 return -EINVAL;
165
166 if (lnw->pdev)
167 pm_runtime_get(&lnw->pdev->dev);
168
146 spin_lock_irqsave(&lnw->lock, flags); 169 spin_lock_irqsave(&lnw->lock, flags);
147 if (type & IRQ_TYPE_EDGE_RISING) 170 if (type & IRQ_TYPE_EDGE_RISING)
148 value = readl(grer) | BIT(gpio % 32); 171 value = readl(grer) | BIT(gpio % 32);
@@ -157,22 +180,25 @@ static int lnw_irq_type(unsigned irq, unsigned type)
157 writel(value, gfer); 180 writel(value, gfer);
158 spin_unlock_irqrestore(&lnw->lock, flags); 181 spin_unlock_irqrestore(&lnw->lock, flags);
159 182
183 if (lnw->pdev)
184 pm_runtime_put(&lnw->pdev->dev);
185
160 return 0; 186 return 0;
161}; 187}
162 188
163static void lnw_irq_unmask(unsigned irq) 189static void lnw_irq_unmask(struct irq_data *d)
164{ 190{
165}; 191}
166 192
167static void lnw_irq_mask(unsigned irq) 193static void lnw_irq_mask(struct irq_data *d)
168{ 194{
169}; 195}
170 196
171static struct irq_chip lnw_irqchip = { 197static struct irq_chip lnw_irqchip = {
172 .name = "LNW-GPIO", 198 .name = "LNW-GPIO",
173 .mask = lnw_irq_mask, 199 .irq_mask = lnw_irq_mask,
174 .unmask = lnw_irq_unmask, 200 .irq_unmask = lnw_irq_unmask,
175 .set_type = lnw_irq_type, 201 .irq_set_type = lnw_irq_type,
176}; 202};
177 203
178static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */ 204static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
@@ -185,28 +211,63 @@ MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
185 211
186static void lnw_irq_handler(unsigned irq, struct irq_desc *desc) 212static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
187{ 213{
188 struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq); 214 struct irq_data *data = irq_desc_get_irq_data(desc);
189 u32 base, gpio; 215 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
216 struct irq_chip *chip = irq_data_get_irq_chip(data);
217 u32 base, gpio, mask;
218 unsigned long pending;
190 void __iomem *gedr; 219 void __iomem *gedr;
191 u32 gedr_v;
192 220
193 /* check GPIO controller to check which pin triggered the interrupt */ 221 /* check GPIO controller to check which pin triggered the interrupt */
194 for (base = 0; base < lnw->chip.ngpio; base += 32) { 222 for (base = 0; base < lnw->chip.ngpio; base += 32) {
195 gedr = gpio_reg(&lnw->chip, base, GEDR); 223 gedr = gpio_reg(&lnw->chip, base, GEDR);
196 gedr_v = readl(gedr); 224 pending = readl(gedr);
197 if (!gedr_v) 225 while (pending) {
198 continue; 226 gpio = __ffs(pending);
199 for (gpio = base; gpio < base + 32; gpio++) 227 mask = BIT(gpio);
200 if (gedr_v & BIT(gpio % 32)) { 228 pending &= ~mask;
201 pr_debug("pin %d triggered\n", gpio); 229 /* Clear before handling so we can't lose an edge */
202 generic_handle_irq(lnw->irq_base + gpio); 230 writel(mask, gedr);
203 } 231 generic_handle_irq(lnw->irq_base + base + gpio);
204 /* clear the edge detect status bit */ 232 }
205 writel(gedr_v, gedr);
206 } 233 }
207 desc->chip->eoi(irq); 234
235 chip->irq_eoi(data);
236}
237
238#ifdef CONFIG_PM
239static int lnw_gpio_runtime_resume(struct device *dev)
240{
241 return 0;
208} 242}
209 243
244static int lnw_gpio_runtime_suspend(struct device *dev)
245{
246 return 0;
247}
248
249static int lnw_gpio_runtime_idle(struct device *dev)
250{
251 int err = pm_schedule_suspend(dev, 500);
252
253 if (!err)
254 return 0;
255
256 return -EBUSY;
257}
258
259#else
260#define lnw_gpio_runtime_suspend NULL
261#define lnw_gpio_runtime_resume NULL
262#define lnw_gpio_runtime_idle NULL
263#endif
264
265static const struct dev_pm_ops lnw_gpio_pm_ops = {
266 .runtime_suspend = lnw_gpio_runtime_suspend,
267 .runtime_resume = lnw_gpio_runtime_resume,
268 .runtime_idle = lnw_gpio_runtime_idle,
269};
270
210static int __devinit lnw_gpio_probe(struct pci_dev *pdev, 271static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
211 const struct pci_device_id *id) 272 const struct pci_device_id *id)
212{ 273{
@@ -266,21 +327,26 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
266 lnw->chip.base = gpio_base; 327 lnw->chip.base = gpio_base;
267 lnw->chip.ngpio = id->driver_data; 328 lnw->chip.ngpio = id->driver_data;
268 lnw->chip.can_sleep = 0; 329 lnw->chip.can_sleep = 0;
330 lnw->pdev = pdev;
269 pci_set_drvdata(pdev, lnw); 331 pci_set_drvdata(pdev, lnw);
270 retval = gpiochip_add(&lnw->chip); 332 retval = gpiochip_add(&lnw->chip);
271 if (retval) { 333 if (retval) {
272 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval); 334 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
273 goto err5; 335 goto err5;
274 } 336 }
275 set_irq_data(pdev->irq, lnw); 337 irq_set_handler_data(pdev->irq, lnw);
276 set_irq_chained_handler(pdev->irq, lnw_irq_handler); 338 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
277 for (i = 0; i < lnw->chip.ngpio; i++) { 339 for (i = 0; i < lnw->chip.ngpio; i++) {
278 set_irq_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip, 340 irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
279 handle_simple_irq, "demux"); 341 handle_simple_irq, "demux");
280 set_irq_chip_data(i + lnw->irq_base, lnw); 342 irq_set_chip_data(i + lnw->irq_base, lnw);
281 } 343 }
282 344
283 spin_lock_init(&lnw->lock); 345 spin_lock_init(&lnw->lock);
346
347 pm_runtime_put_noidle(&pdev->dev);
348 pm_runtime_allow(&pdev->dev);
349
284 goto done; 350 goto done;
285err5: 351err5:
286 kfree(lnw); 352 kfree(lnw);
@@ -298,11 +364,93 @@ static struct pci_driver lnw_gpio_driver = {
298 .name = "langwell_gpio", 364 .name = "langwell_gpio",
299 .id_table = lnw_gpio_ids, 365 .id_table = lnw_gpio_ids,
300 .probe = lnw_gpio_probe, 366 .probe = lnw_gpio_probe,
367 .driver = {
368 .pm = &lnw_gpio_pm_ops,
369 },
370};
371
372
373static int __devinit wp_gpio_probe(struct platform_device *pdev)
374{
375 struct lnw_gpio *lnw;
376 struct gpio_chip *gc;
377 struct resource *rc;
378 int retval = 0;
379
380 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
381 if (!rc)
382 return -EINVAL;
383
384 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
385 if (!lnw) {
386 dev_err(&pdev->dev,
387 "can't allocate whitneypoint_gpio chip data\n");
388 return -ENOMEM;
389 }
390 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
391 if (lnw->reg_base == NULL) {
392 retval = -EINVAL;
393 goto err_kmalloc;
394 }
395 spin_lock_init(&lnw->lock);
396 gc = &lnw->chip;
397 gc->label = dev_name(&pdev->dev);
398 gc->owner = THIS_MODULE;
399 gc->direction_input = lnw_gpio_direction_input;
400 gc->direction_output = lnw_gpio_direction_output;
401 gc->get = lnw_gpio_get;
402 gc->set = lnw_gpio_set;
403 gc->to_irq = NULL;
404 gc->base = 0;
405 gc->ngpio = 64;
406 gc->can_sleep = 0;
407 retval = gpiochip_add(gc);
408 if (retval) {
409 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
410 retval);
411 goto err_ioremap;
412 }
413 platform_set_drvdata(pdev, lnw);
414 return 0;
415err_ioremap:
416 iounmap(lnw->reg_base);
417err_kmalloc:
418 kfree(lnw);
419 return retval;
420}
421
422static int __devexit wp_gpio_remove(struct platform_device *pdev)
423{
424 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
425 int err;
426 err = gpiochip_remove(&lnw->chip);
427 if (err)
428 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
429 iounmap(lnw->reg_base);
430 kfree(lnw);
431 platform_set_drvdata(pdev, NULL);
432 return 0;
433}
434
435static struct platform_driver wp_gpio_driver = {
436 .probe = wp_gpio_probe,
437 .remove = __devexit_p(wp_gpio_remove),
438 .driver = {
439 .name = "wp_gpio",
440 .owner = THIS_MODULE,
441 },
301}; 442};
302 443
303static int __init lnw_gpio_init(void) 444static int __init lnw_gpio_init(void)
304{ 445{
305 return pci_register_driver(&lnw_gpio_driver); 446 int ret;
447 ret = pci_register_driver(&lnw_gpio_driver);
448 if (ret < 0)
449 return ret;
450 ret = platform_driver_register(&wp_gpio_driver);
451 if (ret < 0)
452 pci_unregister_driver(&lnw_gpio_driver);
453 return ret;
306} 454}
307 455
308device_initcall(lnw_gpio_init); 456device_initcall(lnw_gpio_init);
diff --git a/drivers/gpio/max732x.c b/drivers/gpio/max732x.c
index 9cad60f9e962..ad6951edc16c 100644
--- a/drivers/gpio/max732x.c
+++ b/drivers/gpio/max732x.c
@@ -327,40 +327,40 @@ static int max732x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
327 return chip->irq_base + off; 327 return chip->irq_base + off;
328} 328}
329 329
330static void max732x_irq_mask(unsigned int irq) 330static void max732x_irq_mask(struct irq_data *d)
331{ 331{
332 struct max732x_chip *chip = get_irq_chip_data(irq); 332 struct max732x_chip *chip = irq_data_get_irq_chip_data(d);
333 333
334 chip->irq_mask_cur &= ~(1 << (irq - chip->irq_base)); 334 chip->irq_mask_cur &= ~(1 << (d->irq - chip->irq_base));
335} 335}
336 336
337static void max732x_irq_unmask(unsigned int irq) 337static void max732x_irq_unmask(struct irq_data *d)
338{ 338{
339 struct max732x_chip *chip = get_irq_chip_data(irq); 339 struct max732x_chip *chip = irq_data_get_irq_chip_data(d);
340 340
341 chip->irq_mask_cur |= 1 << (irq - chip->irq_base); 341 chip->irq_mask_cur |= 1 << (d->irq - chip->irq_base);
342} 342}
343 343
344static void max732x_irq_bus_lock(unsigned int irq) 344static void max732x_irq_bus_lock(struct irq_data *d)
345{ 345{
346 struct max732x_chip *chip = get_irq_chip_data(irq); 346 struct max732x_chip *chip = irq_data_get_irq_chip_data(d);
347 347
348 mutex_lock(&chip->irq_lock); 348 mutex_lock(&chip->irq_lock);
349 chip->irq_mask_cur = chip->irq_mask; 349 chip->irq_mask_cur = chip->irq_mask;
350} 350}
351 351
352static void max732x_irq_bus_sync_unlock(unsigned int irq) 352static void max732x_irq_bus_sync_unlock(struct irq_data *d)
353{ 353{
354 struct max732x_chip *chip = get_irq_chip_data(irq); 354 struct max732x_chip *chip = irq_data_get_irq_chip_data(d);
355 355
356 max732x_irq_update_mask(chip); 356 max732x_irq_update_mask(chip);
357 mutex_unlock(&chip->irq_lock); 357 mutex_unlock(&chip->irq_lock);
358} 358}
359 359
360static int max732x_irq_set_type(unsigned int irq, unsigned int type) 360static int max732x_irq_set_type(struct irq_data *d, unsigned int type)
361{ 361{
362 struct max732x_chip *chip = get_irq_chip_data(irq); 362 struct max732x_chip *chip = irq_data_get_irq_chip_data(d);
363 uint16_t off = irq - chip->irq_base; 363 uint16_t off = d->irq - chip->irq_base;
364 uint16_t mask = 1 << off; 364 uint16_t mask = 1 << off;
365 365
366 if (!(mask & chip->dir_input)) { 366 if (!(mask & chip->dir_input)) {
@@ -371,7 +371,7 @@ static int max732x_irq_set_type(unsigned int irq, unsigned int type)
371 371
372 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 372 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
373 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 373 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
374 irq, type); 374 d->irq, type);
375 return -EINVAL; 375 return -EINVAL;
376 } 376 }
377 377
@@ -390,11 +390,11 @@ static int max732x_irq_set_type(unsigned int irq, unsigned int type)
390 390
391static struct irq_chip max732x_irq_chip = { 391static struct irq_chip max732x_irq_chip = {
392 .name = "max732x", 392 .name = "max732x",
393 .mask = max732x_irq_mask, 393 .irq_mask = max732x_irq_mask,
394 .unmask = max732x_irq_unmask, 394 .irq_unmask = max732x_irq_unmask,
395 .bus_lock = max732x_irq_bus_lock, 395 .irq_bus_lock = max732x_irq_bus_lock,
396 .bus_sync_unlock = max732x_irq_bus_sync_unlock, 396 .irq_bus_sync_unlock = max732x_irq_bus_sync_unlock,
397 .set_type = max732x_irq_set_type, 397 .irq_set_type = max732x_irq_set_type,
398}; 398};
399 399
400static uint8_t max732x_irq_pending(struct max732x_chip *chip) 400static uint8_t max732x_irq_pending(struct max732x_chip *chip)
@@ -470,14 +470,14 @@ static int max732x_irq_setup(struct max732x_chip *chip,
470 if (!(chip->dir_input & (1 << lvl))) 470 if (!(chip->dir_input & (1 << lvl)))
471 continue; 471 continue;
472 472
473 set_irq_chip_data(irq, chip); 473 irq_set_chip_data(irq, chip);
474 set_irq_chip_and_handler(irq, &max732x_irq_chip, 474 irq_set_chip_and_handler(irq, &max732x_irq_chip,
475 handle_edge_irq); 475 handle_edge_irq);
476 set_irq_nested_thread(irq, 1); 476 irq_set_nested_thread(irq, 1);
477#ifdef CONFIG_ARM 477#ifdef CONFIG_ARM
478 set_irq_flags(irq, IRQF_VALID); 478 set_irq_flags(irq, IRQF_VALID);
479#else 479#else
480 set_irq_noprobe(irq); 480 irq_set_noprobe(irq);
481#endif 481#endif
482 } 482 }
483 483
diff --git a/drivers/gpio/mc33880.c b/drivers/gpio/mc33880.c
index 935479da6705..4ec797593bdb 100644
--- a/drivers/gpio/mc33880.c
+++ b/drivers/gpio/mc33880.c
@@ -45,7 +45,7 @@
45 * To save time we cache them here in memory 45 * To save time we cache them here in memory
46 */ 46 */
47struct mc33880 { 47struct mc33880 {
48 struct mutex lock; /* protect from simultanous accesses */ 48 struct mutex lock; /* protect from simultaneous accesses */
49 u8 port_config; 49 u8 port_config;
50 struct gpio_chip chip; 50 struct gpio_chip chip;
51 struct spi_device *spi; 51 struct spi_device *spi;
@@ -146,7 +146,7 @@ exit_destroy:
146 return ret; 146 return ret;
147} 147}
148 148
149static int mc33880_remove(struct spi_device *spi) 149static int __devexit mc33880_remove(struct spi_device *spi)
150{ 150{
151 struct mc33880 *mc; 151 struct mc33880 *mc;
152 int ret; 152 int ret;
diff --git a/drivers/gpio/mcp23s08.c b/drivers/gpio/mcp23s08.c
index 69f6f1955a31..40e076083ec0 100644
--- a/drivers/gpio/mcp23s08.c
+++ b/drivers/gpio/mcp23s08.c
@@ -10,7 +10,13 @@
10#include <linux/spi/spi.h> 10#include <linux/spi/spi.h>
11#include <linux/spi/mcp23s08.h> 11#include <linux/spi/mcp23s08.h>
12#include <linux/slab.h> 12#include <linux/slab.h>
13#include <asm/byteorder.h>
13 14
15/**
16 * MCP types supported by driver
17 */
18#define MCP_TYPE_S08 0
19#define MCP_TYPE_S17 1
14 20
15/* Registers are all 8 bits wide. 21/* Registers are all 8 bits wide.
16 * 22 *
@@ -35,27 +41,38 @@
35#define MCP_GPIO 0x09 41#define MCP_GPIO 0x09
36#define MCP_OLAT 0x0a 42#define MCP_OLAT 0x0a
37 43
44struct mcp23s08;
45
46struct mcp23s08_ops {
47 int (*read)(struct mcp23s08 *mcp, unsigned reg);
48 int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val);
49 int (*read_regs)(struct mcp23s08 *mcp, unsigned reg,
50 u16 *vals, unsigned n);
51};
52
38struct mcp23s08 { 53struct mcp23s08 {
39 struct spi_device *spi; 54 struct spi_device *spi;
40 u8 addr; 55 u8 addr;
41 56
42 u8 cache[11]; 57 u16 cache[11];
43 /* lock protects the cached values */ 58 /* lock protects the cached values */
44 struct mutex lock; 59 struct mutex lock;
45 60
46 struct gpio_chip chip; 61 struct gpio_chip chip;
47 62
48 struct work_struct work; 63 struct work_struct work;
64
65 const struct mcp23s08_ops *ops;
49}; 66};
50 67
51/* A given spi_device can represent up to four mcp23s08 chips 68/* A given spi_device can represent up to eight mcp23sxx chips
52 * sharing the same chipselect but using different addresses 69 * sharing the same chipselect but using different addresses
53 * (e.g. chips #0 and #3 might be populated, but not #1 or $2). 70 * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
54 * Driver data holds all the per-chip data. 71 * Driver data holds all the per-chip data.
55 */ 72 */
56struct mcp23s08_driver_data { 73struct mcp23s08_driver_data {
57 unsigned ngpio; 74 unsigned ngpio;
58 struct mcp23s08 *mcp[4]; 75 struct mcp23s08 *mcp[8];
59 struct mcp23s08 chip[]; 76 struct mcp23s08 chip[];
60}; 77};
61 78
@@ -70,7 +87,7 @@ static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
70 return (status < 0) ? status : rx[0]; 87 return (status < 0) ? status : rx[0];
71} 88}
72 89
73static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, u8 val) 90static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
74{ 91{
75 u8 tx[3]; 92 u8 tx[3];
76 93
@@ -81,17 +98,81 @@ static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, u8 val)
81} 98}
82 99
83static int 100static int
84mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u8 *vals, unsigned n) 101mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
85{ 102{
86 u8 tx[2]; 103 u8 tx[2], *tmp;
104 int status;
87 105
88 if ((n + reg) > sizeof mcp->cache) 106 if ((n + reg) > sizeof mcp->cache)
89 return -EINVAL; 107 return -EINVAL;
90 tx[0] = mcp->addr | 0x01; 108 tx[0] = mcp->addr | 0x01;
91 tx[1] = reg; 109 tx[1] = reg;
92 return spi_write_then_read(mcp->spi, tx, sizeof tx, vals, n); 110
111 tmp = (u8 *)vals;
112 status = spi_write_then_read(mcp->spi, tx, sizeof tx, tmp, n);
113 if (status >= 0) {
114 while (n--)
115 vals[n] = tmp[n]; /* expand to 16bit */
116 }
117 return status;
118}
119
120static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
121{
122 u8 tx[2], rx[2];
123 int status;
124
125 tx[0] = mcp->addr | 0x01;
126 tx[1] = reg << 1;
127 status = spi_write_then_read(mcp->spi, tx, sizeof tx, rx, sizeof rx);
128 return (status < 0) ? status : (rx[0] | (rx[1] << 8));
129}
130
131static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
132{
133 u8 tx[4];
134
135 tx[0] = mcp->addr;
136 tx[1] = reg << 1;
137 tx[2] = val;
138 tx[3] = val >> 8;
139 return spi_write_then_read(mcp->spi, tx, sizeof tx, NULL, 0);
140}
141
142static int
143mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
144{
145 u8 tx[2];
146 int status;
147
148 if ((n + reg) > sizeof mcp->cache)
149 return -EINVAL;
150 tx[0] = mcp->addr | 0x01;
151 tx[1] = reg << 1;
152
153 status = spi_write_then_read(mcp->spi, tx, sizeof tx,
154 (u8 *)vals, n * 2);
155 if (status >= 0) {
156 while (n--)
157 vals[n] = __le16_to_cpu((__le16)vals[n]);
158 }
159
160 return status;
93} 161}
94 162
163static const struct mcp23s08_ops mcp23s08_ops = {
164 .read = mcp23s08_read,
165 .write = mcp23s08_write,
166 .read_regs = mcp23s08_read_regs,
167};
168
169static const struct mcp23s08_ops mcp23s17_ops = {
170 .read = mcp23s17_read,
171 .write = mcp23s17_write,
172 .read_regs = mcp23s17_read_regs,
173};
174
175
95/*----------------------------------------------------------------------*/ 176/*----------------------------------------------------------------------*/
96 177
97static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) 178static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -101,7 +182,7 @@ static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
101 182
102 mutex_lock(&mcp->lock); 183 mutex_lock(&mcp->lock);
103 mcp->cache[MCP_IODIR] |= (1 << offset); 184 mcp->cache[MCP_IODIR] |= (1 << offset);
104 status = mcp23s08_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); 185 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
105 mutex_unlock(&mcp->lock); 186 mutex_unlock(&mcp->lock);
106 return status; 187 return status;
107} 188}
@@ -114,7 +195,7 @@ static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
114 mutex_lock(&mcp->lock); 195 mutex_lock(&mcp->lock);
115 196
116 /* REVISIT reading this clears any IRQ ... */ 197 /* REVISIT reading this clears any IRQ ... */
117 status = mcp23s08_read(mcp, MCP_GPIO); 198 status = mcp->ops->read(mcp, MCP_GPIO);
118 if (status < 0) 199 if (status < 0)
119 status = 0; 200 status = 0;
120 else { 201 else {
@@ -127,20 +208,20 @@ static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
127 208
128static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value) 209static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
129{ 210{
130 u8 olat = mcp->cache[MCP_OLAT]; 211 unsigned olat = mcp->cache[MCP_OLAT];
131 212
132 if (value) 213 if (value)
133 olat |= mask; 214 olat |= mask;
134 else 215 else
135 olat &= ~mask; 216 olat &= ~mask;
136 mcp->cache[MCP_OLAT] = olat; 217 mcp->cache[MCP_OLAT] = olat;
137 return mcp23s08_write(mcp, MCP_OLAT, olat); 218 return mcp->ops->write(mcp, MCP_OLAT, olat);
138} 219}
139 220
140static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) 221static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
141{ 222{
142 struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); 223 struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
143 u8 mask = 1 << offset; 224 unsigned mask = 1 << offset;
144 225
145 mutex_lock(&mcp->lock); 226 mutex_lock(&mcp->lock);
146 __mcp23s08_set(mcp, mask, value); 227 __mcp23s08_set(mcp, mask, value);
@@ -151,14 +232,14 @@ static int
151mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) 232mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
152{ 233{
153 struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); 234 struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
154 u8 mask = 1 << offset; 235 unsigned mask = 1 << offset;
155 int status; 236 int status;
156 237
157 mutex_lock(&mcp->lock); 238 mutex_lock(&mcp->lock);
158 status = __mcp23s08_set(mcp, mask, value); 239 status = __mcp23s08_set(mcp, mask, value);
159 if (status == 0) { 240 if (status == 0) {
160 mcp->cache[MCP_IODIR] &= ~mask; 241 mcp->cache[MCP_IODIR] &= ~mask;
161 status = mcp23s08_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); 242 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
162 } 243 }
163 mutex_unlock(&mcp->lock); 244 mutex_unlock(&mcp->lock);
164 return status; 245 return status;
@@ -184,16 +265,16 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
184 mcp = container_of(chip, struct mcp23s08, chip); 265 mcp = container_of(chip, struct mcp23s08, chip);
185 266
186 /* NOTE: we only handle one bank for now ... */ 267 /* NOTE: we only handle one bank for now ... */
187 bank = '0' + ((mcp->addr >> 1) & 0x3); 268 bank = '0' + ((mcp->addr >> 1) & 0x7);
188 269
189 mutex_lock(&mcp->lock); 270 mutex_lock(&mcp->lock);
190 t = mcp23s08_read_regs(mcp, 0, mcp->cache, sizeof mcp->cache); 271 t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
191 if (t < 0) { 272 if (t < 0) {
192 seq_printf(s, " I/O ERROR %d\n", t); 273 seq_printf(s, " I/O ERROR %d\n", t);
193 goto done; 274 goto done;
194 } 275 }
195 276
196 for (t = 0, mask = 1; t < 8; t++, mask <<= 1) { 277 for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
197 const char *label; 278 const char *label;
198 279
199 label = gpiochip_is_requested(chip, t); 280 label = gpiochip_is_requested(chip, t);
@@ -219,28 +300,33 @@ done:
219/*----------------------------------------------------------------------*/ 300/*----------------------------------------------------------------------*/
220 301
221static int mcp23s08_probe_one(struct spi_device *spi, unsigned addr, 302static int mcp23s08_probe_one(struct spi_device *spi, unsigned addr,
222 unsigned base, unsigned pullups) 303 unsigned type, unsigned base, unsigned pullups)
223{ 304{
224 struct mcp23s08_driver_data *data = spi_get_drvdata(spi); 305 struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
225 struct mcp23s08 *mcp = data->mcp[addr]; 306 struct mcp23s08 *mcp = data->mcp[addr];
226 int status; 307 int status;
227 int do_update = 0;
228 308
229 mutex_init(&mcp->lock); 309 mutex_init(&mcp->lock);
230 310
231 mcp->spi = spi; 311 mcp->spi = spi;
232 mcp->addr = 0x40 | (addr << 1); 312 mcp->addr = 0x40 | (addr << 1);
233 313
234 mcp->chip.label = "mcp23s08",
235
236 mcp->chip.direction_input = mcp23s08_direction_input; 314 mcp->chip.direction_input = mcp23s08_direction_input;
237 mcp->chip.get = mcp23s08_get; 315 mcp->chip.get = mcp23s08_get;
238 mcp->chip.direction_output = mcp23s08_direction_output; 316 mcp->chip.direction_output = mcp23s08_direction_output;
239 mcp->chip.set = mcp23s08_set; 317 mcp->chip.set = mcp23s08_set;
240 mcp->chip.dbg_show = mcp23s08_dbg_show; 318 mcp->chip.dbg_show = mcp23s08_dbg_show;
241 319
320 if (type == MCP_TYPE_S17) {
321 mcp->ops = &mcp23s17_ops;
322 mcp->chip.ngpio = 16;
323 mcp->chip.label = "mcp23s17";
324 } else {
325 mcp->ops = &mcp23s08_ops;
326 mcp->chip.ngpio = 8;
327 mcp->chip.label = "mcp23s08";
328 }
242 mcp->chip.base = base; 329 mcp->chip.base = base;
243 mcp->chip.ngpio = 8;
244 mcp->chip.can_sleep = 1; 330 mcp->chip.can_sleep = 1;
245 mcp->chip.dev = &spi->dev; 331 mcp->chip.dev = &spi->dev;
246 mcp->chip.owner = THIS_MODULE; 332 mcp->chip.owner = THIS_MODULE;
@@ -248,45 +334,39 @@ static int mcp23s08_probe_one(struct spi_device *spi, unsigned addr,
248 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, 334 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
249 * and MCP_IOCON.HAEN = 1, so we work with all chips. 335 * and MCP_IOCON.HAEN = 1, so we work with all chips.
250 */ 336 */
251 status = mcp23s08_read(mcp, MCP_IOCON); 337 status = mcp->ops->read(mcp, MCP_IOCON);
252 if (status < 0) 338 if (status < 0)
253 goto fail; 339 goto fail;
254 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN)) { 340 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN)) {
255 status &= ~IOCON_SEQOP; 341 /* mcp23s17 has IOCON twice, make sure they are in sync */
256 status |= IOCON_HAEN; 342 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
257 status = mcp23s08_write(mcp, MCP_IOCON, (u8) status); 343 status |= IOCON_HAEN | (IOCON_HAEN << 8);
344 status = mcp->ops->write(mcp, MCP_IOCON, status);
258 if (status < 0) 345 if (status < 0)
259 goto fail; 346 goto fail;
260 } 347 }
261 348
262 /* configure ~100K pullups */ 349 /* configure ~100K pullups */
263 status = mcp23s08_write(mcp, MCP_GPPU, pullups); 350 status = mcp->ops->write(mcp, MCP_GPPU, pullups);
264 if (status < 0) 351 if (status < 0)
265 goto fail; 352 goto fail;
266 353
267 status = mcp23s08_read_regs(mcp, 0, mcp->cache, sizeof mcp->cache); 354 status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
268 if (status < 0) 355 if (status < 0)
269 goto fail; 356 goto fail;
270 357
271 /* disable inverter on input */ 358 /* disable inverter on input */
272 if (mcp->cache[MCP_IPOL] != 0) { 359 if (mcp->cache[MCP_IPOL] != 0) {
273 mcp->cache[MCP_IPOL] = 0; 360 mcp->cache[MCP_IPOL] = 0;
274 do_update = 1; 361 status = mcp->ops->write(mcp, MCP_IPOL, 0);
362 if (status < 0)
363 goto fail;
275 } 364 }
276 365
277 /* disable irqs */ 366 /* disable irqs */
278 if (mcp->cache[MCP_GPINTEN] != 0) { 367 if (mcp->cache[MCP_GPINTEN] != 0) {
279 mcp->cache[MCP_GPINTEN] = 0; 368 mcp->cache[MCP_GPINTEN] = 0;
280 do_update = 1; 369 status = mcp->ops->write(mcp, MCP_GPINTEN, 0);
281 }
282
283 if (do_update) {
284 u8 tx[4];
285
286 tx[0] = mcp->addr;
287 tx[1] = MCP_IPOL;
288 memcpy(&tx[2], &mcp->cache[MCP_IPOL], sizeof(tx) - 2);
289 status = spi_write_then_read(mcp->spi, tx, sizeof tx, NULL, 0);
290 if (status < 0) 370 if (status < 0)
291 goto fail; 371 goto fail;
292 } 372 }
@@ -305,19 +385,26 @@ static int mcp23s08_probe(struct spi_device *spi)
305 unsigned addr; 385 unsigned addr;
306 unsigned chips = 0; 386 unsigned chips = 0;
307 struct mcp23s08_driver_data *data; 387 struct mcp23s08_driver_data *data;
308 int status; 388 int status, type;
309 unsigned base; 389 unsigned base;
310 390
391 type = spi_get_device_id(spi)->driver_data;
392
311 pdata = spi->dev.platform_data; 393 pdata = spi->dev.platform_data;
312 if (!pdata || !gpio_is_valid(pdata->base)) { 394 if (!pdata || !gpio_is_valid(pdata->base)) {
313 dev_dbg(&spi->dev, "invalid or missing platform data\n"); 395 dev_dbg(&spi->dev, "invalid or missing platform data\n");
314 return -EINVAL; 396 return -EINVAL;
315 } 397 }
316 398
317 for (addr = 0; addr < 4; addr++) { 399 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
318 if (!pdata->chip[addr].is_present) 400 if (!pdata->chip[addr].is_present)
319 continue; 401 continue;
320 chips++; 402 chips++;
403 if ((type == MCP_TYPE_S08) && (addr > 3)) {
404 dev_err(&spi->dev,
405 "mcp23s08 only supports address 0..3\n");
406 return -EINVAL;
407 }
321 } 408 }
322 if (!chips) 409 if (!chips)
323 return -ENODEV; 410 return -ENODEV;
@@ -329,16 +416,17 @@ static int mcp23s08_probe(struct spi_device *spi)
329 spi_set_drvdata(spi, data); 416 spi_set_drvdata(spi, data);
330 417
331 base = pdata->base; 418 base = pdata->base;
332 for (addr = 0; addr < 4; addr++) { 419 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
333 if (!pdata->chip[addr].is_present) 420 if (!pdata->chip[addr].is_present)
334 continue; 421 continue;
335 chips--; 422 chips--;
336 data->mcp[addr] = &data->chip[chips]; 423 data->mcp[addr] = &data->chip[chips];
337 status = mcp23s08_probe_one(spi, addr, base, 424 status = mcp23s08_probe_one(spi, addr, type, base,
338 pdata->chip[addr].pullups); 425 pdata->chip[addr].pullups);
339 if (status < 0) 426 if (status < 0)
340 goto fail; 427 goto fail;
341 base += 8; 428
429 base += (type == MCP_TYPE_S17) ? 16 : 8;
342 } 430 }
343 data->ngpio = base - pdata->base; 431 data->ngpio = base - pdata->base;
344 432
@@ -358,7 +446,7 @@ static int mcp23s08_probe(struct spi_device *spi)
358 return 0; 446 return 0;
359 447
360fail: 448fail:
361 for (addr = 0; addr < 4; addr++) { 449 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
362 int tmp; 450 int tmp;
363 451
364 if (!data->mcp[addr]) 452 if (!data->mcp[addr])
@@ -388,7 +476,7 @@ static int mcp23s08_remove(struct spi_device *spi)
388 } 476 }
389 } 477 }
390 478
391 for (addr = 0; addr < 4; addr++) { 479 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
392 int tmp; 480 int tmp;
393 481
394 if (!data->mcp[addr]) 482 if (!data->mcp[addr])
@@ -405,9 +493,17 @@ static int mcp23s08_remove(struct spi_device *spi)
405 return status; 493 return status;
406} 494}
407 495
496static const struct spi_device_id mcp23s08_ids[] = {
497 { "mcp23s08", MCP_TYPE_S08 },
498 { "mcp23s17", MCP_TYPE_S17 },
499 { },
500};
501MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
502
408static struct spi_driver mcp23s08_driver = { 503static struct spi_driver mcp23s08_driver = {
409 .probe = mcp23s08_probe, 504 .probe = mcp23s08_probe,
410 .remove = mcp23s08_remove, 505 .remove = mcp23s08_remove,
506 .id_table = mcp23s08_ids,
411 .driver = { 507 .driver = {
412 .name = "mcp23s08", 508 .name = "mcp23s08",
413 .owner = THIS_MODULE, 509 .owner = THIS_MODULE,
@@ -432,4 +528,3 @@ static void __exit mcp23s08_exit(void)
432module_exit(mcp23s08_exit); 528module_exit(mcp23s08_exit);
433 529
434MODULE_LICENSE("GPL"); 530MODULE_LICENSE("GPL");
435MODULE_ALIAS("spi:mcp23s08");
diff --git a/drivers/gpio/ml_ioh_gpio.c b/drivers/gpio/ml_ioh_gpio.c
new file mode 100644
index 000000000000..1bc621ac3536
--- /dev/null
+++ b/drivers/gpio/ml_ioh_gpio.c
@@ -0,0 +1,357 @@
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/pci.h>
20#include <linux/gpio.h>
21
22#define PCI_VENDOR_ID_ROHM 0x10DB
23
24struct ioh_reg_comn {
25 u32 ien;
26 u32 istatus;
27 u32 idisp;
28 u32 iclr;
29 u32 imask;
30 u32 imaskclr;
31 u32 po;
32 u32 pi;
33 u32 pm;
34 u32 im_0;
35 u32 im_1;
36 u32 reserved;
37};
38
39struct ioh_regs {
40 struct ioh_reg_comn regs[8];
41 u32 reserve1[16];
42 u32 ioh_sel_reg[4];
43 u32 reserve2[11];
44 u32 srst;
45};
46
47/**
48 * struct ioh_gpio_reg_data - The register store data.
49 * @po_reg: To store contents of PO register.
50 * @pm_reg: To store contents of PM register.
51 */
52struct ioh_gpio_reg_data {
53 u32 po_reg;
54 u32 pm_reg;
55};
56
57/**
58 * struct ioh_gpio - GPIO private data structure.
59 * @base: PCI base address of Memory mapped I/O register.
60 * @reg: Memory mapped IOH GPIO register list.
61 * @dev: Pointer to device structure.
62 * @gpio: Data for GPIO infrastructure.
63 * @ioh_gpio_reg: Memory mapped Register data is saved here
64 * when suspend.
65 * @ch: Indicate GPIO channel
66 */
67struct ioh_gpio {
68 void __iomem *base;
69 struct ioh_regs __iomem *reg;
70 struct device *dev;
71 struct gpio_chip gpio;
72 struct ioh_gpio_reg_data ioh_gpio_reg;
73 struct mutex lock;
74 int ch;
75};
76
77static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
78
79static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
80{
81 u32 reg_val;
82 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
83
84 mutex_lock(&chip->lock);
85 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
86 if (val)
87 reg_val |= (1 << nr);
88 else
89 reg_val &= ~(1 << nr);
90
91 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
92 mutex_unlock(&chip->lock);
93}
94
95static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
96{
97 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
98
99 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
100}
101
102static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
103 int val)
104{
105 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
106 u32 pm;
107 u32 reg_val;
108
109 mutex_lock(&chip->lock);
110 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
111 ((1 << num_ports[chip->ch]) - 1);
112 pm |= (1 << nr);
113 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
114
115 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
116 if (val)
117 reg_val |= (1 << nr);
118 else
119 reg_val &= ~(1 << nr);
120 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
121
122 mutex_unlock(&chip->lock);
123
124 return 0;
125}
126
127static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
128{
129 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
130 u32 pm;
131
132 mutex_lock(&chip->lock);
133 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
134 ((1 << num_ports[chip->ch]) - 1);
135 pm &= ~(1 << nr);
136 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
137 mutex_unlock(&chip->lock);
138
139 return 0;
140}
141
142#ifdef CONFIG_PM
143/*
144 * Save register configuration and disable interrupts.
145 */
146static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
147{
148 chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
149 chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
150}
151
152/*
153 * This function restores the register configuration of the GPIO device.
154 */
155static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
156{
157 /* to store contents of PO register */
158 iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
159 /* to store contents of PM register */
160 iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
161}
162#endif
163
164static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
165{
166 struct gpio_chip *gpio = &chip->gpio;
167
168 gpio->label = dev_name(chip->dev);
169 gpio->owner = THIS_MODULE;
170 gpio->direction_input = ioh_gpio_direction_input;
171 gpio->get = ioh_gpio_get;
172 gpio->direction_output = ioh_gpio_direction_output;
173 gpio->set = ioh_gpio_set;
174 gpio->dbg_show = NULL;
175 gpio->base = -1;
176 gpio->ngpio = num_port;
177 gpio->can_sleep = 0;
178}
179
180static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
181 const struct pci_device_id *id)
182{
183 int ret;
184 int i;
185 struct ioh_gpio *chip;
186 void __iomem *base;
187 void __iomem *chip_save;
188
189 ret = pci_enable_device(pdev);
190 if (ret) {
191 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
192 goto err_pci_enable;
193 }
194
195 ret = pci_request_regions(pdev, KBUILD_MODNAME);
196 if (ret) {
197 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
198 goto err_request_regions;
199 }
200
201 base = pci_iomap(pdev, 1, 0);
202 if (base == 0) {
203 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
204 ret = -ENOMEM;
205 goto err_iomap;
206 }
207
208 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
209 if (chip_save == NULL) {
210 dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
211 ret = -ENOMEM;
212 goto err_kzalloc;
213 }
214
215 chip = chip_save;
216 for (i = 0; i < 8; i++, chip++) {
217 chip->dev = &pdev->dev;
218 chip->base = base;
219 chip->reg = chip->base;
220 chip->ch = i;
221 mutex_init(&chip->lock);
222 ioh_gpio_setup(chip, num_ports[i]);
223 ret = gpiochip_add(&chip->gpio);
224 if (ret) {
225 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
226 goto err_gpiochip_add;
227 }
228 }
229
230 chip = chip_save;
231 pci_set_drvdata(pdev, chip);
232
233 return 0;
234
235err_gpiochip_add:
236 for (; i != 0; i--) {
237 chip--;
238 ret = gpiochip_remove(&chip->gpio);
239 if (ret)
240 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
241 }
242 kfree(chip_save);
243
244err_kzalloc:
245 pci_iounmap(pdev, base);
246
247err_iomap:
248 pci_release_regions(pdev);
249
250err_request_regions:
251 pci_disable_device(pdev);
252
253err_pci_enable:
254
255 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
256 return ret;
257}
258
259static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
260{
261 int err;
262 int i;
263 struct ioh_gpio *chip = pci_get_drvdata(pdev);
264 void __iomem *chip_save;
265
266 chip_save = chip;
267 for (i = 0; i < 8; i++, chip++) {
268 err = gpiochip_remove(&chip->gpio);
269 if (err)
270 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
271 }
272
273 chip = chip_save;
274 pci_iounmap(pdev, chip->base);
275 pci_release_regions(pdev);
276 pci_disable_device(pdev);
277 kfree(chip);
278}
279
280#ifdef CONFIG_PM
281static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
282{
283 s32 ret;
284 struct ioh_gpio *chip = pci_get_drvdata(pdev);
285
286 ioh_gpio_save_reg_conf(chip);
287 ioh_gpio_restore_reg_conf(chip);
288
289 ret = pci_save_state(pdev);
290 if (ret) {
291 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
292 return ret;
293 }
294 pci_disable_device(pdev);
295 pci_set_power_state(pdev, PCI_D0);
296 ret = pci_enable_wake(pdev, PCI_D0, 1);
297 if (ret)
298 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
299
300 return 0;
301}
302
303static int ioh_gpio_resume(struct pci_dev *pdev)
304{
305 s32 ret;
306 struct ioh_gpio *chip = pci_get_drvdata(pdev);
307
308 ret = pci_enable_wake(pdev, PCI_D0, 0);
309
310 pci_set_power_state(pdev, PCI_D0);
311 ret = pci_enable_device(pdev);
312 if (ret) {
313 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
314 return ret;
315 }
316 pci_restore_state(pdev);
317
318 iowrite32(0x01, &chip->reg->srst);
319 iowrite32(0x00, &chip->reg->srst);
320 ioh_gpio_restore_reg_conf(chip);
321
322 return 0;
323}
324#else
325#define ioh_gpio_suspend NULL
326#define ioh_gpio_resume NULL
327#endif
328
329static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
330 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
331 { 0, }
332};
333MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
334
335static struct pci_driver ioh_gpio_driver = {
336 .name = "ml_ioh_gpio",
337 .id_table = ioh_gpio_pcidev_id,
338 .probe = ioh_gpio_probe,
339 .remove = __devexit_p(ioh_gpio_remove),
340 .suspend = ioh_gpio_suspend,
341 .resume = ioh_gpio_resume
342};
343
344static int __init ioh_gpio_pci_init(void)
345{
346 return pci_register_driver(&ioh_gpio_driver);
347}
348module_init(ioh_gpio_pci_init);
349
350static void __exit ioh_gpio_pci_exit(void)
351{
352 pci_unregister_driver(&ioh_gpio_driver);
353}
354module_exit(ioh_gpio_pci_exit);
355
356MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
357MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index a2b12aa1f2b9..0451d7ac94ac 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -24,33 +24,46 @@
24#include <linux/of_gpio.h> 24#include <linux/of_gpio.h>
25#endif 25#endif
26 26
27#define PCA953X_INPUT 0 27#define PCA953X_INPUT 0
28#define PCA953X_OUTPUT 1 28#define PCA953X_OUTPUT 1
29#define PCA953X_INVERT 2 29#define PCA953X_INVERT 2
30#define PCA953X_DIRECTION 3 30#define PCA953X_DIRECTION 3
31 31
32#define PCA953X_GPIOS 0x00FF 32#define PCA957X_IN 0
33#define PCA953X_INT 0x0100 33#define PCA957X_INVRT 1
34#define PCA957X_BKEN 2
35#define PCA957X_PUPD 3
36#define PCA957X_CFG 4
37#define PCA957X_OUT 5
38#define PCA957X_MSK 6
39#define PCA957X_INTS 7
40
41#define PCA_GPIO_MASK 0x00FF
42#define PCA_INT 0x0100
43#define PCA953X_TYPE 0x1000
44#define PCA957X_TYPE 0x2000
34 45
35static const struct i2c_device_id pca953x_id[] = { 46static const struct i2c_device_id pca953x_id[] = {
36 { "pca9534", 8 | PCA953X_INT, }, 47 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
37 { "pca9535", 16 | PCA953X_INT, }, 48 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
38 { "pca9536", 4, }, 49 { "pca9536", 4 | PCA953X_TYPE, },
39 { "pca9537", 4 | PCA953X_INT, }, 50 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
40 { "pca9538", 8 | PCA953X_INT, }, 51 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
41 { "pca9539", 16 | PCA953X_INT, }, 52 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
42 { "pca9554", 8 | PCA953X_INT, }, 53 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
43 { "pca9555", 16 | PCA953X_INT, }, 54 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
44 { "pca9556", 8, }, 55 { "pca9556", 8 | PCA953X_TYPE, },
45 { "pca9557", 8, }, 56 { "pca9557", 8 | PCA953X_TYPE, },
46 57 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
47 { "max7310", 8, }, 58 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
48 { "max7312", 16 | PCA953X_INT, }, 59
49 { "max7313", 16 | PCA953X_INT, }, 60 { "max7310", 8 | PCA953X_TYPE, },
50 { "max7315", 8 | PCA953X_INT, }, 61 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
51 { "pca6107", 8 | PCA953X_INT, }, 62 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
52 { "tca6408", 8 | PCA953X_INT, }, 63 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
53 { "tca6416", 16 | PCA953X_INT, }, 64 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
65 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
66 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
54 /* NYET: { "tca6424", 24, }, */ 67 /* NYET: { "tca6424", 24, }, */
55 { } 68 { }
56}; 69};
@@ -60,6 +73,7 @@ struct pca953x_chip {
60 unsigned gpio_start; 73 unsigned gpio_start;
61 uint16_t reg_output; 74 uint16_t reg_output;
62 uint16_t reg_direction; 75 uint16_t reg_direction;
76 struct mutex i2c_lock;
63 77
64#ifdef CONFIG_GPIO_PCA953X_IRQ 78#ifdef CONFIG_GPIO_PCA953X_IRQ
65 struct mutex irq_lock; 79 struct mutex irq_lock;
@@ -74,16 +88,32 @@ struct pca953x_chip {
74 struct pca953x_platform_data *dyn_pdata; 88 struct pca953x_platform_data *dyn_pdata;
75 struct gpio_chip gpio_chip; 89 struct gpio_chip gpio_chip;
76 const char *const *names; 90 const char *const *names;
91 int chip_type;
77}; 92};
78 93
79static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val) 94static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val)
80{ 95{
81 int ret; 96 int ret = 0;
82 97
83 if (chip->gpio_chip.ngpio <= 8) 98 if (chip->gpio_chip.ngpio <= 8)
84 ret = i2c_smbus_write_byte_data(chip->client, reg, val); 99 ret = i2c_smbus_write_byte_data(chip->client, reg, val);
85 else 100 else {
86 ret = i2c_smbus_write_word_data(chip->client, reg << 1, val); 101 switch (chip->chip_type) {
102 case PCA953X_TYPE:
103 ret = i2c_smbus_write_word_data(chip->client,
104 reg << 1, val);
105 break;
106 case PCA957X_TYPE:
107 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
108 val & 0xff);
109 if (ret < 0)
110 break;
111 ret = i2c_smbus_write_byte_data(chip->client,
112 (reg << 1) + 1,
113 (val & 0xff00) >> 8);
114 break;
115 }
116 }
87 117
88 if (ret < 0) { 118 if (ret < 0) {
89 dev_err(&chip->client->dev, "failed writing register\n"); 119 dev_err(&chip->client->dev, "failed writing register\n");
@@ -115,17 +145,30 @@ static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
115{ 145{
116 struct pca953x_chip *chip; 146 struct pca953x_chip *chip;
117 uint16_t reg_val; 147 uint16_t reg_val;
118 int ret; 148 int ret, offset = 0;
119 149
120 chip = container_of(gc, struct pca953x_chip, gpio_chip); 150 chip = container_of(gc, struct pca953x_chip, gpio_chip);
121 151
152 mutex_lock(&chip->i2c_lock);
122 reg_val = chip->reg_direction | (1u << off); 153 reg_val = chip->reg_direction | (1u << off);
123 ret = pca953x_write_reg(chip, PCA953X_DIRECTION, reg_val); 154
155 switch (chip->chip_type) {
156 case PCA953X_TYPE:
157 offset = PCA953X_DIRECTION;
158 break;
159 case PCA957X_TYPE:
160 offset = PCA957X_CFG;
161 break;
162 }
163 ret = pca953x_write_reg(chip, offset, reg_val);
124 if (ret) 164 if (ret)
125 return ret; 165 goto exit;
126 166
127 chip->reg_direction = reg_val; 167 chip->reg_direction = reg_val;
128 return 0; 168 ret = 0;
169exit:
170 mutex_unlock(&chip->i2c_lock);
171 return ret;
129} 172}
130 173
131static int pca953x_gpio_direction_output(struct gpio_chip *gc, 174static int pca953x_gpio_direction_output(struct gpio_chip *gc,
@@ -133,41 +176,71 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
133{ 176{
134 struct pca953x_chip *chip; 177 struct pca953x_chip *chip;
135 uint16_t reg_val; 178 uint16_t reg_val;
136 int ret; 179 int ret, offset = 0;
137 180
138 chip = container_of(gc, struct pca953x_chip, gpio_chip); 181 chip = container_of(gc, struct pca953x_chip, gpio_chip);
139 182
183 mutex_lock(&chip->i2c_lock);
140 /* set output level */ 184 /* set output level */
141 if (val) 185 if (val)
142 reg_val = chip->reg_output | (1u << off); 186 reg_val = chip->reg_output | (1u << off);
143 else 187 else
144 reg_val = chip->reg_output & ~(1u << off); 188 reg_val = chip->reg_output & ~(1u << off);
145 189
146 ret = pca953x_write_reg(chip, PCA953X_OUTPUT, reg_val); 190 switch (chip->chip_type) {
191 case PCA953X_TYPE:
192 offset = PCA953X_OUTPUT;
193 break;
194 case PCA957X_TYPE:
195 offset = PCA957X_OUT;
196 break;
197 }
198 ret = pca953x_write_reg(chip, offset, reg_val);
147 if (ret) 199 if (ret)
148 return ret; 200 goto exit;
149 201
150 chip->reg_output = reg_val; 202 chip->reg_output = reg_val;
151 203
152 /* then direction */ 204 /* then direction */
153 reg_val = chip->reg_direction & ~(1u << off); 205 reg_val = chip->reg_direction & ~(1u << off);
154 ret = pca953x_write_reg(chip, PCA953X_DIRECTION, reg_val); 206 switch (chip->chip_type) {
207 case PCA953X_TYPE:
208 offset = PCA953X_DIRECTION;
209 break;
210 case PCA957X_TYPE:
211 offset = PCA957X_CFG;
212 break;
213 }
214 ret = pca953x_write_reg(chip, offset, reg_val);
155 if (ret) 215 if (ret)
156 return ret; 216 goto exit;
157 217
158 chip->reg_direction = reg_val; 218 chip->reg_direction = reg_val;
159 return 0; 219 ret = 0;
220exit:
221 mutex_unlock(&chip->i2c_lock);
222 return ret;
160} 223}
161 224
162static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 225static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
163{ 226{
164 struct pca953x_chip *chip; 227 struct pca953x_chip *chip;
165 uint16_t reg_val; 228 uint16_t reg_val;
166 int ret; 229 int ret, offset = 0;
167 230
168 chip = container_of(gc, struct pca953x_chip, gpio_chip); 231 chip = container_of(gc, struct pca953x_chip, gpio_chip);
169 232
170 ret = pca953x_read_reg(chip, PCA953X_INPUT, &reg_val); 233 mutex_lock(&chip->i2c_lock);
234 switch (chip->chip_type) {
235 case PCA953X_TYPE:
236 offset = PCA953X_INPUT;
237 break;
238 case PCA957X_TYPE:
239 offset = PCA957X_IN;
240 break;
241 }
242 ret = pca953x_read_reg(chip, offset, &reg_val);
243 mutex_unlock(&chip->i2c_lock);
171 if (ret < 0) { 244 if (ret < 0) {
172 /* NOTE: diagnostic already emitted; that's all we should 245 /* NOTE: diagnostic already emitted; that's all we should
173 * do unless gpio_*_value_cansleep() calls become different 246 * do unless gpio_*_value_cansleep() calls become different
@@ -183,20 +256,31 @@ static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
183{ 256{
184 struct pca953x_chip *chip; 257 struct pca953x_chip *chip;
185 uint16_t reg_val; 258 uint16_t reg_val;
186 int ret; 259 int ret, offset = 0;
187 260
188 chip = container_of(gc, struct pca953x_chip, gpio_chip); 261 chip = container_of(gc, struct pca953x_chip, gpio_chip);
189 262
263 mutex_lock(&chip->i2c_lock);
190 if (val) 264 if (val)
191 reg_val = chip->reg_output | (1u << off); 265 reg_val = chip->reg_output | (1u << off);
192 else 266 else
193 reg_val = chip->reg_output & ~(1u << off); 267 reg_val = chip->reg_output & ~(1u << off);
194 268
195 ret = pca953x_write_reg(chip, PCA953X_OUTPUT, reg_val); 269 switch (chip->chip_type) {
270 case PCA953X_TYPE:
271 offset = PCA953X_OUTPUT;
272 break;
273 case PCA957X_TYPE:
274 offset = PCA957X_OUT;
275 break;
276 }
277 ret = pca953x_write_reg(chip, offset, reg_val);
196 if (ret) 278 if (ret)
197 return; 279 goto exit;
198 280
199 chip->reg_output = reg_val; 281 chip->reg_output = reg_val;
282exit:
283 mutex_unlock(&chip->i2c_lock);
200} 284}
201 285
202static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 286static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
@@ -228,30 +312,30 @@ static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
228 return chip->irq_base + off; 312 return chip->irq_base + off;
229} 313}
230 314
231static void pca953x_irq_mask(unsigned int irq) 315static void pca953x_irq_mask(struct irq_data *d)
232{ 316{
233 struct pca953x_chip *chip = get_irq_chip_data(irq); 317 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
234 318
235 chip->irq_mask &= ~(1 << (irq - chip->irq_base)); 319 chip->irq_mask &= ~(1 << (d->irq - chip->irq_base));
236} 320}
237 321
238static void pca953x_irq_unmask(unsigned int irq) 322static void pca953x_irq_unmask(struct irq_data *d)
239{ 323{
240 struct pca953x_chip *chip = get_irq_chip_data(irq); 324 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
241 325
242 chip->irq_mask |= 1 << (irq - chip->irq_base); 326 chip->irq_mask |= 1 << (d->irq - chip->irq_base);
243} 327}
244 328
245static void pca953x_irq_bus_lock(unsigned int irq) 329static void pca953x_irq_bus_lock(struct irq_data *d)
246{ 330{
247 struct pca953x_chip *chip = get_irq_chip_data(irq); 331 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
248 332
249 mutex_lock(&chip->irq_lock); 333 mutex_lock(&chip->irq_lock);
250} 334}
251 335
252static void pca953x_irq_bus_sync_unlock(unsigned int irq) 336static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
253{ 337{
254 struct pca953x_chip *chip = get_irq_chip_data(irq); 338 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
255 uint16_t new_irqs; 339 uint16_t new_irqs;
256 uint16_t level; 340 uint16_t level;
257 341
@@ -268,15 +352,15 @@ static void pca953x_irq_bus_sync_unlock(unsigned int irq)
268 mutex_unlock(&chip->irq_lock); 352 mutex_unlock(&chip->irq_lock);
269} 353}
270 354
271static int pca953x_irq_set_type(unsigned int irq, unsigned int type) 355static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
272{ 356{
273 struct pca953x_chip *chip = get_irq_chip_data(irq); 357 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
274 uint16_t level = irq - chip->irq_base; 358 uint16_t level = d->irq - chip->irq_base;
275 uint16_t mask = 1 << level; 359 uint16_t mask = 1 << level;
276 360
277 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 361 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
278 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 362 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
279 irq, type); 363 d->irq, type);
280 return -EINVAL; 364 return -EINVAL;
281 } 365 }
282 366
@@ -295,11 +379,11 @@ static int pca953x_irq_set_type(unsigned int irq, unsigned int type)
295 379
296static struct irq_chip pca953x_irq_chip = { 380static struct irq_chip pca953x_irq_chip = {
297 .name = "pca953x", 381 .name = "pca953x",
298 .mask = pca953x_irq_mask, 382 .irq_mask = pca953x_irq_mask,
299 .unmask = pca953x_irq_unmask, 383 .irq_unmask = pca953x_irq_unmask,
300 .bus_lock = pca953x_irq_bus_lock, 384 .irq_bus_lock = pca953x_irq_bus_lock,
301 .bus_sync_unlock = pca953x_irq_bus_sync_unlock, 385 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
302 .set_type = pca953x_irq_set_type, 386 .irq_set_type = pca953x_irq_set_type,
303}; 387};
304 388
305static uint16_t pca953x_irq_pending(struct pca953x_chip *chip) 389static uint16_t pca953x_irq_pending(struct pca953x_chip *chip)
@@ -308,9 +392,17 @@ static uint16_t pca953x_irq_pending(struct pca953x_chip *chip)
308 uint16_t old_stat; 392 uint16_t old_stat;
309 uint16_t pending; 393 uint16_t pending;
310 uint16_t trigger; 394 uint16_t trigger;
311 int ret; 395 int ret, offset = 0;
312 396
313 ret = pca953x_read_reg(chip, PCA953X_INPUT, &cur_stat); 397 switch (chip->chip_type) {
398 case PCA953X_TYPE:
399 offset = PCA953X_INPUT;
400 break;
401 case PCA957X_TYPE:
402 offset = PCA957X_IN;
403 break;
404 }
405 ret = pca953x_read_reg(chip, offset, &cur_stat);
314 if (ret) 406 if (ret)
315 return 0; 407 return 0;
316 408
@@ -345,7 +437,7 @@ static irqreturn_t pca953x_irq_handler(int irq, void *devid)
345 437
346 do { 438 do {
347 level = __ffs(pending); 439 level = __ffs(pending);
348 handle_nested_irq(level + chip->irq_base); 440 generic_handle_irq(level + chip->irq_base);
349 441
350 pending &= ~(1 << level); 442 pending &= ~(1 << level);
351 } while (pending); 443 } while (pending);
@@ -358,13 +450,21 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
358{ 450{
359 struct i2c_client *client = chip->client; 451 struct i2c_client *client = chip->client;
360 struct pca953x_platform_data *pdata = client->dev.platform_data; 452 struct pca953x_platform_data *pdata = client->dev.platform_data;
361 int ret; 453 int ret, offset = 0;
362 454
363 if (pdata->irq_base && (id->driver_data & PCA953X_INT)) { 455 if (pdata->irq_base != -1
456 && (id->driver_data & PCA_INT)) {
364 int lvl; 457 int lvl;
365 458
366 ret = pca953x_read_reg(chip, PCA953X_INPUT, 459 switch (chip->chip_type) {
367 &chip->irq_stat); 460 case PCA953X_TYPE:
461 offset = PCA953X_INPUT;
462 break;
463 case PCA957X_TYPE:
464 offset = PCA957X_IN;
465 break;
466 }
467 ret = pca953x_read_reg(chip, offset, &chip->irq_stat);
368 if (ret) 468 if (ret)
369 goto out_failed; 469 goto out_failed;
370 470
@@ -380,20 +480,20 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
380 for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { 480 for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) {
381 int irq = lvl + chip->irq_base; 481 int irq = lvl + chip->irq_base;
382 482
383 set_irq_chip_data(irq, chip); 483 irq_set_chip_data(irq, chip);
384 set_irq_chip_and_handler(irq, &pca953x_irq_chip, 484 irq_set_chip_and_handler(irq, &pca953x_irq_chip,
385 handle_edge_irq); 485 handle_simple_irq);
386 set_irq_nested_thread(irq, 1);
387#ifdef CONFIG_ARM 486#ifdef CONFIG_ARM
388 set_irq_flags(irq, IRQF_VALID); 487 set_irq_flags(irq, IRQF_VALID);
389#else 488#else
390 set_irq_noprobe(irq); 489 irq_set_noprobe(irq);
391#endif 490#endif
392 } 491 }
393 492
394 ret = request_threaded_irq(client->irq, 493 ret = request_threaded_irq(client->irq,
395 NULL, 494 NULL,
396 pca953x_irq_handler, 495 pca953x_irq_handler,
496 IRQF_TRIGGER_RISING |
397 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 497 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
398 dev_name(&client->dev), chip); 498 dev_name(&client->dev), chip);
399 if (ret) { 499 if (ret) {
@@ -408,13 +508,13 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
408 return 0; 508 return 0;
409 509
410out_failed: 510out_failed:
411 chip->irq_base = 0; 511 chip->irq_base = -1;
412 return ret; 512 return ret;
413} 513}
414 514
415static void pca953x_irq_teardown(struct pca953x_chip *chip) 515static void pca953x_irq_teardown(struct pca953x_chip *chip)
416{ 516{
417 if (chip->irq_base) 517 if (chip->irq_base != -1)
418 free_irq(chip->client->irq, chip); 518 free_irq(chip->client->irq, chip);
419} 519}
420#else /* CONFIG_GPIO_PCA953X_IRQ */ 520#else /* CONFIG_GPIO_PCA953X_IRQ */
@@ -424,7 +524,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
424 struct i2c_client *client = chip->client; 524 struct i2c_client *client = chip->client;
425 struct pca953x_platform_data *pdata = client->dev.platform_data; 525 struct pca953x_platform_data *pdata = client->dev.platform_data;
426 526
427 if (pdata->irq_base && (id->driver_data & PCA953X_INT)) 527 if (pdata->irq_base != -1 && (id->driver_data & PCA_INT))
428 dev_warn(&client->dev, "interrupt support not compiled in\n"); 528 dev_warn(&client->dev, "interrupt support not compiled in\n");
429 529
430 return 0; 530 return 0;
@@ -447,7 +547,8 @@ pca953x_get_alt_pdata(struct i2c_client *client)
447{ 547{
448 struct pca953x_platform_data *pdata; 548 struct pca953x_platform_data *pdata;
449 struct device_node *node; 549 struct device_node *node;
450 const uint16_t *val; 550 const __be32 *val;
551 int size;
451 552
452 node = client->dev.of_node; 553 node = client->dev.of_node;
453 if (node == NULL) 554 if (node == NULL)
@@ -460,13 +561,13 @@ pca953x_get_alt_pdata(struct i2c_client *client)
460 } 561 }
461 562
462 pdata->gpio_base = -1; 563 pdata->gpio_base = -1;
463 val = of_get_property(node, "linux,gpio-base", NULL); 564 val = of_get_property(node, "linux,gpio-base", &size);
464 if (val) { 565 if (val) {
465 if (*val < 0) 566 if (size != sizeof(*val))
466 dev_warn(&client->dev, 567 dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
467 "invalid gpio-base in device tree\n"); 568 node->full_name);
468 else 569 else
469 pdata->gpio_base = *val; 570 pdata->gpio_base = be32_to_cpup(val);
470 } 571 }
471 572
472 val = of_get_property(node, "polarity", NULL); 573 val = of_get_property(node, "polarity", NULL);
@@ -483,12 +584,65 @@ pca953x_get_alt_pdata(struct i2c_client *client)
483} 584}
484#endif 585#endif
485 586
587static int __devinit device_pca953x_init(struct pca953x_chip *chip, int invert)
588{
589 int ret;
590
591 ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output);
592 if (ret)
593 goto out;
594
595 ret = pca953x_read_reg(chip, PCA953X_DIRECTION,
596 &chip->reg_direction);
597 if (ret)
598 goto out;
599
600 /* set platform specific polarity inversion */
601 ret = pca953x_write_reg(chip, PCA953X_INVERT, invert);
602 if (ret)
603 goto out;
604 return 0;
605out:
606 return ret;
607}
608
609static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert)
610{
611 int ret;
612 uint16_t val = 0;
613
614 /* Let every port in proper state, that could save power */
615 pca953x_write_reg(chip, PCA957X_PUPD, 0x0);
616 pca953x_write_reg(chip, PCA957X_CFG, 0xffff);
617 pca953x_write_reg(chip, PCA957X_OUT, 0x0);
618
619 ret = pca953x_read_reg(chip, PCA957X_IN, &val);
620 if (ret)
621 goto out;
622 ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output);
623 if (ret)
624 goto out;
625 ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction);
626 if (ret)
627 goto out;
628
629 /* set platform specific polarity inversion */
630 pca953x_write_reg(chip, PCA957X_INVRT, invert);
631
632 /* To enable register 6, 7 to controll pull up and pull down */
633 pca953x_write_reg(chip, PCA957X_BKEN, 0x202);
634
635 return 0;
636out:
637 return ret;
638}
639
486static int __devinit pca953x_probe(struct i2c_client *client, 640static int __devinit pca953x_probe(struct i2c_client *client,
487 const struct i2c_device_id *id) 641 const struct i2c_device_id *id)
488{ 642{
489 struct pca953x_platform_data *pdata; 643 struct pca953x_platform_data *pdata;
490 struct pca953x_chip *chip; 644 struct pca953x_chip *chip;
491 int ret; 645 int ret = 0;
492 646
493 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL); 647 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL);
494 if (chip == NULL) 648 if (chip == NULL)
@@ -515,23 +669,20 @@ static int __devinit pca953x_probe(struct i2c_client *client,
515 chip->gpio_start = pdata->gpio_base; 669 chip->gpio_start = pdata->gpio_base;
516 670
517 chip->names = pdata->names; 671 chip->names = pdata->names;
672 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
673
674 mutex_init(&chip->i2c_lock);
518 675
519 /* initialize cached registers from their original values. 676 /* initialize cached registers from their original values.
520 * we can't share this chip with another i2c master. 677 * we can't share this chip with another i2c master.
521 */ 678 */
522 pca953x_setup_gpio(chip, id->driver_data & PCA953X_GPIOS); 679 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
523
524 ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output);
525 if (ret)
526 goto out_failed;
527 680
528 ret = pca953x_read_reg(chip, PCA953X_DIRECTION, &chip->reg_direction); 681 if (chip->chip_type == PCA953X_TYPE)
529 if (ret) 682 device_pca953x_init(chip, pdata->invert);
530 goto out_failed; 683 else if (chip->chip_type == PCA957X_TYPE)
531 684 device_pca957x_init(chip, pdata->invert);
532 /* set platform specific polarity inversion */ 685 else
533 ret = pca953x_write_reg(chip, PCA953X_INVERT, pdata->invert);
534 if (ret)
535 goto out_failed; 686 goto out_failed;
536 687
537 ret = pca953x_irq_setup(chip, id); 688 ret = pca953x_irq_setup(chip, id);
@@ -540,7 +691,7 @@ static int __devinit pca953x_probe(struct i2c_client *client,
540 691
541 ret = gpiochip_add(&chip->gpio_chip); 692 ret = gpiochip_add(&chip->gpio_chip);
542 if (ret) 693 if (ret)
543 goto out_failed; 694 goto out_failed_irq;
544 695
545 if (pdata->setup) { 696 if (pdata->setup) {
546 ret = pdata->setup(client, chip->gpio_chip.base, 697 ret = pdata->setup(client, chip->gpio_chip.base,
@@ -552,8 +703,9 @@ static int __devinit pca953x_probe(struct i2c_client *client,
552 i2c_set_clientdata(client, chip); 703 i2c_set_clientdata(client, chip);
553 return 0; 704 return 0;
554 705
555out_failed: 706out_failed_irq:
556 pca953x_irq_teardown(chip); 707 pca953x_irq_teardown(chip);
708out_failed:
557 kfree(chip->dyn_pdata); 709 kfree(chip->dyn_pdata);
558 kfree(chip); 710 kfree(chip);
559 return ret; 711 return ret;
diff --git a/drivers/gpio/pch_gpio.c b/drivers/gpio/pch_gpio.c
new file mode 100644
index 000000000000..36919e77c495
--- /dev/null
+++ b/drivers/gpio/pch_gpio.c
@@ -0,0 +1,316 @@
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/gpio.h>
20
21#define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */
22#define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */
23
24struct pch_regs {
25 u32 ien;
26 u32 istatus;
27 u32 idisp;
28 u32 iclr;
29 u32 imask;
30 u32 imaskclr;
31 u32 po;
32 u32 pi;
33 u32 pm;
34 u32 im0;
35 u32 im1;
36 u32 reserved[4];
37 u32 reset;
38};
39
40/**
41 * struct pch_gpio_reg_data - The register store data.
42 * @po_reg: To store contents of PO register.
43 * @pm_reg: To store contents of PM register.
44 */
45struct pch_gpio_reg_data {
46 u32 po_reg;
47 u32 pm_reg;
48};
49
50/**
51 * struct pch_gpio - GPIO private data structure.
52 * @base: PCI base address of Memory mapped I/O register.
53 * @reg: Memory mapped PCH GPIO register list.
54 * @dev: Pointer to device structure.
55 * @gpio: Data for GPIO infrastructure.
56 * @pch_gpio_reg: Memory mapped Register data is saved here
57 * when suspend.
58 */
59struct pch_gpio {
60 void __iomem *base;
61 struct pch_regs __iomem *reg;
62 struct device *dev;
63 struct gpio_chip gpio;
64 struct pch_gpio_reg_data pch_gpio_reg;
65 struct mutex lock;
66};
67
68static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
69{
70 u32 reg_val;
71 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
72
73 mutex_lock(&chip->lock);
74 reg_val = ioread32(&chip->reg->po);
75 if (val)
76 reg_val |= (1 << nr);
77 else
78 reg_val &= ~(1 << nr);
79
80 iowrite32(reg_val, &chip->reg->po);
81 mutex_unlock(&chip->lock);
82}
83
84static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
85{
86 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
87
88 return ioread32(&chip->reg->pi) & (1 << nr);
89}
90
91static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
92 int val)
93{
94 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
95 u32 pm;
96 u32 reg_val;
97
98 mutex_lock(&chip->lock);
99 pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
100 pm |= (1 << nr);
101 iowrite32(pm, &chip->reg->pm);
102
103 reg_val = ioread32(&chip->reg->po);
104 if (val)
105 reg_val |= (1 << nr);
106 else
107 reg_val &= ~(1 << nr);
108 iowrite32(reg_val, &chip->reg->po);
109
110 mutex_unlock(&chip->lock);
111
112 return 0;
113}
114
115static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
116{
117 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
118 u32 pm;
119
120 mutex_lock(&chip->lock);
121 pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
122 pm &= ~(1 << nr);
123 iowrite32(pm, &chip->reg->pm);
124 mutex_unlock(&chip->lock);
125
126 return 0;
127}
128
129/*
130 * Save register configuration and disable interrupts.
131 */
132static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
133{
134 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
135 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
136}
137
138/*
139 * This function restores the register configuration of the GPIO device.
140 */
141static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
142{
143 /* to store contents of PO register */
144 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
145 /* to store contents of PM register */
146 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
147}
148
149static void pch_gpio_setup(struct pch_gpio *chip)
150{
151 struct gpio_chip *gpio = &chip->gpio;
152
153 gpio->label = dev_name(chip->dev);
154 gpio->owner = THIS_MODULE;
155 gpio->direction_input = pch_gpio_direction_input;
156 gpio->get = pch_gpio_get;
157 gpio->direction_output = pch_gpio_direction_output;
158 gpio->set = pch_gpio_set;
159 gpio->dbg_show = NULL;
160 gpio->base = -1;
161 gpio->ngpio = GPIO_NUM_PINS;
162 gpio->can_sleep = 0;
163}
164
165static int __devinit pch_gpio_probe(struct pci_dev *pdev,
166 const struct pci_device_id *id)
167{
168 s32 ret;
169 struct pch_gpio *chip;
170
171 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
172 if (chip == NULL)
173 return -ENOMEM;
174
175 chip->dev = &pdev->dev;
176 ret = pci_enable_device(pdev);
177 if (ret) {
178 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
179 goto err_pci_enable;
180 }
181
182 ret = pci_request_regions(pdev, KBUILD_MODNAME);
183 if (ret) {
184 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
185 goto err_request_regions;
186 }
187
188 chip->base = pci_iomap(pdev, 1, 0);
189 if (chip->base == 0) {
190 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
191 ret = -ENOMEM;
192 goto err_iomap;
193 }
194
195 chip->reg = chip->base;
196 pci_set_drvdata(pdev, chip);
197 mutex_init(&chip->lock);
198 pch_gpio_setup(chip);
199 ret = gpiochip_add(&chip->gpio);
200 if (ret) {
201 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
202 goto err_gpiochip_add;
203 }
204
205 return 0;
206
207err_gpiochip_add:
208 pci_iounmap(pdev, chip->base);
209
210err_iomap:
211 pci_release_regions(pdev);
212
213err_request_regions:
214 pci_disable_device(pdev);
215
216err_pci_enable:
217 kfree(chip);
218 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
219 return ret;
220}
221
222static void __devexit pch_gpio_remove(struct pci_dev *pdev)
223{
224 int err;
225 struct pch_gpio *chip = pci_get_drvdata(pdev);
226
227 err = gpiochip_remove(&chip->gpio);
228 if (err)
229 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
230
231 pci_iounmap(pdev, chip->base);
232 pci_release_regions(pdev);
233 pci_disable_device(pdev);
234 kfree(chip);
235}
236
237#ifdef CONFIG_PM
238static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
239{
240 s32 ret;
241 struct pch_gpio *chip = pci_get_drvdata(pdev);
242
243 pch_gpio_save_reg_conf(chip);
244 pch_gpio_restore_reg_conf(chip);
245
246 ret = pci_save_state(pdev);
247 if (ret) {
248 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
249 return ret;
250 }
251 pci_disable_device(pdev);
252 pci_set_power_state(pdev, PCI_D0);
253 ret = pci_enable_wake(pdev, PCI_D0, 1);
254 if (ret)
255 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
256
257 return 0;
258}
259
260static int pch_gpio_resume(struct pci_dev *pdev)
261{
262 s32 ret;
263 struct pch_gpio *chip = pci_get_drvdata(pdev);
264
265 ret = pci_enable_wake(pdev, PCI_D0, 0);
266
267 pci_set_power_state(pdev, PCI_D0);
268 ret = pci_enable_device(pdev);
269 if (ret) {
270 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
271 return ret;
272 }
273 pci_restore_state(pdev);
274
275 iowrite32(0x01, &chip->reg->reset);
276 iowrite32(0x00, &chip->reg->reset);
277 pch_gpio_restore_reg_conf(chip);
278
279 return 0;
280}
281#else
282#define pch_gpio_suspend NULL
283#define pch_gpio_resume NULL
284#endif
285
286#define PCI_VENDOR_ID_ROHM 0x10DB
287static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
288 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
289 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
290 { 0, }
291};
292MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
293
294static struct pci_driver pch_gpio_driver = {
295 .name = "pch_gpio",
296 .id_table = pch_gpio_pcidev_id,
297 .probe = pch_gpio_probe,
298 .remove = __devexit_p(pch_gpio_remove),
299 .suspend = pch_gpio_suspend,
300 .resume = pch_gpio_resume
301};
302
303static int __init pch_gpio_pci_init(void)
304{
305 return pci_register_driver(&pch_gpio_driver);
306}
307module_init(pch_gpio_pci_init);
308
309static void __exit pch_gpio_pci_exit(void)
310{
311 pci_unregister_driver(&pch_gpio_driver);
312}
313module_exit(pch_gpio_pci_exit);
314
315MODULE_DESCRIPTION("PCH GPIO PCI Driver");
316MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 5005990f751f..6fcb28cdd862 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -129,10 +129,10 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
129/* 129/*
130 * PL061 GPIO IRQ 130 * PL061 GPIO IRQ
131 */ 131 */
132static void pl061_irq_disable(unsigned irq) 132static void pl061_irq_disable(struct irq_data *d)
133{ 133{
134 struct pl061_gpio *chip = get_irq_chip_data(irq); 134 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
135 int offset = irq - chip->irq_base; 135 int offset = d->irq - chip->irq_base;
136 unsigned long flags; 136 unsigned long flags;
137 u8 gpioie; 137 u8 gpioie;
138 138
@@ -143,10 +143,10 @@ static void pl061_irq_disable(unsigned irq)
143 spin_unlock_irqrestore(&chip->irq_lock, flags); 143 spin_unlock_irqrestore(&chip->irq_lock, flags);
144} 144}
145 145
146static void pl061_irq_enable(unsigned irq) 146static void pl061_irq_enable(struct irq_data *d)
147{ 147{
148 struct pl061_gpio *chip = get_irq_chip_data(irq); 148 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
149 int offset = irq - chip->irq_base; 149 int offset = d->irq - chip->irq_base;
150 unsigned long flags; 150 unsigned long flags;
151 u8 gpioie; 151 u8 gpioie;
152 152
@@ -157,10 +157,10 @@ static void pl061_irq_enable(unsigned irq)
157 spin_unlock_irqrestore(&chip->irq_lock, flags); 157 spin_unlock_irqrestore(&chip->irq_lock, flags);
158} 158}
159 159
160static int pl061_irq_type(unsigned irq, unsigned trigger) 160static int pl061_irq_type(struct irq_data *d, unsigned trigger)
161{ 161{
162 struct pl061_gpio *chip = get_irq_chip_data(irq); 162 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
163 int offset = irq - chip->irq_base; 163 int offset = d->irq - chip->irq_base;
164 unsigned long flags; 164 unsigned long flags;
165 u8 gpiois, gpioibe, gpioiev; 165 u8 gpiois, gpioibe, gpioiev;
166 166
@@ -203,18 +203,18 @@ static int pl061_irq_type(unsigned irq, unsigned trigger)
203 203
204static struct irq_chip pl061_irqchip = { 204static struct irq_chip pl061_irqchip = {
205 .name = "GPIO", 205 .name = "GPIO",
206 .enable = pl061_irq_enable, 206 .irq_enable = pl061_irq_enable,
207 .disable = pl061_irq_disable, 207 .irq_disable = pl061_irq_disable,
208 .set_type = pl061_irq_type, 208 .irq_set_type = pl061_irq_type,
209}; 209};
210 210
211static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) 211static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
212{ 212{
213 struct list_head *chip_list = get_irq_data(irq); 213 struct list_head *chip_list = irq_get_handler_data(irq);
214 struct list_head *ptr; 214 struct list_head *ptr;
215 struct pl061_gpio *chip; 215 struct pl061_gpio *chip;
216 216
217 desc->chip->ack(irq); 217 desc->irq_data.chip->irq_ack(&desc->irq_data);
218 list_for_each(ptr, chip_list) { 218 list_for_each(ptr, chip_list) {
219 unsigned long pending; 219 unsigned long pending;
220 int offset; 220 int offset;
@@ -229,10 +229,10 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
229 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 229 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
230 generic_handle_irq(pl061_to_irq(&chip->gc, offset)); 230 generic_handle_irq(pl061_to_irq(&chip->gc, offset));
231 } 231 }
232 desc->chip->unmask(irq); 232 desc->irq_data.chip->irq_unmask(&desc->irq_data);
233} 233}
234 234
235static int pl061_probe(struct amba_device *dev, struct amba_id *id) 235static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
236{ 236{
237 struct pl061_platform_data *pdata; 237 struct pl061_platform_data *pdata;
238 struct pl061_gpio *chip; 238 struct pl061_gpio *chip;
@@ -294,7 +294,7 @@ static int pl061_probe(struct amba_device *dev, struct amba_id *id)
294 ret = -ENODEV; 294 ret = -ENODEV;
295 goto iounmap; 295 goto iounmap;
296 } 296 }
297 set_irq_chained_handler(irq, pl061_irq_handler); 297 irq_set_chained_handler(irq, pl061_irq_handler);
298 if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */ 298 if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
299 chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL); 299 chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
300 if (chip_list == NULL) { 300 if (chip_list == NULL) {
@@ -303,9 +303,9 @@ static int pl061_probe(struct amba_device *dev, struct amba_id *id)
303 goto iounmap; 303 goto iounmap;
304 } 304 }
305 INIT_LIST_HEAD(chip_list); 305 INIT_LIST_HEAD(chip_list);
306 set_irq_data(irq, chip_list); 306 irq_set_handler_data(irq, chip_list);
307 } else 307 } else
308 chip_list = get_irq_data(irq); 308 chip_list = irq_get_handler_data(irq);
309 list_add(&chip->list, chip_list); 309 list_add(&chip->list, chip_list);
310 310
311 for (i = 0; i < PL061_GPIO_NR; i++) { 311 for (i = 0; i < PL061_GPIO_NR; i++) {
@@ -315,10 +315,10 @@ static int pl061_probe(struct amba_device *dev, struct amba_id *id)
315 else 315 else
316 pl061_direction_input(&chip->gc, i); 316 pl061_direction_input(&chip->gc, i);
317 317
318 set_irq_chip(i+chip->irq_base, &pl061_irqchip); 318 irq_set_chip_and_handler(i + chip->irq_base, &pl061_irqchip,
319 set_irq_handler(i+chip->irq_base, handle_simple_irq); 319 handle_simple_irq);
320 set_irq_flags(i+chip->irq_base, IRQF_VALID); 320 set_irq_flags(i+chip->irq_base, IRQF_VALID);
321 set_irq_chip_data(i+chip->irq_base, chip); 321 irq_set_chip_data(i + chip->irq_base, chip);
322 } 322 }
323 323
324 return 0; 324 return 0;
diff --git a/drivers/gpio/sch_gpio.c b/drivers/gpio/sch_gpio.c
index 583521352c16..56060421cdff 100644
--- a/drivers/gpio/sch_gpio.c
+++ b/drivers/gpio/sch_gpio.c
@@ -25,6 +25,7 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/acpi.h> 26#include <linux/acpi.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/pci_ids.h>
28 29
29#include <linux/gpio.h> 30#include <linux/gpio.h>
30 31
@@ -187,7 +188,11 @@ static struct gpio_chip sch_gpio_resume = {
187static int __devinit sch_gpio_probe(struct platform_device *pdev) 188static int __devinit sch_gpio_probe(struct platform_device *pdev)
188{ 189{
189 struct resource *res; 190 struct resource *res;
190 int err; 191 int err, id;
192
193 id = pdev->id;
194 if (!id)
195 return -ENODEV;
191 196
192 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 197 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
193 if (!res) 198 if (!res)
@@ -198,12 +203,40 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
198 203
199 gpio_ba = res->start; 204 gpio_ba = res->start;
200 205
201 sch_gpio_core.base = 0; 206 switch (id) {
202 sch_gpio_core.ngpio = 10; 207 case PCI_DEVICE_ID_INTEL_SCH_LPC:
203 sch_gpio_core.dev = &pdev->dev; 208 sch_gpio_core.base = 0;
209 sch_gpio_core.ngpio = 10;
210
211 sch_gpio_resume.base = 10;
212 sch_gpio_resume.ngpio = 4;
213
214 /*
215 * GPIO[6:0] enabled by default
216 * GPIO7 is configured by the CMC as SLPIOVR
217 * Enable GPIO[9:8] core powered gpios explicitly
218 */
219 outb(0x3, gpio_ba + CGEN + 1);
220 /*
221 * SUS_GPIO[2:0] enabled by default
222 * Enable SUS_GPIO3 resume powered gpio explicitly
223 */
224 outb(0x8, gpio_ba + RGEN);
225 break;
226
227 case PCI_DEVICE_ID_INTEL_ITC_LPC:
228 sch_gpio_core.base = 0;
229 sch_gpio_core.ngpio = 5;
230
231 sch_gpio_resume.base = 5;
232 sch_gpio_resume.ngpio = 9;
233 break;
234
235 default:
236 return -ENODEV;
237 }
204 238
205 sch_gpio_resume.base = 10; 239 sch_gpio_core.dev = &pdev->dev;
206 sch_gpio_resume.ngpio = 4;
207 sch_gpio_resume.dev = &pdev->dev; 240 sch_gpio_resume.dev = &pdev->dev;
208 241
209 err = gpiochip_add(&sch_gpio_core); 242 err = gpiochip_add(&sch_gpio_core);
@@ -214,18 +247,6 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
214 if (err < 0) 247 if (err < 0)
215 goto err_sch_gpio_resume; 248 goto err_sch_gpio_resume;
216 249
217 /*
218 * GPIO[6:0] enabled by default
219 * GPIO7 is configured by the CMC as SLPIOVR
220 * Enable GPIO[9:8] core powered gpios explicitly
221 */
222 outb(0x3, gpio_ba + CGEN + 1);
223 /*
224 * SUS_GPIO[2:0] enabled by default
225 * Enable SUS_GPIO3 resume powered gpio explicitly
226 */
227 outb(0x8, gpio_ba + RGEN);
228
229 return 0; 250 return 0;
230 251
231err_sch_gpio_resume: 252err_sch_gpio_resume:
diff --git a/drivers/gpio/stmpe-gpio.c b/drivers/gpio/stmpe-gpio.c
index 4e1f1b9d5e67..4c980b573328 100644
--- a/drivers/gpio/stmpe-gpio.c
+++ b/drivers/gpio/stmpe-gpio.c
@@ -30,6 +30,7 @@ struct stmpe_gpio {
30 struct mutex irq_lock; 30 struct mutex irq_lock;
31 31
32 int irq_base; 32 int irq_base;
33 unsigned norequest_mask;
33 34
34 /* Caches of interrupt control registers for bus_lock */ 35 /* Caches of interrupt control registers for bus_lock */
35 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
@@ -103,6 +104,9 @@ static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
103 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 104 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
104 struct stmpe *stmpe = stmpe_gpio->stmpe; 105 struct stmpe *stmpe = stmpe_gpio->stmpe;
105 106
107 if (stmpe_gpio->norequest_mask & (1 << offset))
108 return -EINVAL;
109
106 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); 110 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
107} 111}
108 112
@@ -118,10 +122,10 @@ static struct gpio_chip template_chip = {
118 .can_sleep = 1, 122 .can_sleep = 1,
119}; 123};
120 124
121static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type) 125static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
122{ 126{
123 struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq); 127 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
124 int offset = irq - stmpe_gpio->irq_base; 128 int offset = d->irq - stmpe_gpio->irq_base;
125 int regoffset = offset / 8; 129 int regoffset = offset / 8;
126 int mask = 1 << (offset % 8); 130 int mask = 1 << (offset % 8);
127 131
@@ -141,16 +145,16 @@ static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type)
141 return 0; 145 return 0;
142} 146}
143 147
144static void stmpe_gpio_irq_lock(unsigned int irq) 148static void stmpe_gpio_irq_lock(struct irq_data *d)
145{ 149{
146 struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq); 150 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
147 151
148 mutex_lock(&stmpe_gpio->irq_lock); 152 mutex_lock(&stmpe_gpio->irq_lock);
149} 153}
150 154
151static void stmpe_gpio_irq_sync_unlock(unsigned int irq) 155static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
152{ 156{
153 struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq); 157 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
154 struct stmpe *stmpe = stmpe_gpio->stmpe; 158 struct stmpe *stmpe = stmpe_gpio->stmpe;
155 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
156 static const u8 regmap[] = { 160 static const u8 regmap[] = {
@@ -176,20 +180,20 @@ static void stmpe_gpio_irq_sync_unlock(unsigned int irq)
176 mutex_unlock(&stmpe_gpio->irq_lock); 180 mutex_unlock(&stmpe_gpio->irq_lock);
177} 181}
178 182
179static void stmpe_gpio_irq_mask(unsigned int irq) 183static void stmpe_gpio_irq_mask(struct irq_data *d)
180{ 184{
181 struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq); 185 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
182 int offset = irq - stmpe_gpio->irq_base; 186 int offset = d->irq - stmpe_gpio->irq_base;
183 int regoffset = offset / 8; 187 int regoffset = offset / 8;
184 int mask = 1 << (offset % 8); 188 int mask = 1 << (offset % 8);
185 189
186 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 190 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
187} 191}
188 192
189static void stmpe_gpio_irq_unmask(unsigned int irq) 193static void stmpe_gpio_irq_unmask(struct irq_data *d)
190{ 194{
191 struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq); 195 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
192 int offset = irq - stmpe_gpio->irq_base; 196 int offset = d->irq - stmpe_gpio->irq_base;
193 int regoffset = offset / 8; 197 int regoffset = offset / 8;
194 int mask = 1 << (offset % 8); 198 int mask = 1 << (offset % 8);
195 199
@@ -198,11 +202,11 @@ static void stmpe_gpio_irq_unmask(unsigned int irq)
198 202
199static struct irq_chip stmpe_gpio_irq_chip = { 203static struct irq_chip stmpe_gpio_irq_chip = {
200 .name = "stmpe-gpio", 204 .name = "stmpe-gpio",
201 .bus_lock = stmpe_gpio_irq_lock, 205 .irq_bus_lock = stmpe_gpio_irq_lock,
202 .bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 206 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
203 .mask = stmpe_gpio_irq_mask, 207 .irq_mask = stmpe_gpio_irq_mask,
204 .unmask = stmpe_gpio_irq_unmask, 208 .irq_unmask = stmpe_gpio_irq_unmask,
205 .set_type = stmpe_gpio_irq_set_type, 209 .irq_set_type = stmpe_gpio_irq_set_type,
206}; 210};
207 211
208static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 212static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
@@ -250,14 +254,14 @@ static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
250 int irq; 254 int irq;
251 255
252 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) { 256 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
253 set_irq_chip_data(irq, stmpe_gpio); 257 irq_set_chip_data(irq, stmpe_gpio);
254 set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip, 258 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
255 handle_simple_irq); 259 handle_simple_irq);
256 set_irq_nested_thread(irq, 1); 260 irq_set_nested_thread(irq, 1);
257#ifdef CONFIG_ARM 261#ifdef CONFIG_ARM
258 set_irq_flags(irq, IRQF_VALID); 262 set_irq_flags(irq, IRQF_VALID);
259#else 263#else
260 set_irq_noprobe(irq); 264 irq_set_noprobe(irq);
261#endif 265#endif
262 } 266 }
263 267
@@ -273,8 +277,8 @@ static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
273#ifdef CONFIG_ARM 277#ifdef CONFIG_ARM
274 set_irq_flags(irq, 0); 278 set_irq_flags(irq, 0);
275#endif 279#endif
276 set_irq_chip_and_handler(irq, NULL, NULL); 280 irq_set_chip_and_handler(irq, NULL, NULL);
277 set_irq_chip_data(irq, NULL); 281 irq_set_chip_data(irq, NULL);
278 } 282 }
279} 283}
280 284
@@ -287,8 +291,6 @@ static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
287 int irq; 291 int irq;
288 292
289 pdata = stmpe->pdata->gpio; 293 pdata = stmpe->pdata->gpio;
290 if (!pdata)
291 return -ENODEV;
292 294
293 irq = platform_get_irq(pdev, 0); 295 irq = platform_get_irq(pdev, 0);
294 if (irq < 0) 296 if (irq < 0)
@@ -302,6 +304,7 @@ static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
302 304
303 stmpe_gpio->dev = &pdev->dev; 305 stmpe_gpio->dev = &pdev->dev;
304 stmpe_gpio->stmpe = stmpe; 306 stmpe_gpio->stmpe = stmpe;
307 stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
305 308
306 stmpe_gpio->chip = template_chip; 309 stmpe_gpio->chip = template_chip;
307 stmpe_gpio->chip.ngpio = stmpe->num_gpios; 310 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
@@ -312,11 +315,11 @@ static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
312 315
313 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 316 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
314 if (ret) 317 if (ret)
315 return ret; 318 goto out_free;
316 319
317 ret = stmpe_gpio_irq_init(stmpe_gpio); 320 ret = stmpe_gpio_irq_init(stmpe_gpio);
318 if (ret) 321 if (ret)
319 goto out_free; 322 goto out_disable;
320 323
321 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT, 324 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
322 "stmpe-gpio", stmpe_gpio); 325 "stmpe-gpio", stmpe_gpio);
@@ -342,6 +345,8 @@ out_freeirq:
342 free_irq(irq, stmpe_gpio); 345 free_irq(irq, stmpe_gpio);
343out_removeirq: 346out_removeirq:
344 stmpe_gpio_irq_remove(stmpe_gpio); 347 stmpe_gpio_irq_remove(stmpe_gpio);
348out_disable:
349 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
345out_free: 350out_free:
346 kfree(stmpe_gpio); 351 kfree(stmpe_gpio);
347 return ret; 352 return ret;
diff --git a/drivers/gpio/sx150x.c b/drivers/gpio/sx150x.c
index 823559ab0e24..a4f73534394e 100644
--- a/drivers/gpio/sx150x.c
+++ b/drivers/gpio/sx150x.c
@@ -25,6 +25,8 @@
25#include <linux/workqueue.h> 25#include <linux/workqueue.h>
26#include <linux/i2c/sx150x.h> 26#include <linux/i2c/sx150x.h>
27 27
28#define NO_UPDATE_PENDING -1
29
28struct sx150x_device_data { 30struct sx150x_device_data {
29 u8 reg_pullup; 31 u8 reg_pullup;
30 u8 reg_pulldn; 32 u8 reg_pulldn;
@@ -47,8 +49,11 @@ struct sx150x_chip {
47 const struct sx150x_device_data *dev_cfg; 49 const struct sx150x_device_data *dev_cfg;
48 int irq_summary; 50 int irq_summary;
49 int irq_base; 51 int irq_base;
52 int irq_update;
50 u32 irq_sense; 53 u32 irq_sense;
51 unsigned long irq_set_type_pending; 54 u32 irq_masked;
55 u32 dev_sense;
56 u32 dev_masked;
52 struct irq_chip irq_chip; 57 struct irq_chip irq_chip;
53 struct mutex lock; 58 struct mutex lock;
54}; 59};
@@ -304,36 +309,34 @@ static int sx150x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
304 return chip->irq_base + offset; 309 return chip->irq_base + offset;
305} 310}
306 311
307static void sx150x_irq_mask(unsigned int irq) 312static void sx150x_irq_mask(struct irq_data *d)
308{ 313{
309 struct irq_chip *ic = get_irq_chip(irq); 314 struct irq_chip *ic = irq_data_get_irq_chip(d);
310 struct sx150x_chip *chip; 315 struct sx150x_chip *chip;
311 unsigned n; 316 unsigned n;
312 317
313 chip = container_of(ic, struct sx150x_chip, irq_chip); 318 chip = container_of(ic, struct sx150x_chip, irq_chip);
314 n = irq - chip->irq_base; 319 n = d->irq - chip->irq_base;
315 320 chip->irq_masked |= (1 << n);
316 sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1); 321 chip->irq_update = n;
317 sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
318} 322}
319 323
320static void sx150x_irq_unmask(unsigned int irq) 324static void sx150x_irq_unmask(struct irq_data *d)
321{ 325{
322 struct irq_chip *ic = get_irq_chip(irq); 326 struct irq_chip *ic = irq_data_get_irq_chip(d);
323 struct sx150x_chip *chip; 327 struct sx150x_chip *chip;
324 unsigned n; 328 unsigned n;
325 329
326 chip = container_of(ic, struct sx150x_chip, irq_chip); 330 chip = container_of(ic, struct sx150x_chip, irq_chip);
327 n = irq - chip->irq_base; 331 n = d->irq - chip->irq_base;
328 332
329 sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0); 333 chip->irq_masked &= ~(1 << n);
330 sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 334 chip->irq_update = n;
331 chip->irq_sense >> (n * 2));
332} 335}
333 336
334static int sx150x_irq_set_type(unsigned int irq, unsigned int flow_type) 337static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
335{ 338{
336 struct irq_chip *ic = get_irq_chip(irq); 339 struct irq_chip *ic = irq_data_get_irq_chip(d);
337 struct sx150x_chip *chip; 340 struct sx150x_chip *chip;
338 unsigned n, val = 0; 341 unsigned n, val = 0;
339 342
@@ -341,7 +344,7 @@ static int sx150x_irq_set_type(unsigned int irq, unsigned int flow_type)
341 return -EINVAL; 344 return -EINVAL;
342 345
343 chip = container_of(ic, struct sx150x_chip, irq_chip); 346 chip = container_of(ic, struct sx150x_chip, irq_chip);
344 n = irq - chip->irq_base; 347 n = d->irq - chip->irq_base;
345 348
346 if (flow_type & IRQ_TYPE_EDGE_RISING) 349 if (flow_type & IRQ_TYPE_EDGE_RISING)
347 val |= 0x1; 350 val |= 0x1;
@@ -350,7 +353,7 @@ static int sx150x_irq_set_type(unsigned int irq, unsigned int flow_type)
350 353
351 chip->irq_sense &= ~(3UL << (n * 2)); 354 chip->irq_sense &= ~(3UL << (n * 2));
352 chip->irq_sense |= val << (n * 2); 355 chip->irq_sense |= val << (n * 2);
353 chip->irq_set_type_pending |= BIT(n); 356 chip->irq_update = n;
354 return 0; 357 return 0;
355} 358}
356 359
@@ -386,9 +389,9 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
386 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 389 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
387} 390}
388 391
389static void sx150x_irq_bus_lock(unsigned int irq) 392static void sx150x_irq_bus_lock(struct irq_data *d)
390{ 393{
391 struct irq_chip *ic = get_irq_chip(irq); 394 struct irq_chip *ic = irq_data_get_irq_chip(d);
392 struct sx150x_chip *chip; 395 struct sx150x_chip *chip;
393 396
394 chip = container_of(ic, struct sx150x_chip, irq_chip); 397 chip = container_of(ic, struct sx150x_chip, irq_chip);
@@ -396,23 +399,37 @@ static void sx150x_irq_bus_lock(unsigned int irq)
396 mutex_lock(&chip->lock); 399 mutex_lock(&chip->lock);
397} 400}
398 401
399static void sx150x_irq_bus_sync_unlock(unsigned int irq) 402static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
400{ 403{
401 struct irq_chip *ic = get_irq_chip(irq); 404 struct irq_chip *ic = irq_data_get_irq_chip(d);
402 struct sx150x_chip *chip; 405 struct sx150x_chip *chip;
403 unsigned n; 406 unsigned n;
404 407
405 chip = container_of(ic, struct sx150x_chip, irq_chip); 408 chip = container_of(ic, struct sx150x_chip, irq_chip);
406 409
407 while (chip->irq_set_type_pending) { 410 if (chip->irq_update == NO_UPDATE_PENDING)
408 n = __ffs(chip->irq_set_type_pending); 411 goto out;
409 chip->irq_set_type_pending &= ~BIT(n); 412
410 if (!(irq_to_desc(n + chip->irq_base)->status & IRQ_MASKED)) 413 n = chip->irq_update;
411 sx150x_write_cfg(chip, n, 2, 414 chip->irq_update = NO_UPDATE_PENDING;
412 chip->dev_cfg->reg_sense,
413 chip->irq_sense >> (n * 2));
414 }
415 415
416 /* Avoid updates if nothing changed */
417 if (chip->dev_sense == chip->irq_sense &&
418 chip->dev_sense == chip->irq_masked)
419 goto out;
420
421 chip->dev_sense = chip->irq_sense;
422 chip->dev_masked = chip->irq_masked;
423
424 if (chip->irq_masked & (1 << n)) {
425 sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
426 sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
427 } else {
428 sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
429 sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
430 chip->irq_sense >> (n * 2));
431 }
432out:
416 mutex_unlock(&chip->lock); 433 mutex_unlock(&chip->lock);
417} 434}
418 435
@@ -437,16 +454,19 @@ static void sx150x_init_chip(struct sx150x_chip *chip,
437 if (pdata->oscio_is_gpo) 454 if (pdata->oscio_is_gpo)
438 ++chip->gpio_chip.ngpio; 455 ++chip->gpio_chip.ngpio;
439 456
440 chip->irq_chip.name = client->name; 457 chip->irq_chip.name = client->name;
441 chip->irq_chip.mask = sx150x_irq_mask; 458 chip->irq_chip.irq_mask = sx150x_irq_mask;
442 chip->irq_chip.unmask = sx150x_irq_unmask; 459 chip->irq_chip.irq_unmask = sx150x_irq_unmask;
443 chip->irq_chip.set_type = sx150x_irq_set_type; 460 chip->irq_chip.irq_set_type = sx150x_irq_set_type;
444 chip->irq_chip.bus_lock = sx150x_irq_bus_lock; 461 chip->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
445 chip->irq_chip.bus_sync_unlock = sx150x_irq_bus_sync_unlock; 462 chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
446 chip->irq_summary = -1; 463 chip->irq_summary = -1;
447 chip->irq_base = -1; 464 chip->irq_base = -1;
448 chip->irq_sense = 0; 465 chip->irq_masked = ~0;
449 chip->irq_set_type_pending = 0; 466 chip->irq_sense = 0;
467 chip->dev_masked = ~0;
468 chip->dev_sense = 0;
469 chip->irq_update = NO_UPDATE_PENDING;
450} 470}
451 471
452static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg) 472static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
@@ -531,12 +551,12 @@ static int sx150x_install_irq_chip(struct sx150x_chip *chip,
531 551
532 for (n = 0; n < chip->dev_cfg->ngpios; ++n) { 552 for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
533 irq = irq_base + n; 553 irq = irq_base + n;
534 set_irq_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq); 554 irq_set_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
535 set_irq_nested_thread(irq, 1); 555 irq_set_nested_thread(irq, 1);
536#ifdef CONFIG_ARM 556#ifdef CONFIG_ARM
537 set_irq_flags(irq, IRQF_VALID); 557 set_irq_flags(irq, IRQF_VALID);
538#else 558#else
539 set_irq_noprobe(irq); 559 irq_set_noprobe(irq);
540#endif 560#endif
541 } 561 }
542 562
@@ -563,8 +583,7 @@ static void sx150x_remove_irq_chip(struct sx150x_chip *chip)
563 583
564 for (n = 0; n < chip->dev_cfg->ngpios; ++n) { 584 for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
565 irq = chip->irq_base + n; 585 irq = chip->irq_base + n;
566 set_irq_handler(irq, NULL); 586 irq_set_chip_and_handler(irq, NULL, NULL);
567 set_irq_chip(irq, NULL);
568 } 587 }
569} 588}
570 589
diff --git a/drivers/gpio/tc35892-gpio.c b/drivers/gpio/tc35892-gpio.c
deleted file mode 100644
index 1be6288780de..000000000000
--- a/drivers/gpio/tc35892-gpio.c
+++ /dev/null
@@ -1,381 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
7 */
8
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/gpio.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/mfd/tc35892.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
23
24#define CACHE_NR_REGS 4
25#define CACHE_NR_BANKS 3
26
27struct tc35892_gpio {
28 struct gpio_chip chip;
29 struct tc35892 *tc35892;
30 struct device *dev;
31 struct mutex irq_lock;
32
33 int irq_base;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct tc35892_gpio *to_tc35892_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct tc35892_gpio, chip);
43}
44
45static int tc35892_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip);
48 struct tc35892 *tc35892 = tc35892_gpio->tc35892;
49 u8 reg = TC35892_GPIODATA0 + (offset / 8) * 2;
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = tc35892_reg_read(tc35892, reg);
54 if (ret < 0)
55 return ret;
56
57 return ret & mask;
58}
59
60static void tc35892_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip);
63 struct tc35892 *tc35892 = tc35892_gpio->tc35892;
64 u8 reg = TC35892_GPIODATA0 + (offset / 8) * 2;
65 unsigned pos = offset % 8;
66 u8 data[] = {!!val << pos, 1 << pos};
67
68 tc35892_block_write(tc35892, reg, ARRAY_SIZE(data), data);
69}
70
71static int tc35892_gpio_direction_output(struct gpio_chip *chip,
72 unsigned offset, int val)
73{
74 struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip);
75 struct tc35892 *tc35892 = tc35892_gpio->tc35892;
76 u8 reg = TC35892_GPIODIR0 + offset / 8;
77 unsigned pos = offset % 8;
78
79 tc35892_gpio_set(chip, offset, val);
80
81 return tc35892_set_bits(tc35892, reg, 1 << pos, 1 << pos);
82}
83
84static int tc35892_gpio_direction_input(struct gpio_chip *chip,
85 unsigned offset)
86{
87 struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip);
88 struct tc35892 *tc35892 = tc35892_gpio->tc35892;
89 u8 reg = TC35892_GPIODIR0 + offset / 8;
90 unsigned pos = offset % 8;
91
92 return tc35892_set_bits(tc35892, reg, 1 << pos, 0);
93}
94
95static int tc35892_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
96{
97 struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip);
98
99 return tc35892_gpio->irq_base + offset;
100}
101
102static struct gpio_chip template_chip = {
103 .label = "tc35892",
104 .owner = THIS_MODULE,
105 .direction_input = tc35892_gpio_direction_input,
106 .get = tc35892_gpio_get,
107 .direction_output = tc35892_gpio_direction_output,
108 .set = tc35892_gpio_set,
109 .to_irq = tc35892_gpio_to_irq,
110 .can_sleep = 1,
111};
112
113static int tc35892_gpio_irq_set_type(unsigned int irq, unsigned int type)
114{
115 struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq);
116 int offset = irq - tc35892_gpio->irq_base;
117 int regoffset = offset / 8;
118 int mask = 1 << (offset % 8);
119
120 if (type == IRQ_TYPE_EDGE_BOTH) {
121 tc35892_gpio->regs[REG_IBE][regoffset] |= mask;
122 return 0;
123 }
124
125 tc35892_gpio->regs[REG_IBE][regoffset] &= ~mask;
126
127 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
128 tc35892_gpio->regs[REG_IS][regoffset] |= mask;
129 else
130 tc35892_gpio->regs[REG_IS][regoffset] &= ~mask;
131
132 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
133 tc35892_gpio->regs[REG_IEV][regoffset] |= mask;
134 else
135 tc35892_gpio->regs[REG_IEV][regoffset] &= ~mask;
136
137 return 0;
138}
139
140static void tc35892_gpio_irq_lock(unsigned int irq)
141{
142 struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq);
143
144 mutex_lock(&tc35892_gpio->irq_lock);
145}
146
147static void tc35892_gpio_irq_sync_unlock(unsigned int irq)
148{
149 struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq);
150 struct tc35892 *tc35892 = tc35892_gpio->tc35892;
151 static const u8 regmap[] = {
152 [REG_IBE] = TC35892_GPIOIBE0,
153 [REG_IEV] = TC35892_GPIOIEV0,
154 [REG_IS] = TC35892_GPIOIS0,
155 [REG_IE] = TC35892_GPIOIE0,
156 };
157 int i, j;
158
159 for (i = 0; i < CACHE_NR_REGS; i++) {
160 for (j = 0; j < CACHE_NR_BANKS; j++) {
161 u8 old = tc35892_gpio->oldregs[i][j];
162 u8 new = tc35892_gpio->regs[i][j];
163
164 if (new == old)
165 continue;
166
167 tc35892_gpio->oldregs[i][j] = new;
168 tc35892_reg_write(tc35892, regmap[i] + j * 8, new);
169 }
170 }
171
172 mutex_unlock(&tc35892_gpio->irq_lock);
173}
174
175static void tc35892_gpio_irq_mask(unsigned int irq)
176{
177 struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq);
178 int offset = irq - tc35892_gpio->irq_base;
179 int regoffset = offset / 8;
180 int mask = 1 << (offset % 8);
181
182 tc35892_gpio->regs[REG_IE][regoffset] &= ~mask;
183}
184
185static void tc35892_gpio_irq_unmask(unsigned int irq)
186{
187 struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq);
188 int offset = irq - tc35892_gpio->irq_base;
189 int regoffset = offset / 8;
190 int mask = 1 << (offset % 8);
191
192 tc35892_gpio->regs[REG_IE][regoffset] |= mask;
193}
194
195static struct irq_chip tc35892_gpio_irq_chip = {
196 .name = "tc35892-gpio",
197 .bus_lock = tc35892_gpio_irq_lock,
198 .bus_sync_unlock = tc35892_gpio_irq_sync_unlock,
199 .mask = tc35892_gpio_irq_mask,
200 .unmask = tc35892_gpio_irq_unmask,
201 .set_type = tc35892_gpio_irq_set_type,
202};
203
204static irqreturn_t tc35892_gpio_irq(int irq, void *dev)
205{
206 struct tc35892_gpio *tc35892_gpio = dev;
207 struct tc35892 *tc35892 = tc35892_gpio->tc35892;
208 u8 status[CACHE_NR_BANKS];
209 int ret;
210 int i;
211
212 ret = tc35892_block_read(tc35892, TC35892_GPIOMIS0,
213 ARRAY_SIZE(status), status);
214 if (ret < 0)
215 return IRQ_NONE;
216
217 for (i = 0; i < ARRAY_SIZE(status); i++) {
218 unsigned int stat = status[i];
219 if (!stat)
220 continue;
221
222 while (stat) {
223 int bit = __ffs(stat);
224 int line = i * 8 + bit;
225
226 handle_nested_irq(tc35892_gpio->irq_base + line);
227 stat &= ~(1 << bit);
228 }
229
230 tc35892_reg_write(tc35892, TC35892_GPIOIC0 + i, status[i]);
231 }
232
233 return IRQ_HANDLED;
234}
235
236static int tc35892_gpio_irq_init(struct tc35892_gpio *tc35892_gpio)
237{
238 int base = tc35892_gpio->irq_base;
239 int irq;
240
241 for (irq = base; irq < base + tc35892_gpio->chip.ngpio; irq++) {
242 set_irq_chip_data(irq, tc35892_gpio);
243 set_irq_chip_and_handler(irq, &tc35892_gpio_irq_chip,
244 handle_simple_irq);
245 set_irq_nested_thread(irq, 1);
246#ifdef CONFIG_ARM
247 set_irq_flags(irq, IRQF_VALID);
248#else
249 set_irq_noprobe(irq);
250#endif
251 }
252
253 return 0;
254}
255
256static void tc35892_gpio_irq_remove(struct tc35892_gpio *tc35892_gpio)
257{
258 int base = tc35892_gpio->irq_base;
259 int irq;
260
261 for (irq = base; irq < base + tc35892_gpio->chip.ngpio; irq++) {
262#ifdef CONFIG_ARM
263 set_irq_flags(irq, 0);
264#endif
265 set_irq_chip_and_handler(irq, NULL, NULL);
266 set_irq_chip_data(irq, NULL);
267 }
268}
269
270static int __devinit tc35892_gpio_probe(struct platform_device *pdev)
271{
272 struct tc35892 *tc35892 = dev_get_drvdata(pdev->dev.parent);
273 struct tc35892_gpio_platform_data *pdata;
274 struct tc35892_gpio *tc35892_gpio;
275 int ret;
276 int irq;
277
278 pdata = tc35892->pdata->gpio;
279 if (!pdata)
280 return -ENODEV;
281
282 irq = platform_get_irq(pdev, 0);
283 if (irq < 0)
284 return irq;
285
286 tc35892_gpio = kzalloc(sizeof(struct tc35892_gpio), GFP_KERNEL);
287 if (!tc35892_gpio)
288 return -ENOMEM;
289
290 mutex_init(&tc35892_gpio->irq_lock);
291
292 tc35892_gpio->dev = &pdev->dev;
293 tc35892_gpio->tc35892 = tc35892;
294
295 tc35892_gpio->chip = template_chip;
296 tc35892_gpio->chip.ngpio = tc35892->num_gpio;
297 tc35892_gpio->chip.dev = &pdev->dev;
298 tc35892_gpio->chip.base = pdata->gpio_base;
299
300 tc35892_gpio->irq_base = tc35892->irq_base + TC35892_INT_GPIO(0);
301
302 /* Bring the GPIO module out of reset */
303 ret = tc35892_set_bits(tc35892, TC35892_RSTCTRL,
304 TC35892_RSTCTRL_GPIRST, 0);
305 if (ret < 0)
306 goto out_free;
307
308 ret = tc35892_gpio_irq_init(tc35892_gpio);
309 if (ret)
310 goto out_free;
311
312 ret = request_threaded_irq(irq, NULL, tc35892_gpio_irq, IRQF_ONESHOT,
313 "tc35892-gpio", tc35892_gpio);
314 if (ret) {
315 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
316 goto out_removeirq;
317 }
318
319 ret = gpiochip_add(&tc35892_gpio->chip);
320 if (ret) {
321 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
322 goto out_freeirq;
323 }
324
325 platform_set_drvdata(pdev, tc35892_gpio);
326
327 return 0;
328
329out_freeirq:
330 free_irq(irq, tc35892_gpio);
331out_removeirq:
332 tc35892_gpio_irq_remove(tc35892_gpio);
333out_free:
334 kfree(tc35892_gpio);
335 return ret;
336}
337
338static int __devexit tc35892_gpio_remove(struct platform_device *pdev)
339{
340 struct tc35892_gpio *tc35892_gpio = platform_get_drvdata(pdev);
341 int irq = platform_get_irq(pdev, 0);
342 int ret;
343
344 ret = gpiochip_remove(&tc35892_gpio->chip);
345 if (ret < 0) {
346 dev_err(tc35892_gpio->dev,
347 "unable to remove gpiochip: %d\n", ret);
348 return ret;
349 }
350
351 free_irq(irq, tc35892_gpio);
352 tc35892_gpio_irq_remove(tc35892_gpio);
353
354 platform_set_drvdata(pdev, NULL);
355 kfree(tc35892_gpio);
356
357 return 0;
358}
359
360static struct platform_driver tc35892_gpio_driver = {
361 .driver.name = "tc35892-gpio",
362 .driver.owner = THIS_MODULE,
363 .probe = tc35892_gpio_probe,
364 .remove = __devexit_p(tc35892_gpio_remove),
365};
366
367static int __init tc35892_gpio_init(void)
368{
369 return platform_driver_register(&tc35892_gpio_driver);
370}
371subsys_initcall(tc35892_gpio_init);
372
373static void __exit tc35892_gpio_exit(void)
374{
375 platform_driver_unregister(&tc35892_gpio_driver);
376}
377module_exit(tc35892_gpio_exit);
378
379MODULE_LICENSE("GPL v2");
380MODULE_DESCRIPTION("TC35892 GPIO driver");
381MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");
diff --git a/drivers/gpio/tc3589x-gpio.c b/drivers/gpio/tc3589x-gpio.c
new file mode 100644
index 000000000000..2a82e8999a42
--- /dev/null
+++ b/drivers/gpio/tc3589x-gpio.c
@@ -0,0 +1,389 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
7 */
8
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/gpio.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/mfd/tc3589x.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
23
24#define CACHE_NR_REGS 4
25#define CACHE_NR_BANKS 3
26
27struct tc3589x_gpio {
28 struct gpio_chip chip;
29 struct tc3589x *tc3589x;
30 struct device *dev;
31 struct mutex irq_lock;
32
33 int irq_base;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct tc3589x_gpio, chip);
43}
44
45static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
48 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
49 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = tc3589x_reg_read(tc3589x, reg);
54 if (ret < 0)
55 return ret;
56
57 return ret & mask;
58}
59
60static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
63 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
64 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
65 unsigned pos = offset % 8;
66 u8 data[] = {!!val << pos, 1 << pos};
67
68 tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
69}
70
71static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
72 unsigned offset, int val)
73{
74 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
75 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
76 u8 reg = TC3589x_GPIODIR0 + offset / 8;
77 unsigned pos = offset % 8;
78
79 tc3589x_gpio_set(chip, offset, val);
80
81 return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
82}
83
84static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
85 unsigned offset)
86{
87 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
88 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
89 u8 reg = TC3589x_GPIODIR0 + offset / 8;
90 unsigned pos = offset % 8;
91
92 return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
93}
94
95static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
96{
97 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
98
99 return tc3589x_gpio->irq_base + offset;
100}
101
102static struct gpio_chip template_chip = {
103 .label = "tc3589x",
104 .owner = THIS_MODULE,
105 .direction_input = tc3589x_gpio_direction_input,
106 .get = tc3589x_gpio_get,
107 .direction_output = tc3589x_gpio_direction_output,
108 .set = tc3589x_gpio_set,
109 .to_irq = tc3589x_gpio_to_irq,
110 .can_sleep = 1,
111};
112
113static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
114{
115 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
116 int offset = d->irq - tc3589x_gpio->irq_base;
117 int regoffset = offset / 8;
118 int mask = 1 << (offset % 8);
119
120 if (type == IRQ_TYPE_EDGE_BOTH) {
121 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
122 return 0;
123 }
124
125 tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
126
127 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
128 tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
129 else
130 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
131
132 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
133 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
134 else
135 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
136
137 return 0;
138}
139
140static void tc3589x_gpio_irq_lock(struct irq_data *d)
141{
142 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
143
144 mutex_lock(&tc3589x_gpio->irq_lock);
145}
146
147static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
148{
149 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
150 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
151 static const u8 regmap[] = {
152 [REG_IBE] = TC3589x_GPIOIBE0,
153 [REG_IEV] = TC3589x_GPIOIEV0,
154 [REG_IS] = TC3589x_GPIOIS0,
155 [REG_IE] = TC3589x_GPIOIE0,
156 };
157 int i, j;
158
159 for (i = 0; i < CACHE_NR_REGS; i++) {
160 for (j = 0; j < CACHE_NR_BANKS; j++) {
161 u8 old = tc3589x_gpio->oldregs[i][j];
162 u8 new = tc3589x_gpio->regs[i][j];
163
164 if (new == old)
165 continue;
166
167 tc3589x_gpio->oldregs[i][j] = new;
168 tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
169 }
170 }
171
172 mutex_unlock(&tc3589x_gpio->irq_lock);
173}
174
175static void tc3589x_gpio_irq_mask(struct irq_data *d)
176{
177 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
178 int offset = d->irq - tc3589x_gpio->irq_base;
179 int regoffset = offset / 8;
180 int mask = 1 << (offset % 8);
181
182 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
183}
184
185static void tc3589x_gpio_irq_unmask(struct irq_data *d)
186{
187 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
188 int offset = d->irq - tc3589x_gpio->irq_base;
189 int regoffset = offset / 8;
190 int mask = 1 << (offset % 8);
191
192 tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
193}
194
195static struct irq_chip tc3589x_gpio_irq_chip = {
196 .name = "tc3589x-gpio",
197 .irq_bus_lock = tc3589x_gpio_irq_lock,
198 .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
199 .irq_mask = tc3589x_gpio_irq_mask,
200 .irq_unmask = tc3589x_gpio_irq_unmask,
201 .irq_set_type = tc3589x_gpio_irq_set_type,
202};
203
204static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
205{
206 struct tc3589x_gpio *tc3589x_gpio = dev;
207 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
208 u8 status[CACHE_NR_BANKS];
209 int ret;
210 int i;
211
212 ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
213 ARRAY_SIZE(status), status);
214 if (ret < 0)
215 return IRQ_NONE;
216
217 for (i = 0; i < ARRAY_SIZE(status); i++) {
218 unsigned int stat = status[i];
219 if (!stat)
220 continue;
221
222 while (stat) {
223 int bit = __ffs(stat);
224 int line = i * 8 + bit;
225
226 handle_nested_irq(tc3589x_gpio->irq_base + line);
227 stat &= ~(1 << bit);
228 }
229
230 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
231 }
232
233 return IRQ_HANDLED;
234}
235
236static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio)
237{
238 int base = tc3589x_gpio->irq_base;
239 int irq;
240
241 for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
242 irq_set_chip_data(irq, tc3589x_gpio);
243 irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
244 handle_simple_irq);
245 irq_set_nested_thread(irq, 1);
246#ifdef CONFIG_ARM
247 set_irq_flags(irq, IRQF_VALID);
248#else
249 irq_set_noprobe(irq);
250#endif
251 }
252
253 return 0;
254}
255
256static void tc3589x_gpio_irq_remove(struct tc3589x_gpio *tc3589x_gpio)
257{
258 int base = tc3589x_gpio->irq_base;
259 int irq;
260
261 for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
262#ifdef CONFIG_ARM
263 set_irq_flags(irq, 0);
264#endif
265 irq_set_chip_and_handler(irq, NULL, NULL);
266 irq_set_chip_data(irq, NULL);
267 }
268}
269
270static int __devinit tc3589x_gpio_probe(struct platform_device *pdev)
271{
272 struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
273 struct tc3589x_gpio_platform_data *pdata;
274 struct tc3589x_gpio *tc3589x_gpio;
275 int ret;
276 int irq;
277
278 pdata = tc3589x->pdata->gpio;
279 if (!pdata)
280 return -ENODEV;
281
282 irq = platform_get_irq(pdev, 0);
283 if (irq < 0)
284 return irq;
285
286 tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
287 if (!tc3589x_gpio)
288 return -ENOMEM;
289
290 mutex_init(&tc3589x_gpio->irq_lock);
291
292 tc3589x_gpio->dev = &pdev->dev;
293 tc3589x_gpio->tc3589x = tc3589x;
294
295 tc3589x_gpio->chip = template_chip;
296 tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
297 tc3589x_gpio->chip.dev = &pdev->dev;
298 tc3589x_gpio->chip.base = pdata->gpio_base;
299
300 tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0);
301
302 /* Bring the GPIO module out of reset */
303 ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
304 TC3589x_RSTCTRL_GPIRST, 0);
305 if (ret < 0)
306 goto out_free;
307
308 ret = tc3589x_gpio_irq_init(tc3589x_gpio);
309 if (ret)
310 goto out_free;
311
312 ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
313 "tc3589x-gpio", tc3589x_gpio);
314 if (ret) {
315 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
316 goto out_removeirq;
317 }
318
319 ret = gpiochip_add(&tc3589x_gpio->chip);
320 if (ret) {
321 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
322 goto out_freeirq;
323 }
324
325 if (pdata->setup)
326 pdata->setup(tc3589x, tc3589x_gpio->chip.base);
327
328 platform_set_drvdata(pdev, tc3589x_gpio);
329
330 return 0;
331
332out_freeirq:
333 free_irq(irq, tc3589x_gpio);
334out_removeirq:
335 tc3589x_gpio_irq_remove(tc3589x_gpio);
336out_free:
337 kfree(tc3589x_gpio);
338 return ret;
339}
340
341static int __devexit tc3589x_gpio_remove(struct platform_device *pdev)
342{
343 struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
344 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
345 struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
346 int irq = platform_get_irq(pdev, 0);
347 int ret;
348
349 if (pdata->remove)
350 pdata->remove(tc3589x, tc3589x_gpio->chip.base);
351
352 ret = gpiochip_remove(&tc3589x_gpio->chip);
353 if (ret < 0) {
354 dev_err(tc3589x_gpio->dev,
355 "unable to remove gpiochip: %d\n", ret);
356 return ret;
357 }
358
359 free_irq(irq, tc3589x_gpio);
360 tc3589x_gpio_irq_remove(tc3589x_gpio);
361
362 platform_set_drvdata(pdev, NULL);
363 kfree(tc3589x_gpio);
364
365 return 0;
366}
367
368static struct platform_driver tc3589x_gpio_driver = {
369 .driver.name = "tc3589x-gpio",
370 .driver.owner = THIS_MODULE,
371 .probe = tc3589x_gpio_probe,
372 .remove = __devexit_p(tc3589x_gpio_remove),
373};
374
375static int __init tc3589x_gpio_init(void)
376{
377 return platform_driver_register(&tc3589x_gpio_driver);
378}
379subsys_initcall(tc3589x_gpio_init);
380
381static void __exit tc3589x_gpio_exit(void)
382{
383 platform_driver_unregister(&tc3589x_gpio_driver);
384}
385module_exit(tc3589x_gpio_exit);
386
387MODULE_LICENSE("GPL v2");
388MODULE_DESCRIPTION("TC3589x GPIO driver");
389MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");
diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/timbgpio.c
index ddd053108a13..0265872e57d1 100644
--- a/drivers/gpio/timbgpio.c
+++ b/drivers/gpio/timbgpio.c
@@ -47,6 +47,7 @@ struct timbgpio {
47 spinlock_t lock; /* mutual exclusion */ 47 spinlock_t lock; /* mutual exclusion */
48 struct gpio_chip gpio; 48 struct gpio_chip gpio;
49 int irq_base; 49 int irq_base;
50 unsigned long last_ier;
50}; 51};
51 52
52static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, 53static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
@@ -108,26 +109,34 @@ static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
108/* 109/*
109 * GPIO IRQ 110 * GPIO IRQ
110 */ 111 */
111static void timbgpio_irq_disable(unsigned irq) 112static void timbgpio_irq_disable(struct irq_data *d)
112{ 113{
113 struct timbgpio *tgpio = get_irq_chip_data(irq); 114 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
114 int offset = irq - tgpio->irq_base; 115 int offset = d->irq - tgpio->irq_base;
116 unsigned long flags;
115 117
116 timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0); 118 spin_lock_irqsave(&tgpio->lock, flags);
119 tgpio->last_ier &= ~(1 << offset);
120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
121 spin_unlock_irqrestore(&tgpio->lock, flags);
117} 122}
118 123
119static void timbgpio_irq_enable(unsigned irq) 124static void timbgpio_irq_enable(struct irq_data *d)
120{ 125{
121 struct timbgpio *tgpio = get_irq_chip_data(irq); 126 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
122 int offset = irq - tgpio->irq_base; 127 int offset = d->irq - tgpio->irq_base;
128 unsigned long flags;
123 129
124 timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1); 130 spin_lock_irqsave(&tgpio->lock, flags);
131 tgpio->last_ier |= 1 << offset;
132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
133 spin_unlock_irqrestore(&tgpio->lock, flags);
125} 134}
126 135
127static int timbgpio_irq_type(unsigned irq, unsigned trigger) 136static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
128{ 137{
129 struct timbgpio *tgpio = get_irq_chip_data(irq); 138 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
130 int offset = irq - tgpio->irq_base; 139 int offset = d->irq - tgpio->irq_base;
131 unsigned long flags; 140 unsigned long flags;
132 u32 lvr, flr, bflr = 0; 141 u32 lvr, flr, bflr = 0;
133 u32 ver; 142 u32 ver;
@@ -186,23 +195,31 @@ out:
186 195
187static void timbgpio_irq(unsigned int irq, struct irq_desc *desc) 196static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
188{ 197{
189 struct timbgpio *tgpio = get_irq_data(irq); 198 struct timbgpio *tgpio = irq_get_handler_data(irq);
190 unsigned long ipr; 199 unsigned long ipr;
191 int offset; 200 int offset;
192 201
193 desc->chip->ack(irq); 202 desc->irq_data.chip->irq_ack(irq_get_irq_data(irq));
194 ipr = ioread32(tgpio->membase + TGPIO_IPR); 203 ipr = ioread32(tgpio->membase + TGPIO_IPR);
195 iowrite32(ipr, tgpio->membase + TGPIO_ICR); 204 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
196 205
206 /*
207 * Some versions of the hardware trash the IER register if more than
208 * one interrupt is received simultaneously.
209 */
210 iowrite32(0, tgpio->membase + TGPIO_IER);
211
197 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio) 212 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
198 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); 213 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
214
215 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
199} 216}
200 217
201static struct irq_chip timbgpio_irqchip = { 218static struct irq_chip timbgpio_irqchip = {
202 .name = "GPIO", 219 .name = "GPIO",
203 .enable = timbgpio_irq_enable, 220 .irq_enable = timbgpio_irq_enable,
204 .disable = timbgpio_irq_disable, 221 .irq_disable = timbgpio_irq_disable,
205 .set_type = timbgpio_irq_type, 222 .irq_set_type = timbgpio_irq_type,
206}; 223};
207 224
208static int __devinit timbgpio_probe(struct platform_device *pdev) 225static int __devinit timbgpio_probe(struct platform_device *pdev)
@@ -274,16 +291,16 @@ static int __devinit timbgpio_probe(struct platform_device *pdev)
274 return 0; 291 return 0;
275 292
276 for (i = 0; i < pdata->nr_pins; i++) { 293 for (i = 0; i < pdata->nr_pins; i++) {
277 set_irq_chip_and_handler_name(tgpio->irq_base + i, 294 irq_set_chip_and_handler_name(tgpio->irq_base + i,
278 &timbgpio_irqchip, handle_simple_irq, "mux"); 295 &timbgpio_irqchip, handle_simple_irq, "mux");
279 set_irq_chip_data(tgpio->irq_base + i, tgpio); 296 irq_set_chip_data(tgpio->irq_base + i, tgpio);
280#ifdef CONFIG_ARM 297#ifdef CONFIG_ARM
281 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE); 298 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
282#endif 299#endif
283 } 300 }
284 301
285 set_irq_data(irq, tgpio); 302 irq_set_handler_data(irq, tgpio);
286 set_irq_chained_handler(irq, timbgpio_irq); 303 irq_set_chained_handler(irq, timbgpio_irq);
287 304
288 return 0; 305 return 0;
289 306
@@ -310,12 +327,12 @@ static int __devexit timbgpio_remove(struct platform_device *pdev)
310 if (irq >= 0 && tgpio->irq_base > 0) { 327 if (irq >= 0 && tgpio->irq_base > 0) {
311 int i; 328 int i;
312 for (i = 0; i < pdata->nr_pins; i++) { 329 for (i = 0; i < pdata->nr_pins; i++) {
313 set_irq_chip(tgpio->irq_base + i, NULL); 330 irq_set_chip(tgpio->irq_base + i, NULL);
314 set_irq_chip_data(tgpio->irq_base + i, NULL); 331 irq_set_chip_data(tgpio->irq_base + i, NULL);
315 } 332 }
316 333
317 set_irq_handler(irq, NULL); 334 irq_set_handler(irq, NULL);
318 set_irq_data(irq, NULL); 335 irq_set_handler_data(irq, NULL);
319 } 336 }
320 337
321 err = gpiochip_remove(&tgpio->gpio); 338 err = gpiochip_remove(&tgpio->gpio);
diff --git a/drivers/gpio/tps65910-gpio.c b/drivers/gpio/tps65910-gpio.c
new file mode 100644
index 000000000000..15097ca616d6
--- /dev/null
+++ b/drivers/gpio/tps65910-gpio.c
@@ -0,0 +1,102 @@
1/*
2 * tps65910-gpio.c -- TI TPS6591x
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19#include <linux/gpio.h>
20#include <linux/i2c.h>
21#include <linux/mfd/tps65910.h>
22
23static int tps65910_gpio_get(struct gpio_chip *gc, unsigned offset)
24{
25 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
26 uint8_t val;
27
28 tps65910->read(tps65910, TPS65910_GPIO0 + offset, 1, &val);
29
30 if (val & GPIO_STS_MASK)
31 return 1;
32
33 return 0;
34}
35
36static void tps65910_gpio_set(struct gpio_chip *gc, unsigned offset,
37 int value)
38{
39 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
40
41 if (value)
42 tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
43 GPIO_SET_MASK);
44 else
45 tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
46 GPIO_SET_MASK);
47}
48
49static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset,
50 int value)
51{
52 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
53
54 /* Set the initial value */
55 tps65910_gpio_set(gc, 0, value);
56
57 return tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
58 GPIO_CFG_MASK);
59}
60
61static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
62{
63 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
64
65 return tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
66 GPIO_CFG_MASK);
67}
68
69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
70{
71 int ret;
72
73 if (!gpio_base)
74 return;
75
76 tps65910->gpio.owner = THIS_MODULE;
77 tps65910->gpio.label = tps65910->i2c_client->name;
78 tps65910->gpio.dev = tps65910->dev;
79 tps65910->gpio.base = gpio_base;
80
81 switch(tps65910_chip_id(tps65910)) {
82 case TPS65910:
83 tps65910->gpio.ngpio = 6;
84 break;
85 case TPS65911:
86 tps65910->gpio.ngpio = 9;
87 break;
88 default:
89 return;
90 }
91 tps65910->gpio.can_sleep = 1;
92
93 tps65910->gpio.direction_input = tps65910_gpio_input;
94 tps65910->gpio.direction_output = tps65910_gpio_output;
95 tps65910->gpio.set = tps65910_gpio_set;
96 tps65910->gpio.get = tps65910_gpio_get;
97
98 ret = gpiochip_add(&tps65910->gpio);
99
100 if (ret)
101 dev_warn(tps65910->dev, "GPIO registration failed: %d\n", ret);
102}
diff --git a/drivers/gpio/vr41xx_giu.c b/drivers/gpio/vr41xx_giu.c
index b16c9a8c03f5..a365be040b36 100644
--- a/drivers/gpio/vr41xx_giu.c
+++ b/drivers/gpio/vr41xx_giu.c
@@ -111,69 +111,69 @@ static inline u16 giu_clear(u16 offset, u16 clear)
111 return data; 111 return data;
112} 112}
113 113
114static void ack_giuint_low(unsigned int irq) 114static void ack_giuint_low(struct irq_data *d)
115{ 115{
116 giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq)); 116 giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
117} 117}
118 118
119static void mask_giuint_low(unsigned int irq) 119static void mask_giuint_low(struct irq_data *d)
120{ 120{
121 giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); 121 giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
122} 122}
123 123
124static void mask_ack_giuint_low(unsigned int irq) 124static void mask_ack_giuint_low(struct irq_data *d)
125{ 125{
126 unsigned int pin; 126 unsigned int pin;
127 127
128 pin = GPIO_PIN_OF_IRQ(irq); 128 pin = GPIO_PIN_OF_IRQ(d->irq);
129 giu_clear(GIUINTENL, 1 << pin); 129 giu_clear(GIUINTENL, 1 << pin);
130 giu_write(GIUINTSTATL, 1 << pin); 130 giu_write(GIUINTSTATL, 1 << pin);
131} 131}
132 132
133static void unmask_giuint_low(unsigned int irq) 133static void unmask_giuint_low(struct irq_data *d)
134{ 134{
135 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); 135 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
136} 136}
137 137
138static struct irq_chip giuint_low_irq_chip = { 138static struct irq_chip giuint_low_irq_chip = {
139 .name = "GIUINTL", 139 .name = "GIUINTL",
140 .ack = ack_giuint_low, 140 .irq_ack = ack_giuint_low,
141 .mask = mask_giuint_low, 141 .irq_mask = mask_giuint_low,
142 .mask_ack = mask_ack_giuint_low, 142 .irq_mask_ack = mask_ack_giuint_low,
143 .unmask = unmask_giuint_low, 143 .irq_unmask = unmask_giuint_low,
144}; 144};
145 145
146static void ack_giuint_high(unsigned int irq) 146static void ack_giuint_high(struct irq_data *d)
147{ 147{
148 giu_write(GIUINTSTATH, 148 giu_write(GIUINTSTATH,
149 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); 149 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
150} 150}
151 151
152static void mask_giuint_high(unsigned int irq) 152static void mask_giuint_high(struct irq_data *d)
153{ 153{
154 giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); 154 giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
155} 155}
156 156
157static void mask_ack_giuint_high(unsigned int irq) 157static void mask_ack_giuint_high(struct irq_data *d)
158{ 158{
159 unsigned int pin; 159 unsigned int pin;
160 160
161 pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET; 161 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
162 giu_clear(GIUINTENH, 1 << pin); 162 giu_clear(GIUINTENH, 1 << pin);
163 giu_write(GIUINTSTATH, 1 << pin); 163 giu_write(GIUINTSTATH, 1 << pin);
164} 164}
165 165
166static void unmask_giuint_high(unsigned int irq) 166static void unmask_giuint_high(struct irq_data *d)
167{ 167{
168 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); 168 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
169} 169}
170 170
171static struct irq_chip giuint_high_irq_chip = { 171static struct irq_chip giuint_high_irq_chip = {
172 .name = "GIUINTH", 172 .name = "GIUINTH",
173 .ack = ack_giuint_high, 173 .irq_ack = ack_giuint_high,
174 .mask = mask_giuint_high, 174 .irq_mask = mask_giuint_high,
175 .mask_ack = mask_ack_giuint_high, 175 .irq_mask_ack = mask_ack_giuint_high,
176 .unmask = unmask_giuint_high, 176 .irq_unmask = unmask_giuint_high,
177}; 177};
178 178
179static int giu_get_irq(unsigned int irq) 179static int giu_get_irq(unsigned int irq)
@@ -238,13 +238,13 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
238 break; 238 break;
239 } 239 }
240 } 240 }
241 set_irq_chip_and_handler(GIU_IRQ(pin), 241 irq_set_chip_and_handler(GIU_IRQ(pin),
242 &giuint_low_irq_chip, 242 &giuint_low_irq_chip,
243 handle_edge_irq); 243 handle_edge_irq);
244 } else { 244 } else {
245 giu_clear(GIUINTTYPL, mask); 245 giu_clear(GIUINTTYPL, mask);
246 giu_clear(GIUINTHTSELL, mask); 246 giu_clear(GIUINTHTSELL, mask);
247 set_irq_chip_and_handler(GIU_IRQ(pin), 247 irq_set_chip_and_handler(GIU_IRQ(pin),
248 &giuint_low_irq_chip, 248 &giuint_low_irq_chip,
249 handle_level_irq); 249 handle_level_irq);
250 } 250 }
@@ -273,13 +273,13 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
273 break; 273 break;
274 } 274 }
275 } 275 }
276 set_irq_chip_and_handler(GIU_IRQ(pin), 276 irq_set_chip_and_handler(GIU_IRQ(pin),
277 &giuint_high_irq_chip, 277 &giuint_high_irq_chip,
278 handle_edge_irq); 278 handle_edge_irq);
279 } else { 279 } else {
280 giu_clear(GIUINTTYPH, mask); 280 giu_clear(GIUINTTYPH, mask);
281 giu_clear(GIUINTHTSELH, mask); 281 giu_clear(GIUINTHTSELH, mask);
282 set_irq_chip_and_handler(GIU_IRQ(pin), 282 irq_set_chip_and_handler(GIU_IRQ(pin),
283 &giuint_high_irq_chip, 283 &giuint_high_irq_chip,
284 handle_level_irq); 284 handle_level_irq);
285 } 285 }
@@ -539,9 +539,9 @@ static int __devinit giu_probe(struct platform_device *pdev)
539 chip = &giuint_high_irq_chip; 539 chip = &giuint_high_irq_chip;
540 540
541 if (trigger & (1 << pin)) 541 if (trigger & (1 << pin))
542 set_irq_chip_and_handler(i, chip, handle_edge_irq); 542 irq_set_chip_and_handler(i, chip, handle_edge_irq);
543 else 543 else
544 set_irq_chip_and_handler(i, chip, handle_level_irq); 544 irq_set_chip_and_handler(i, chip, handle_level_irq);
545 545
546 } 546 }
547 547
diff --git a/drivers/gpio/vx855_gpio.c b/drivers/gpio/vx855_gpio.c
new file mode 100644
index 000000000000..ef5aabd8b8b7
--- /dev/null
+++ b/drivers/gpio/vx855_gpio.c
@@ -0,0 +1,333 @@
1/*
2 * Linux GPIOlib driver for the VIA VX855 integrated southbridge GPIO
3 *
4 * Copyright (C) 2009 VIA Technologies, Inc.
5 * Copyright (C) 2010 One Laptop per Child
6 * Author: Harald Welte <HaraldWelte@viatech.com>
7 * All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/gpio.h>
29#include <linux/slab.h>
30#include <linux/device.h>
31#include <linux/platform_device.h>
32#include <linux/pci.h>
33#include <linux/io.h>
34
35#define MODULE_NAME "vx855_gpio"
36
37/* The VX855 south bridge has the following GPIO pins:
38 * GPI 0...13 General Purpose Input
39 * GPO 0...12 General Purpose Output
40 * GPIO 0...14 General Purpose I/O (Open-Drain)
41 */
42
43#define NR_VX855_GPI 14
44#define NR_VX855_GPO 13
45#define NR_VX855_GPIO 15
46
47#define NR_VX855_GPInO (NR_VX855_GPI + NR_VX855_GPO)
48#define NR_VX855_GP (NR_VX855_GPI + NR_VX855_GPO + NR_VX855_GPIO)
49
50struct vx855_gpio {
51 struct gpio_chip gpio;
52 spinlock_t lock;
53 u32 io_gpi;
54 u32 io_gpo;
55 bool gpi_reserved;
56 bool gpo_reserved;
57};
58
59/* resolve a GPIx into the corresponding bit position */
60static inline u_int32_t gpi_i_bit(int i)
61{
62 if (i < 10)
63 return 1 << i;
64 else
65 return 1 << (i + 14);
66}
67
68static inline u_int32_t gpo_o_bit(int i)
69{
70 if (i < 11)
71 return 1 << i;
72 else
73 return 1 << (i + 14);
74}
75
76static inline u_int32_t gpio_i_bit(int i)
77{
78 if (i < 14)
79 return 1 << (i + 10);
80 else
81 return 1 << (i + 14);
82}
83
84static inline u_int32_t gpio_o_bit(int i)
85{
86 if (i < 14)
87 return 1 << (i + 11);
88 else
89 return 1 << (i + 13);
90}
91
92/* Mapping betwee numeric GPIO ID and the actual GPIO hardware numbering:
93 * 0..13 GPI 0..13
94 * 14..26 GPO 0..12
95 * 27..41 GPIO 0..14
96 */
97
98static int vx855gpio_direction_input(struct gpio_chip *gpio,
99 unsigned int nr)
100{
101 struct vx855_gpio *vg = container_of(gpio, struct vx855_gpio, gpio);
102 unsigned long flags;
103 u_int32_t reg_out;
104
105 /* Real GPI bits are always in input direction */
106 if (nr < NR_VX855_GPI)
107 return 0;
108
109 /* Real GPO bits cannot be put in output direction */
110 if (nr < NR_VX855_GPInO)
111 return -EINVAL;
112
113 /* Open Drain GPIO have to be set to one */
114 spin_lock_irqsave(&vg->lock, flags);
115 reg_out = inl(vg->io_gpo);
116 reg_out |= gpio_o_bit(nr - NR_VX855_GPInO);
117 outl(reg_out, vg->io_gpo);
118 spin_unlock_irqrestore(&vg->lock, flags);
119
120 return 0;
121}
122
123static int vx855gpio_get(struct gpio_chip *gpio, unsigned int nr)
124{
125 struct vx855_gpio *vg = container_of(gpio, struct vx855_gpio, gpio);
126 u_int32_t reg_in;
127 int ret = 0;
128
129 if (nr < NR_VX855_GPI) {
130 reg_in = inl(vg->io_gpi);
131 if (reg_in & gpi_i_bit(nr))
132 ret = 1;
133 } else if (nr < NR_VX855_GPInO) {
134 /* GPO don't have an input bit, we need to read it
135 * back from the output register */
136 reg_in = inl(vg->io_gpo);
137 if (reg_in & gpo_o_bit(nr - NR_VX855_GPI))
138 ret = 1;
139 } else {
140 reg_in = inl(vg->io_gpi);
141 if (reg_in & gpio_i_bit(nr - NR_VX855_GPInO))
142 ret = 1;
143 }
144
145 return ret;
146}
147
148static void vx855gpio_set(struct gpio_chip *gpio, unsigned int nr,
149 int val)
150{
151 struct vx855_gpio *vg = container_of(gpio, struct vx855_gpio, gpio);
152 unsigned long flags;
153 u_int32_t reg_out;
154
155 /* True GPI cannot be switched to output mode */
156 if (nr < NR_VX855_GPI)
157 return;
158
159 spin_lock_irqsave(&vg->lock, flags);
160 reg_out = inl(vg->io_gpo);
161 if (nr < NR_VX855_GPInO) {
162 if (val)
163 reg_out |= gpo_o_bit(nr - NR_VX855_GPI);
164 else
165 reg_out &= ~gpo_o_bit(nr - NR_VX855_GPI);
166 } else {
167 if (val)
168 reg_out |= gpio_o_bit(nr - NR_VX855_GPInO);
169 else
170 reg_out &= ~gpio_o_bit(nr - NR_VX855_GPInO);
171 }
172 outl(reg_out, vg->io_gpo);
173 spin_unlock_irqrestore(&vg->lock, flags);
174}
175
176static int vx855gpio_direction_output(struct gpio_chip *gpio,
177 unsigned int nr, int val)
178{
179 /* True GPI cannot be switched to output mode */
180 if (nr < NR_VX855_GPI)
181 return -EINVAL;
182
183 /* True GPO don't need to be switched to output mode,
184 * and GPIO are open-drain, i.e. also need no switching,
185 * so all we do is set the level */
186 vx855gpio_set(gpio, nr, val);
187
188 return 0;
189}
190
191static const char *vx855gpio_names[NR_VX855_GP] = {
192 "VX855_GPI0", "VX855_GPI1", "VX855_GPI2", "VX855_GPI3", "VX855_GPI4",
193 "VX855_GPI5", "VX855_GPI6", "VX855_GPI7", "VX855_GPI8", "VX855_GPI9",
194 "VX855_GPI10", "VX855_GPI11", "VX855_GPI12", "VX855_GPI13",
195 "VX855_GPO0", "VX855_GPO1", "VX855_GPO2", "VX855_GPO3", "VX855_GPO4",
196 "VX855_GPO5", "VX855_GPO6", "VX855_GPO7", "VX855_GPO8", "VX855_GPO9",
197 "VX855_GPO10", "VX855_GPO11", "VX855_GPO12",
198 "VX855_GPIO0", "VX855_GPIO1", "VX855_GPIO2", "VX855_GPIO3",
199 "VX855_GPIO4", "VX855_GPIO5", "VX855_GPIO6", "VX855_GPIO7",
200 "VX855_GPIO8", "VX855_GPIO9", "VX855_GPIO10", "VX855_GPIO11",
201 "VX855_GPIO12", "VX855_GPIO13", "VX855_GPIO14"
202};
203
204static void vx855gpio_gpio_setup(struct vx855_gpio *vg)
205{
206 struct gpio_chip *c = &vg->gpio;
207
208 c->label = "VX855 South Bridge";
209 c->owner = THIS_MODULE;
210 c->direction_input = vx855gpio_direction_input;
211 c->direction_output = vx855gpio_direction_output;
212 c->get = vx855gpio_get;
213 c->set = vx855gpio_set;
214 c->dbg_show = NULL;
215 c->base = 0;
216 c->ngpio = NR_VX855_GP;
217 c->can_sleep = 0;
218 c->names = vx855gpio_names;
219}
220
221/* This platform device is ordinarily registered by the vx855 mfd driver */
222static __devinit int vx855gpio_probe(struct platform_device *pdev)
223{
224 struct resource *res_gpi;
225 struct resource *res_gpo;
226 struct vx855_gpio *vg;
227 int ret;
228
229 res_gpi = platform_get_resource(pdev, IORESOURCE_IO, 0);
230 res_gpo = platform_get_resource(pdev, IORESOURCE_IO, 1);
231 if (!res_gpi || !res_gpo)
232 return -EBUSY;
233
234 vg = kzalloc(sizeof(*vg), GFP_KERNEL);
235 if (!vg)
236 return -ENOMEM;
237
238 platform_set_drvdata(pdev, vg);
239
240 dev_info(&pdev->dev, "found VX855 GPIO controller\n");
241 vg->io_gpi = res_gpi->start;
242 vg->io_gpo = res_gpo->start;
243 spin_lock_init(&vg->lock);
244
245 /*
246 * A single byte is used to control various GPIO ports on the VX855,
247 * and in the case of the OLPC XO-1.5, some of those ports are used
248 * for switches that are interpreted and exposed through ACPI. ACPI
249 * will have reserved the region, so our own reservation will not
250 * succeed. Ignore and continue.
251 */
252
253 if (!request_region(res_gpi->start, resource_size(res_gpi),
254 MODULE_NAME "_gpi"))
255 dev_warn(&pdev->dev,
256 "GPI I/O resource busy, probably claimed by ACPI\n");
257 else
258 vg->gpi_reserved = true;
259
260 if (!request_region(res_gpo->start, resource_size(res_gpo),
261 MODULE_NAME "_gpo"))
262 dev_warn(&pdev->dev,
263 "GPO I/O resource busy, probably claimed by ACPI\n");
264 else
265 vg->gpo_reserved = true;
266
267 vx855gpio_gpio_setup(vg);
268
269 ret = gpiochip_add(&vg->gpio);
270 if (ret) {
271 dev_err(&pdev->dev, "failed to register GPIOs\n");
272 goto out_release;
273 }
274
275 return 0;
276
277out_release:
278 if (vg->gpi_reserved)
279 release_region(res_gpi->start, resource_size(res_gpi));
280 if (vg->gpo_reserved)
281 release_region(res_gpi->start, resource_size(res_gpo));
282 platform_set_drvdata(pdev, NULL);
283 kfree(vg);
284 return ret;
285}
286
287static int __devexit vx855gpio_remove(struct platform_device *pdev)
288{
289 struct vx855_gpio *vg = platform_get_drvdata(pdev);
290 struct resource *res;
291
292 if (gpiochip_remove(&vg->gpio))
293 dev_err(&pdev->dev, "unable to remove gpio_chip?\n");
294
295 if (vg->gpi_reserved) {
296 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
297 release_region(res->start, resource_size(res));
298 }
299 if (vg->gpo_reserved) {
300 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
301 release_region(res->start, resource_size(res));
302 }
303
304 platform_set_drvdata(pdev, NULL);
305 kfree(vg);
306 return 0;
307}
308
309static struct platform_driver vx855gpio_driver = {
310 .driver = {
311 .name = MODULE_NAME,
312 .owner = THIS_MODULE,
313 },
314 .probe = vx855gpio_probe,
315 .remove = __devexit_p(vx855gpio_remove),
316};
317
318static int vx855gpio_init(void)
319{
320 return platform_driver_register(&vx855gpio_driver);
321}
322module_init(vx855gpio_init);
323
324static void vx855gpio_exit(void)
325{
326 platform_driver_unregister(&vx855gpio_driver);
327}
328module_exit(vx855gpio_exit);
329
330MODULE_LICENSE("GPL");
331MODULE_AUTHOR("Harald Welte <HaraldWelte@viatech.com>");
332MODULE_DESCRIPTION("GPIO driver for the VIA VX855 chipset");
333MODULE_ALIAS("platform:vx855_gpio");
diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/wm831x-gpio.c
index 309644cf4d9b..2bcfb0be09ff 100644
--- a/drivers/gpio/wm831x-gpio.c
+++ b/drivers/gpio/wm831x-gpio.c
@@ -180,6 +180,7 @@ static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
180 break; 180 break;
181 case WM831X_GPIO_PULL_UP: 181 case WM831X_GPIO_PULL_UP:
182 pull = "pullup"; 182 pull = "pullup";
183 break;
183 default: 184 default:
184 pull = "INVALID PULL"; 185 pull = "INVALID PULL";
185 break; 186 break;
diff --git a/drivers/gpio/wm8994-gpio.c b/drivers/gpio/wm8994-gpio.c
index 2ac9a16d3daa..c822baacd8fc 100644
--- a/drivers/gpio/wm8994-gpio.c
+++ b/drivers/gpio/wm8994-gpio.c
@@ -35,6 +35,29 @@ static inline struct wm8994_gpio *to_wm8994_gpio(struct gpio_chip *chip)
35 return container_of(chip, struct wm8994_gpio, gpio_chip); 35 return container_of(chip, struct wm8994_gpio, gpio_chip);
36} 36}
37 37
38static int wm8994_gpio_request(struct gpio_chip *chip, unsigned offset)
39{
40 struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
41 struct wm8994 *wm8994 = wm8994_gpio->wm8994;
42
43 switch (wm8994->type) {
44 case WM8958:
45 switch (offset) {
46 case 1:
47 case 2:
48 case 3:
49 case 4:
50 case 6:
51 return -EINVAL;
52 }
53 break;
54 default:
55 break;
56 }
57
58 return 0;
59}
60
38static int wm8994_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 61static int wm8994_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
39{ 62{
40 struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); 63 struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
@@ -136,10 +159,12 @@ static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
136static struct gpio_chip template_chip = { 159static struct gpio_chip template_chip = {
137 .label = "wm8994", 160 .label = "wm8994",
138 .owner = THIS_MODULE, 161 .owner = THIS_MODULE,
162 .request = wm8994_gpio_request,
139 .direction_input = wm8994_gpio_direction_in, 163 .direction_input = wm8994_gpio_direction_in,
140 .get = wm8994_gpio_get, 164 .get = wm8994_gpio_get,
141 .direction_output = wm8994_gpio_direction_out, 165 .direction_output = wm8994_gpio_direction_out,
142 .set = wm8994_gpio_set, 166 .set = wm8994_gpio_set,
167 .to_irq = wm8994_gpio_to_irq,
143 .dbg_show = wm8994_gpio_dbg_show, 168 .dbg_show = wm8994_gpio_dbg_show,
144 .can_sleep = 1, 169 .can_sleep = 1,
145}; 170};
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
index 709690995d0d..846fbd5e31bf 100644
--- a/drivers/gpio/xilinx_gpio.c
+++ b/drivers/gpio/xilinx_gpio.c
@@ -171,13 +171,13 @@ static int __devinit xgpio_of_probe(struct device_node *np)
171 /* Update GPIO state shadow register with default value */ 171 /* Update GPIO state shadow register with default value */
172 tree_info = of_get_property(np, "xlnx,dout-default", NULL); 172 tree_info = of_get_property(np, "xlnx,dout-default", NULL);
173 if (tree_info) 173 if (tree_info)
174 chip->gpio_state = *tree_info; 174 chip->gpio_state = be32_to_cpup(tree_info);
175 175
176 /* Update GPIO direction shadow register with default value */ 176 /* Update GPIO direction shadow register with default value */
177 chip->gpio_dir = 0xFFFFFFFF; /* By default, all pins are inputs */ 177 chip->gpio_dir = 0xFFFFFFFF; /* By default, all pins are inputs */
178 tree_info = of_get_property(np, "xlnx,tri-default", NULL); 178 tree_info = of_get_property(np, "xlnx,tri-default", NULL);
179 if (tree_info) 179 if (tree_info)
180 chip->gpio_dir = *tree_info; 180 chip->gpio_dir = be32_to_cpup(tree_info);
181 181
182 /* Check device node and parent device node for device width */ 182 /* Check device node and parent device node for device width */
183 chip->mmchip.gc.ngpio = 32; /* By default assume full GPIO controller */ 183 chip->mmchip.gc.ngpio = 32; /* By default assume full GPIO controller */
@@ -186,7 +186,7 @@ static int __devinit xgpio_of_probe(struct device_node *np)
186 tree_info = of_get_property(np->parent, 186 tree_info = of_get_property(np->parent,
187 "xlnx,gpio-width", NULL); 187 "xlnx,gpio-width", NULL);
188 if (tree_info) 188 if (tree_info)
189 chip->mmchip.gc.ngpio = *tree_info; 189 chip->mmchip.gc.ngpio = be32_to_cpup(tree_info);
190 190
191 spin_lock_init(&chip->gpio_lock); 191 spin_lock_init(&chip->gpio_lock);
192 192
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-29 08:47:14 -0400