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path: root/drivers/gpio/gpio-omap.c
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Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r--drivers/gpio/gpio-omap.c48
1 files changed, 9 insertions, 39 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index cd1d5bf48f36..b232397ad7ec 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1054,38 +1054,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
1054 dev_err(bank->dev, "Could not get gpio dbck\n"); 1054 dev_err(bank->dev, "Could not get gpio dbck\n");
1055} 1055}
1056 1056
1057static void
1058omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1059 unsigned int num)
1060{
1061 struct irq_chip_generic *gc;
1062 struct irq_chip_type *ct;
1063
1064 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1065 handle_simple_irq);
1066 if (!gc) {
1067 dev_err(bank->dev, "Memory alloc failed for gc\n");
1068 return;
1069 }
1070
1071 ct = gc->chip_types;
1072
1073 /* NOTE: No ack required, reading IRQ status clears it. */
1074 ct->chip.irq_mask = irq_gc_mask_set_bit;
1075 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1076 ct->chip.irq_set_type = omap_gpio_irq_type;
1077
1078 if (bank->regs->wkup_en)
1079 ct->chip.irq_set_wake = omap_gpio_wake_enable;
1080
1081 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1082 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1083 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1084}
1085
1086static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) 1057static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1087{ 1058{
1088 int j;
1089 static int gpio; 1059 static int gpio;
1090 int irq_base = 0; 1060 int irq_base = 0;
1091 int ret; 1061 int ret;
@@ -1132,6 +1102,15 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1132 } 1102 }
1133#endif 1103#endif
1134 1104
1105 /* MPUIO is a bit different, reading IRQ status clears it */
1106 if (bank->is_mpuio) {
1107 irqc->irq_ack = dummy_irq_chip.irq_ack;
1108 irqc->irq_mask = irq_gc_mask_set_bit;
1109 irqc->irq_unmask = irq_gc_mask_clr_bit;
1110 if (!bank->regs->wkup_en)
1111 irqc->irq_set_wake = NULL;
1112 }
1113
1135 ret = gpiochip_irqchip_add(&bank->chip, irqc, 1114 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1136 irq_base, omap_gpio_irq_handler, 1115 irq_base, omap_gpio_irq_handler,
1137 IRQ_TYPE_NONE); 1116 IRQ_TYPE_NONE);
@@ -1145,15 +1124,6 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1145 gpiochip_set_chained_irqchip(&bank->chip, irqc, 1124 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1146 bank->irq, omap_gpio_irq_handler); 1125 bank->irq, omap_gpio_irq_handler);
1147 1126
1148 for (j = 0; j < bank->width; j++) {
1149 int irq = irq_find_mapping(bank->chip.irqdomain, j);
1150 if (bank->is_mpuio) {
1151 omap_mpuio_alloc_gc(bank, irq, bank->width);
1152 irq_set_chip_and_handler(irq, NULL, NULL);
1153 set_irq_flags(irq, 0);
1154 }
1155 }
1156
1157 return 0; 1127 return 0;
1158} 1128}
1159 1129