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-rw-r--r--drivers/edac/edac_core.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index 3493c6bdb820..871c13b4c148 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -150,6 +150,8 @@ enum mem_type {
150 MEM_FB_DDR2, /* fully buffered DDR2 */ 150 MEM_FB_DDR2, /* fully buffered DDR2 */
151 MEM_RDDR2, /* Registered DDR2 RAM */ 151 MEM_RDDR2, /* Registered DDR2 RAM */
152 MEM_XDR, /* Rambus XDR */ 152 MEM_XDR, /* Rambus XDR */
153 MEM_DDR3, /* DDR3 RAM */
154 MEM_RDDR3, /* Registered DDR3 RAM */
153}; 155};
154 156
155#define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 157#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
@@ -167,6 +169,8 @@ enum mem_type {
167#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) 169#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
168#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) 170#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
169#define MEM_FLAG_XDR BIT(MEM_XDR) 171#define MEM_FLAG_XDR BIT(MEM_XDR)
172#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
173#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
170 174
171/* chipset Error Detection and Correction capabilities and mode */ 175/* chipset Error Detection and Correction capabilities and mode */
172enum edac_type { 176enum edac_type {