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Diffstat (limited to 'drivers/dma/shdma.h')
-rw-r--r--drivers/dma/shdma.h48
1 files changed, 19 insertions, 29 deletions
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h
index 2b4bc15a2c0a..153609a1e96c 100644
--- a/drivers/dma/shdma.h
+++ b/drivers/dma/shdma.h
@@ -13,48 +13,38 @@
13#ifndef __DMA_SHDMA_H 13#ifndef __DMA_SHDMA_H
14#define __DMA_SHDMA_H 14#define __DMA_SHDMA_H
15 15
16#include <linux/device.h>
17#include <linux/dmapool.h>
18#include <linux/dmaengine.h> 16#include <linux/dmaengine.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19
20#include <asm/dmaengine.h>
19 21
20#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ 22#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
21 23
22struct sh_dmae_regs { 24struct device;
23 u32 sar; /* SAR / source address */
24 u32 dar; /* DAR / destination address */
25 u32 tcr; /* TCR / transfer count */
26};
27
28struct sh_desc {
29 struct list_head tx_list;
30 struct sh_dmae_regs hw;
31 struct list_head node;
32 struct dma_async_tx_descriptor async_tx;
33 int mark;
34};
35 25
36struct sh_dmae_chan { 26struct sh_dmae_chan {
37 dma_cookie_t completed_cookie; /* The maximum cookie completed */ 27 dma_cookie_t completed_cookie; /* The maximum cookie completed */
38 spinlock_t desc_lock; /* Descriptor operation lock */ 28 spinlock_t desc_lock; /* Descriptor operation lock */
39 struct list_head ld_queue; /* Link descriptors queue */ 29 struct list_head ld_queue; /* Link descriptors queue */
40 struct list_head ld_free; /* Link descriptors free */ 30 struct list_head ld_free; /* Link descriptors free */
41 struct dma_chan common; /* DMA common channel */ 31 struct dma_chan common; /* DMA common channel */
42 struct device *dev; /* Channel device */ 32 struct device *dev; /* Channel device */
43 struct tasklet_struct tasklet; /* Tasklet */ 33 struct tasklet_struct tasklet; /* Tasklet */
44 int descs_allocated; /* desc count */ 34 int descs_allocated; /* desc count */
35 int xmit_shift; /* log_2(bytes_per_xfer) */
36 int irq;
45 int id; /* Raw id of this channel */ 37 int id; /* Raw id of this channel */
46 char dev_id[16]; /* unique name per DMAC of channel */ 38 u32 __iomem *base;
47 39 char dev_id[16]; /* unique name per DMAC of channel */
48 /* Set chcr */
49 int (*set_chcr)(struct sh_dmae_chan *sh_chan, u32 regs);
50 /* Set DMA resource */
51 int (*set_dmars)(struct sh_dmae_chan *sh_chan, u16 res);
52}; 40};
53 41
54struct sh_dmae_device { 42struct sh_dmae_device {
55 struct dma_device common; 43 struct dma_device common;
56 struct sh_dmae_chan *chan[MAX_DMA_CHANNELS]; 44 struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS];
57 struct sh_dmae_pdata pdata; 45 struct sh_dmae_pdata *pdata;
46 u32 __iomem *chan_reg;
47 u16 __iomem *dmars;
58}; 48};
59 49
60#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) 50#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)