diff options
Diffstat (limited to 'drivers/dma/fsldma.h')
-rw-r--r-- | drivers/dma/fsldma.h | 35 |
1 files changed, 16 insertions, 19 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 0df14cbb8ca3..cb4d6ff51597 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h | |||
@@ -92,11 +92,9 @@ struct fsl_desc_sw { | |||
92 | struct list_head node; | 92 | struct list_head node; |
93 | struct list_head tx_list; | 93 | struct list_head tx_list; |
94 | struct dma_async_tx_descriptor async_tx; | 94 | struct dma_async_tx_descriptor async_tx; |
95 | struct list_head *ld; | ||
96 | void *priv; | ||
97 | } __attribute__((aligned(32))); | 95 | } __attribute__((aligned(32))); |
98 | 96 | ||
99 | struct fsl_dma_chan_regs { | 97 | struct fsldma_chan_regs { |
100 | u32 mr; /* 0x00 - Mode Register */ | 98 | u32 mr; /* 0x00 - Mode Register */ |
101 | u32 sr; /* 0x04 - Status Register */ | 99 | u32 sr; /* 0x04 - Status Register */ |
102 | u64 cdar; /* 0x08 - Current descriptor address register */ | 100 | u64 cdar; /* 0x08 - Current descriptor address register */ |
@@ -106,20 +104,19 @@ struct fsl_dma_chan_regs { | |||
106 | u64 ndar; /* 0x24 - Next Descriptor Address Register */ | 104 | u64 ndar; /* 0x24 - Next Descriptor Address Register */ |
107 | }; | 105 | }; |
108 | 106 | ||
109 | struct fsl_dma_chan; | 107 | struct fsldma_chan; |
110 | #define FSL_DMA_MAX_CHANS_PER_DEVICE 4 | 108 | #define FSL_DMA_MAX_CHANS_PER_DEVICE 4 |
111 | 109 | ||
112 | struct fsl_dma_device { | 110 | struct fsldma_device { |
113 | void __iomem *reg_base; /* DGSR register base */ | 111 | void __iomem *regs; /* DGSR register base */ |
114 | struct resource reg; /* Resource for register */ | ||
115 | struct device *dev; | 112 | struct device *dev; |
116 | struct dma_device common; | 113 | struct dma_device common; |
117 | struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; | 114 | struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; |
118 | u32 feature; /* The same as DMA channels */ | 115 | u32 feature; /* The same as DMA channels */ |
119 | int irq; /* Channel IRQ */ | 116 | int irq; /* Channel IRQ */ |
120 | }; | 117 | }; |
121 | 118 | ||
122 | /* Define macros for fsl_dma_chan->feature property */ | 119 | /* Define macros for fsldma_chan->feature property */ |
123 | #define FSL_DMA_LITTLE_ENDIAN 0x00000000 | 120 | #define FSL_DMA_LITTLE_ENDIAN 0x00000000 |
124 | #define FSL_DMA_BIG_ENDIAN 0x00000001 | 121 | #define FSL_DMA_BIG_ENDIAN 0x00000001 |
125 | 122 | ||
@@ -130,28 +127,28 @@ struct fsl_dma_device { | |||
130 | #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000 | 127 | #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000 |
131 | #define FSL_DMA_CHAN_START_EXT 0x00002000 | 128 | #define FSL_DMA_CHAN_START_EXT 0x00002000 |
132 | 129 | ||
133 | struct fsl_dma_chan { | 130 | struct fsldma_chan { |
134 | struct fsl_dma_chan_regs __iomem *reg_base; | 131 | struct fsldma_chan_regs __iomem *regs; |
135 | dma_cookie_t completed_cookie; /* The maximum cookie completed */ | 132 | dma_cookie_t completed_cookie; /* The maximum cookie completed */ |
136 | spinlock_t desc_lock; /* Descriptor operation lock */ | 133 | spinlock_t desc_lock; /* Descriptor operation lock */ |
137 | struct list_head ld_queue; /* Link descriptors queue */ | 134 | struct list_head ld_pending; /* Link descriptors queue */ |
135 | struct list_head ld_running; /* Link descriptors queue */ | ||
138 | struct dma_chan common; /* DMA common channel */ | 136 | struct dma_chan common; /* DMA common channel */ |
139 | struct dma_pool *desc_pool; /* Descriptors pool */ | 137 | struct dma_pool *desc_pool; /* Descriptors pool */ |
140 | struct device *dev; /* Channel device */ | 138 | struct device *dev; /* Channel device */ |
141 | struct resource reg; /* Resource for register */ | ||
142 | int irq; /* Channel IRQ */ | 139 | int irq; /* Channel IRQ */ |
143 | int id; /* Raw id of this channel */ | 140 | int id; /* Raw id of this channel */ |
144 | struct tasklet_struct tasklet; | 141 | struct tasklet_struct tasklet; |
145 | u32 feature; | 142 | u32 feature; |
146 | 143 | ||
147 | void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int enable); | 144 | void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable); |
148 | void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable); | 145 | void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable); |
149 | void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size); | 146 | void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size); |
150 | void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size); | 147 | void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size); |
151 | void (*set_request_count)(struct fsl_dma_chan *fsl_chan, int size); | 148 | void (*set_request_count)(struct fsldma_chan *fsl_chan, int size); |
152 | }; | 149 | }; |
153 | 150 | ||
154 | #define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common) | 151 | #define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common) |
155 | #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) | 152 | #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) |
156 | #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) | 153 | #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) |
157 | 154 | ||