1 files changed, 654 insertions, 523 deletions

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 296f9e747fac..bbb4be5a3ff4 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -37,19 +37,19 @@
 #include <asm/fsldma.h>
 #include "fsldma.h"
 
-static void dma_init(struct fsl_dma_chan *fsl_chan)
+static void dma_init(struct fsldma_chan *chan)
 {
         /* Reset the channel */
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
+        DMA_OUT(chan, &chan->regs->mr, 0, 32);
 
-        switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
+        switch (chan->feature & FSL_DMA_IP_MASK) {
         case FSL_DMA_IP_85XX:
                 /* Set the channel to below modes:
                  * EIE - Error interrupt enable
                  * EOSIE - End of segments interrupt enable (basic mode)
                  * EOLNIE - End of links interrupt enable
                  */
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
+                DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
                                 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
                 break;
         case FSL_DMA_IP_83XX:
@@ -57,170 +57,146 @@ static void dma_init(struct fsl_dma_chan *fsl_chan)
                  * EOTIE - End-of-transfer interrupt enable
                  * PRC_RM - PCI read multiple
                  */
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE
+                DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
                                 | FSL_DMA_MR_PRC_RM, 32);
                 break;
         }
-
 }
 
-static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
+static void set_sr(struct fsldma_chan *chan, u32 val)
 {
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
+        DMA_OUT(chan, &chan->regs->sr, val, 32);
 }
 
-static u32 get_sr(struct fsl_dma_chan *fsl_chan)
+static u32 get_sr(struct fsldma_chan *chan)
 {
-        return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
+        return DMA_IN(chan, &chan->regs->sr, 32);
 }
 
-static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
+static void set_desc_cnt(struct fsldma_chan *chan,
                                 struct fsl_dma_ld_hw *hw, u32 count)
 {
-        hw->count = CPU_TO_DMA(fsl_chan, count, 32);
+        hw->count = CPU_TO_DMA(chan, count, 32);
 }
 
-static void set_desc_src(struct fsl_dma_chan *fsl_chan,
+static void set_desc_src(struct fsldma_chan *chan,
                                 struct fsl_dma_ld_hw *hw, dma_addr_t src)
 {
         u64 snoop_bits;
 
-        snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+        snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
-        hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
+        hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
 }
 
-static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
-                                struct fsl_dma_ld_hw *hw, dma_addr_t dest)
+static void set_desc_dst(struct fsldma_chan *chan,
+                                struct fsl_dma_ld_hw *hw, dma_addr_t dst)
 {
         u64 snoop_bits;
 
-        snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+        snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
-        hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
+        hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
 }
 
-static void set_desc_next(struct fsl_dma_chan *fsl_chan,
+static void set_desc_next(struct fsldma_chan *chan,
                                 struct fsl_dma_ld_hw *hw, dma_addr_t next)
 {
         u64 snoop_bits;
 
-        snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
+        snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
                 ? FSL_DMA_SNEN : 0;
-        hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
-}
-
-static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
-{
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
+        hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
 }
 
-static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
+static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
 {
-        return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
+        DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
 }
 
-static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
+static dma_addr_t get_cdar(struct fsldma_chan *chan)
 {
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
+        return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
 }
 
-static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
+static dma_addr_t get_ndar(struct fsldma_chan *chan)
 {
-        return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
+        return DMA_IN(chan, &chan->regs->ndar, 64);
 }
 
-static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
+static u32 get_bcr(struct fsldma_chan *chan)
 {
-        return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
+        return DMA_IN(chan, &chan->regs->bcr, 32);
 }
 
-static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
+static int dma_is_idle(struct fsldma_chan *chan)
 {
-        u32 sr = get_sr(fsl_chan);
+        u32 sr = get_sr(chan);
         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 }
 
-static void dma_start(struct fsl_dma_chan *fsl_chan)
+static void dma_start(struct fsldma_chan *chan)
 {
-        u32 mr_set = 0;
-
-        if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
-                mr_set |= FSL_DMA_MR_EMP_EN;
-        } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
-                                & ~FSL_DMA_MR_EMP_EN, 32);
+        u32 mode;
+
+        mode = DMA_IN(chan, &chan->regs->mr, 32);
+
+        if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+                if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
+                        DMA_OUT(chan, &chan->regs->bcr, 0, 32);
+                        mode |= FSL_DMA_MR_EMP_EN;
+                } else {
+                        mode &= ~FSL_DMA_MR_EMP_EN;
+                }
         }
 
-        if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
-                mr_set |= FSL_DMA_MR_EMS_EN;
+        if (chan->feature & FSL_DMA_CHAN_START_EXT)
+                mode |= FSL_DMA_MR_EMS_EN;
         else
-                mr_set |= FSL_DMA_MR_CS;
+                mode |= FSL_DMA_MR_CS;
 
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
-                        | mr_set, 32);
+        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
-static void dma_halt(struct fsl_dma_chan *fsl_chan)
+static void dma_halt(struct fsldma_chan *chan)
 {
+        u32 mode;
         int i;
 
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
-                32);
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
-                | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
+        mode = DMA_IN(chan, &chan->regs->mr, 32);
+        mode |= FSL_DMA_MR_CA;
+        DMA_OUT(chan, &chan->regs->mr, mode, 32);
+
+        mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
+        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 
         for (i = 0; i < 100; i++) {
-                if (dma_is_idle(fsl_chan))
-                        break;
+                if (dma_is_idle(chan))
+                        return;
+
                 udelay(10);
         }
-        if (i >= 100 && !dma_is_idle(fsl_chan))
-                dev_err(fsl_chan->dev, "DMA halt timeout!\n");
+
+        if (!dma_is_idle(chan))
+                dev_err(chan->dev, "DMA halt timeout!\n");
 }
 
-static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
+static void set_ld_eol(struct fsldma_chan *chan,
                         struct fsl_desc_sw *desc)
 {
         u64 snoop_bits;
 
-        snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
+        snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
                 ? FSL_DMA_SNEN : 0;
 
-        desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
-                DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
+        desc->hw.next_ln_addr = CPU_TO_DMA(chan,
+                DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
                         | snoop_bits, 64);
 }
 
-static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
-                struct fsl_desc_sw *new_desc)
-{
-        struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
-
-        if (list_empty(&fsl_chan->ld_queue))
-                return;
-
-        /* Link to the new descriptor physical address and
-         * Enable End-of-segment interrupt for
-         * the last link descriptor.
-         * (the previous node's next link descriptor)
-         *
-         * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
-         */
-        queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
-                        new_desc->async_tx.phys | FSL_DMA_EOSIE |
-                        (((fsl_chan->feature & FSL_DMA_IP_MASK)
-                                == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
-}
-
 /**
  * fsl_chan_set_src_loop_size - Set source address hold transfer size
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  * @size     : Address loop size, 0 for disable loop
  *
  * The set source address hold transfer size. The source
@@ -229,29 +205,30 @@ static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
  * SA + 1 ... and so on.
  */
-static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
+static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
 {
+        u32 mode;
+
+        mode = DMA_IN(chan, &chan->regs->mr, 32);
+
         switch (size) {
         case 0:
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
-                        (~FSL_DMA_MR_SAHE), 32);
+                mode &= ~FSL_DMA_MR_SAHE;
                 break;
         case 1:
         case 2:
         case 4:
         case 8:
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
-                        FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
-                        32);
+                mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
                 break;
         }
+
+        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
 /**
- * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
- * @fsl_chan : Freescale DMA channel
+ * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
+ * @chan : Freescale DMA channel
  * @size     : Address loop size, 0 for disable loop
  *
  * The set destination address hold transfer size. The destination
@@ -260,29 +237,30 @@ static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
  * TA + 1 ... and so on.
  */
-static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
+static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
 {
+        u32 mode;
+
+        mode = DMA_IN(chan, &chan->regs->mr, 32);
+
         switch (size) {
         case 0:
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
-                        (~FSL_DMA_MR_DAHE), 32);
+                mode &= ~FSL_DMA_MR_DAHE;
                 break;
         case 1:
         case 2:
         case 4:
         case 8:
-                DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                        DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
-                        FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
-                        32);
+                mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
                 break;
         }
+
+        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
 /**
  * fsl_chan_set_request_count - Set DMA Request Count for external control
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  * @size     : Number of bytes to transfer in a single request
  *
  * The Freescale DMA channel can be controlled by the external signal DREQ#.
@@ -292,35 +270,38 @@ static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
  *
  * A size of 0 disables external pause control. The maximum size is 1024.
  */
-static void fsl_chan_set_request_count(struct fsl_dma_chan *fsl_chan, int size)
+static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
 {
+        u32 mode;
+
         BUG_ON(size > 1024);
-        DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
-                        | ((__ilog2(size) << 24) & 0x0f000000),
-                32);
+
+        mode = DMA_IN(chan, &chan->regs->mr, 32);
+        mode |= (__ilog2(size) << 24) & 0x0f000000;
+
+        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
 /**
  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  * @enable   : 0 is disabled, 1 is enabled.
  *
  * The Freescale DMA channel can be controlled by the external signal DREQ#.
  * The DMA Request Count feature should be used in addition to this feature
  * to set the number of bytes to transfer before pausing the channel.
  */
-static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int enable)
+static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
 {
         if (enable)
-                fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
+                chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
         else
-                fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
+                chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
 }
 
 /**
  * fsl_chan_toggle_ext_start - Toggle channel external start status
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  * @enable   : 0 is disabled, 1 is enabled.
  *
  * If enable the external start, the channel can be started by an
@@ -328,141 +309,196 @@ static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int enable)
  * transfer immediately. The DMA channel will wait for the
  * control pin asserted.
  */
-static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
+static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
 {
         if (enable)
-                fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
+                chan->feature |= FSL_DMA_CHAN_START_EXT;
         else
-                fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
+                chan->feature &= ~FSL_DMA_CHAN_START_EXT;
+}
+
+static void append_ld_queue(struct fsldma_chan *chan,
+                            struct fsl_desc_sw *desc)
+{
+        struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
+
+        if (list_empty(&chan->ld_pending))
+                goto out_splice;
+
+        /*
+         * Add the hardware descriptor to the chain of hardware descriptors
+         * that already exists in memory.
+         *
+         * This will un-set the EOL bit of the existing transaction, and the
+         * last link in this transaction will become the EOL descriptor.
+         */
+        set_desc_next(chan, &tail->hw, desc->async_tx.phys);
+
+        /*
+         * Add the software descriptor and all children to the list
+         * of pending transactions
+         */
+out_splice:
+        list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
 }
 
 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
-        struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
+        struct fsldma_chan *chan = to_fsl_chan(tx->chan);
         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
         struct fsl_desc_sw *child;
         unsigned long flags;
         dma_cookie_t cookie;
 
-        /* cookie increment and adding to ld_queue must be atomic */
-        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+        spin_lock_irqsave(&chan->desc_lock, flags);
 
-        cookie = fsl_chan->common.cookie;
+        /*
+         * assign cookies to all of the software descriptors
+         * that make up this transaction
+         */
+        cookie = chan->common.cookie;
         list_for_each_entry(child, &desc->tx_list, node) {
                 cookie++;
                 if (cookie < 0)
                         cookie = 1;
 
-                desc->async_tx.cookie = cookie;
+                child->async_tx.cookie = cookie;
         }
 
-        fsl_chan->common.cookie = cookie;
-        append_ld_queue(fsl_chan, desc);
-        list_splice_init(&desc->tx_list, fsl_chan->ld_queue.prev);
+        chan->common.cookie = cookie;
+
+        /* put this transaction onto the tail of the pending queue */
+        append_ld_queue(chan, desc);
 
-        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+        spin_unlock_irqrestore(&chan->desc_lock, flags);
 
         return cookie;
 }
 
 /**
  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  *
  * Return - The descriptor allocated. NULL for failed.
  */
 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
-                                        struct fsl_dma_chan *fsl_chan)
+                                        struct fsldma_chan *chan)
 {
+        struct fsl_desc_sw *desc;
         dma_addr_t pdesc;
-        struct fsl_desc_sw *desc_sw;
-
-        desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
-        if (desc_sw) {
-                memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
-                INIT_LIST_HEAD(&desc_sw->tx_list);
-                dma_async_tx_descriptor_init(&desc_sw->async_tx,
-                                                &fsl_chan->common);
-                desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
-                desc_sw->async_tx.phys = pdesc;
+
+        desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
+        if (!desc) {
+                dev_dbg(chan->dev, "out of memory for link desc\n");
+                return NULL;
         }
 
-        return desc_sw;
+        memset(desc, 0, sizeof(*desc));
+        INIT_LIST_HEAD(&desc->tx_list);
+        dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
+        desc->async_tx.tx_submit = fsl_dma_tx_submit;
+        desc->async_tx.phys = pdesc;
+
+        return desc;
 }
 
 
 /**
  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  *
  * This function will create a dma pool for descriptor allocation.
  *
  * Return - The number of descriptors allocated.
  */
-static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
+static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
 {
-        struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+        struct fsldma_chan *chan = to_fsl_chan(dchan);
 
         /* Has this channel already been allocated? */
-        if (fsl_chan->desc_pool)
+        if (chan->desc_pool)
                 return 1;
 
-        /* We need the descriptor to be aligned to 32bytes
+        /*
+         * We need the descriptor to be aligned to 32bytes
          * for meeting FSL DMA specification requirement.
          */
-        fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
-                        fsl_chan->dev, sizeof(struct fsl_desc_sw),
-                        32, 0);
-        if (!fsl_chan->desc_pool) {
-                dev_err(fsl_chan->dev, "No memory for channel %d "
-                        "descriptor dma pool.\n", fsl_chan->id);
-                return 0;
+        chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
+                                          chan->dev,
+                                          sizeof(struct fsl_desc_sw),
+                                          __alignof__(struct fsl_desc_sw), 0);
+        if (!chan->desc_pool) {
+                dev_err(chan->dev, "unable to allocate channel %d "
+                                   "descriptor pool\n", chan->id);
+                return -ENOMEM;
         }
 
+        /* there is at least one descriptor free to be allocated */
         return 1;
 }
 
 /**
- * fsl_dma_free_chan_resources - Free all resources of the channel.
- * @fsl_chan : Freescale DMA channel
+ * fsldma_free_desc_list - Free all descriptors in a queue
+ * @chan: Freescae DMA channel
+ * @list: the list to free
+ *
+ * LOCKING: must hold chan->desc_lock
  */
-static void fsl_dma_free_chan_resources(struct dma_chan *chan)
+static void fsldma_free_desc_list(struct fsldma_chan *chan,
+                                  struct list_head *list)
 {
-        struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
         struct fsl_desc_sw *desc, *_desc;
-        unsigned long flags;
 
-        dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
-        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
-        list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
-#ifdef FSL_DMA_LD_DEBUG
-                dev_dbg(fsl_chan->dev,
-                                "LD %p will be released.\n", desc);
-#endif
+        list_for_each_entry_safe(desc, _desc, list, node) {
+                list_del(&desc->node);
+                dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+        }
+}
+
+static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
+                                          struct list_head *list)
+{
+        struct fsl_desc_sw *desc, *_desc;
+
+        list_for_each_entry_safe_reverse(desc, _desc, list, node) {
                 list_del(&desc->node);
-                /* free link descriptor */
-                dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
+                dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
         }
-        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-        dma_pool_destroy(fsl_chan->desc_pool);
+}
+
+/**
+ * fsl_dma_free_chan_resources - Free all resources of the channel.
+ * @chan : Freescale DMA channel
+ */
+static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
+{
+        struct fsldma_chan *chan = to_fsl_chan(dchan);
+        unsigned long flags;
+
+        dev_dbg(chan->dev, "Free all channel resources.\n");
+        spin_lock_irqsave(&chan->desc_lock, flags);
+        fsldma_free_desc_list(chan, &chan->ld_pending);
+        fsldma_free_desc_list(chan, &chan->ld_running);
+        spin_unlock_irqrestore(&chan->desc_lock, flags);
 
-        fsl_chan->desc_pool = NULL;
+        dma_pool_destroy(chan->desc_pool);
+        chan->desc_pool = NULL;
 }
 
 static struct dma_async_tx_descriptor *
-fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
+fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
 {
-        struct fsl_dma_chan *fsl_chan;
+        struct fsldma_chan *chan;
         struct fsl_desc_sw *new;
 
-        if (!chan)
+        if (!dchan)
                 return NULL;
 
-        fsl_chan = to_fsl_chan(chan);
+        chan = to_fsl_chan(dchan);
 
-        new = fsl_dma_alloc_descriptor(fsl_chan);
+        new = fsl_dma_alloc_descriptor(chan);
         if (!new) {
-                dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
+                dev_err(chan->dev, "No free memory for link descriptor\n");
                 return NULL;
         }
 
@@ -473,51 +509,50 @@ fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
         list_add_tail(&new->node, &new->tx_list);
 
         /* Set End-of-link to the last link descriptor of new list*/
-        set_ld_eol(fsl_chan, new);
+        set_ld_eol(chan, new);
 
         return &new->async_tx;
 }
 
 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
-        struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
+        struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
         size_t len, unsigned long flags)
 {
-        struct fsl_dma_chan *fsl_chan;
+        struct fsldma_chan *chan;
         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
-        struct list_head *list;
         size_t copy;
 
-        if (!chan)
+        if (!dchan)
                 return NULL;
 
         if (!len)
                 return NULL;
 
-        fsl_chan = to_fsl_chan(chan);
+        chan = to_fsl_chan(dchan);
 
         do {
 
                 /* Allocate the link descriptor from DMA pool */
-                new = fsl_dma_alloc_descriptor(fsl_chan);
+                new = fsl_dma_alloc_descriptor(chan);
                 if (!new) {
-                        dev_err(fsl_chan->dev,
+                        dev_err(chan->dev,
                                         "No free memory for link descriptor\n");
                         goto fail;
                 }
 #ifdef FSL_DMA_LD_DEBUG
-                dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
+                dev_dbg(chan->dev, "new link desc alloc %p\n", new);
 #endif
 
                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 
-                set_desc_cnt(fsl_chan, &new->hw, copy);
-                set_desc_src(fsl_chan, &new->hw, dma_src);
-                set_desc_dest(fsl_chan, &new->hw, dma_dest);
+                set_desc_cnt(chan, &new->hw, copy);
+                set_desc_src(chan, &new->hw, dma_src);
+                set_desc_dst(chan, &new->hw, dma_dst);
 
                 if (!first)
                         first = new;
                 else
-                        set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
+                        set_desc_next(chan, &prev->hw, new->async_tx.phys);
 
                 new->async_tx.cookie = 0;
                 async_tx_ack(&new->async_tx);
@@ -525,7 +560,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
                 prev = new;
                 len -= copy;
                 dma_src += copy;
-                dma_dest += copy;
+                dma_dst += copy;
 
                 /* Insert the link descriptor to the LD ring */
                 list_add_tail(&new->node, &first->tx_list);
@@ -535,7 +570,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
         new->async_tx.cookie = -EBUSY;
 
         /* Set End-of-link to the last link descriptor of new list*/
-        set_ld_eol(fsl_chan, new);
+        set_ld_eol(chan, new);
 
         return &first->async_tx;
 
@@ -543,12 +578,7 @@ fail:
         if (!first)
                 return NULL;
 
-        list = &first->tx_list;
-        list_for_each_entry_safe_reverse(new, prev, list, node) {
-                list_del(&new->node);
-                dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
-        }
-
+        fsldma_free_desc_list_reverse(chan, &first->tx_list);
         return NULL;
 }
 
@@ -565,13 +595,12 @@ fail:
  * chan->private variable.
  */
 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
-        struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
+        struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
         enum dma_data_direction direction, unsigned long flags)
 {
-        struct fsl_dma_chan *fsl_chan;
+        struct fsldma_chan *chan;
         struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
         struct fsl_dma_slave *slave;
-        struct list_head *tx_list;
         size_t copy;
 
         int i;
@@ -581,14 +610,14 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
         struct fsl_dma_hw_addr *hw;
         dma_addr_t dma_dst, dma_src;
 
-        if (!chan)
+        if (!dchan)
                 return NULL;
 
-        if (!chan->private)
+        if (!dchan->private)
                 return NULL;
 
-        fsl_chan = to_fsl_chan(chan);
-        slave = chan->private;
+        chan = to_fsl_chan(dchan);
+        slave = dchan->private;
 
         if (list_empty(&slave->addresses))
                 return NULL;
@@ -637,14 +666,14 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
                         }
 
                         /* Allocate the link descriptor from DMA pool */
-                        new = fsl_dma_alloc_descriptor(fsl_chan);
+                        new = fsl_dma_alloc_descriptor(chan);
                         if (!new) {
-                                dev_err(fsl_chan->dev, "No free memory for "
+                                dev_err(chan->dev, "No free memory for "
                                                        "link descriptor\n");
                                 goto fail;
                         }
 #ifdef FSL_DMA_LD_DEBUG
-                        dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
+                        dev_dbg(chan->dev, "new link desc alloc %p\n", new);
 #endif
 
                         /*
@@ -671,9 +700,9 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
                         }
 
                         /* Fill in the descriptor */
-                        set_desc_cnt(fsl_chan, &new->hw, copy);
-                        set_desc_src(fsl_chan, &new->hw, dma_src);
-                        set_desc_dest(fsl_chan, &new->hw, dma_dst);
+                        set_desc_cnt(chan, &new->hw, copy);
+                        set_desc_src(chan, &new->hw, dma_src);
+                        set_desc_dst(chan, &new->hw, dma_dst);
 
                         /*
                          * If this is not the first descriptor, chain the
@@ -682,7 +711,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
                         if (!first) {
                                 first = new;
                         } else {
-                                set_desc_next(fsl_chan, &prev->hw,
+                                set_desc_next(chan, &prev->hw,
                                               new->async_tx.phys);
                         }
 
@@ -708,23 +737,23 @@ finished:
         new->async_tx.cookie = -EBUSY;
 
         /* Set End-of-link to the last link descriptor of new list */
-        set_ld_eol(fsl_chan, new);
+        set_ld_eol(chan, new);
 
         /* Enable extra controller features */
-        if (fsl_chan->set_src_loop_size)
-                fsl_chan->set_src_loop_size(fsl_chan, slave->src_loop_size);
+        if (chan->set_src_loop_size)
+                chan->set_src_loop_size(chan, slave->src_loop_size);
 
-        if (fsl_chan->set_dest_loop_size)
-                fsl_chan->set_dest_loop_size(fsl_chan, slave->dst_loop_size);
+        if (chan->set_dst_loop_size)
+                chan->set_dst_loop_size(chan, slave->dst_loop_size);
 
-        if (fsl_chan->toggle_ext_start)
-                fsl_chan->toggle_ext_start(fsl_chan, slave->external_start);
+        if (chan->toggle_ext_start)
+                chan->toggle_ext_start(chan, slave->external_start);
 
-        if (fsl_chan->toggle_ext_pause)
-                fsl_chan->toggle_ext_pause(fsl_chan, slave->external_pause);
+        if (chan->toggle_ext_pause)
+                chan->toggle_ext_pause(chan, slave->external_pause);
 
-        if (fsl_chan->set_request_count)
-                fsl_chan->set_request_count(fsl_chan, slave->request_count);
+        if (chan->set_request_count)
+                chan->set_request_count(chan, slave->request_count);
 
         return &first->async_tx;
 
@@ -741,215 +770,216 @@ fail:
          *
          * We're re-using variables for the loop, oh well
          */
-        tx_list = &first->tx_list;
-        list_for_each_entry_safe_reverse(new, prev, tx_list, node) {
-                list_del_init(&new->node);
-                dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
-        }
-
+        fsldma_free_desc_list_reverse(chan, &first->tx_list);
         return NULL;
 }
 
-static void fsl_dma_device_terminate_all(struct dma_chan *chan)
+static void fsl_dma_device_terminate_all(struct dma_chan *dchan)
 {
-        struct fsl_dma_chan *fsl_chan;
-        struct fsl_desc_sw *desc, *tmp;
+        struct fsldma_chan *chan;
         unsigned long flags;
 
-        if (!chan)
+        if (!dchan)
                 return;
 
-        fsl_chan = to_fsl_chan(chan);
+        chan = to_fsl_chan(dchan);
 
         /* Halt the DMA engine */
-        dma_halt(fsl_chan);
+        dma_halt(chan);
 
-        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+        spin_lock_irqsave(&chan->desc_lock, flags);
 
         /* Remove and free all of the descriptors in the LD queue */
-        list_for_each_entry_safe(desc, tmp, &fsl_chan->ld_queue, node) {
-                list_del(&desc->node);
-                dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
-        }
+        fsldma_free_desc_list(chan, &chan->ld_pending);
+        fsldma_free_desc_list(chan, &chan->ld_running);
 
-        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+        spin_unlock_irqrestore(&chan->desc_lock, flags);
 }
 
 /**
  * fsl_dma_update_completed_cookie - Update the completed cookie.
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
+ *
+ * CONTEXT: hardirq
  */
-static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
+static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
 {
-        struct fsl_desc_sw *cur_desc, *desc;
-        dma_addr_t ld_phy;
+        struct fsl_desc_sw *desc;
+        unsigned long flags;
+        dma_cookie_t cookie;
 
-        ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
+        spin_lock_irqsave(&chan->desc_lock, flags);
 
-        if (ld_phy) {
-                cur_desc = NULL;
-                list_for_each_entry(desc, &fsl_chan->ld_queue, node)
-                        if (desc->async_tx.phys == ld_phy) {
-                                cur_desc = desc;
-                                break;
-                        }
+        if (list_empty(&chan->ld_running)) {
+                dev_dbg(chan->dev, "no running descriptors\n");
+                goto out_unlock;
+        }
 
-                if (cur_desc && cur_desc->async_tx.cookie) {
-                        if (dma_is_idle(fsl_chan))
-                                fsl_chan->completed_cookie =
-                                        cur_desc->async_tx.cookie;
-                        else
-                                fsl_chan->completed_cookie =
-                                        cur_desc->async_tx.cookie - 1;
-                }
+        /* Get the last descriptor, update the cookie to that */
+        desc = to_fsl_desc(chan->ld_running.prev);
+        if (dma_is_idle(chan))
+                cookie = desc->async_tx.cookie;
+        else {
+                cookie = desc->async_tx.cookie - 1;
+                if (unlikely(cookie < DMA_MIN_COOKIE))
+                        cookie = DMA_MAX_COOKIE;
         }
+
+        chan->completed_cookie = cookie;
+
+out_unlock:
+        spin_unlock_irqrestore(&chan->desc_lock, flags);
+}
+
+/**
+ * fsldma_desc_status - Check the status of a descriptor
+ * @chan: Freescale DMA channel
+ * @desc: DMA SW descriptor
+ *
+ * This function will return the status of the given descriptor
+ */
+static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
+                                          struct fsl_desc_sw *desc)
+{
+        return dma_async_is_complete(desc->async_tx.cookie,
+                                     chan->completed_cookie,
+                                     chan->common.cookie);
 }
 
 /**
  * fsl_chan_ld_cleanup - Clean up link descriptors
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  *
  * This function clean up the ld_queue of DMA channel.
- * If 'in_intr' is set, the function will move the link descriptor to
- * the recycle list. Otherwise, free it directly.
  */
-static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
+static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
 {
         struct fsl_desc_sw *desc, *_desc;
         unsigned long flags;
 
-        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+        spin_lock_irqsave(&chan->desc_lock, flags);
 
-        dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
-                        fsl_chan->completed_cookie);
-        list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
+        dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
+        list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
                 dma_async_tx_callback callback;
                 void *callback_param;
 
-                if (dma_async_is_complete(desc->async_tx.cookie,
-                            fsl_chan->completed_cookie, fsl_chan->common.cookie)
-                                == DMA_IN_PROGRESS)
+                if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
                         break;
 
-                callback = desc->async_tx.callback;
-                callback_param = desc->async_tx.callback_param;
-
-                /* Remove from ld_queue list */
+                /* Remove from the list of running transactions */
                 list_del(&desc->node);
 
-                dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
-                                desc);
-                dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
-
                 /* Run the link descriptor callback function */
+                callback = desc->async_tx.callback;
+                callback_param = desc->async_tx.callback_param;
                 if (callback) {
-                        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-                        dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
-                                        desc);
+                        spin_unlock_irqrestore(&chan->desc_lock, flags);
+                        dev_dbg(chan->dev, "LD %p callback\n", desc);
                         callback(callback_param);
-                        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+                        spin_lock_irqsave(&chan->desc_lock, flags);
                 }
+
+                /* Run any dependencies, then free the descriptor */
+                dma_run_dependencies(&desc->async_tx);
+                dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
         }
-        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+
+        spin_unlock_irqrestore(&chan->desc_lock, flags);
 }
 
 /**
- * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
- * @fsl_chan : Freescale DMA channel
+ * fsl_chan_xfer_ld_queue - transfer any pending transactions
+ * @chan : Freescale DMA channel
+ *
+ * This will make sure that any pending transactions will be run.
+ * If the DMA controller is idle, it will be started. Otherwise,
+ * the DMA controller's interrupt handler will start any pending
+ * transactions when it becomes idle.
  */
-static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
+static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
 {
-        struct list_head *ld_node;
-        dma_addr_t next_dest_addr;
+        struct fsl_desc_sw *desc;
         unsigned long flags;
 
-        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+        spin_lock_irqsave(&chan->desc_lock, flags);
 
-        if (!dma_is_idle(fsl_chan))
+        /*
+         * If the list of pending descriptors is empty, then we
+         * don't need to do any work at all
+         */
+        if (list_empty(&chan->ld_pending)) {
+                dev_dbg(chan->dev, "no pending LDs\n");
                 goto out_unlock;
+        }
 
-        dma_halt(fsl_chan);
+        /*
+         * The DMA controller is not idle, which means the interrupt
+         * handler will start any queued transactions when it runs
+         * at the end of the current transaction
+         */
+        if (!dma_is_idle(chan)) {
+                dev_dbg(chan->dev, "DMA controller still busy\n");
+                goto out_unlock;
+        }
 
-        /* If there are some link descriptors
-         * not transfered in queue. We need to start it.
+        /*
+         * TODO:
+         * make sure the dma_halt() function really un-wedges the
+         * controller as much as possible
          */
+        dma_halt(chan);
 
-        /* Find the first un-transfer desciptor */
-        for (ld_node = fsl_chan->ld_queue.next;
-                (ld_node != &fsl_chan->ld_queue)
-                        && (dma_async_is_complete(
-                                to_fsl_desc(ld_node)->async_tx.cookie,
-                                fsl_chan->completed_cookie,
-                                fsl_chan->common.cookie) == DMA_SUCCESS);
-                ld_node = ld_node->next);
-
-        if (ld_node != &fsl_chan->ld_queue) {
-                /* Get the ld start address from ld_queue */
-                next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
-                dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
-                                (unsigned long long)next_dest_addr);
-                set_cdar(fsl_chan, next_dest_addr);
-                dma_start(fsl_chan);
-        } else {
-                set_cdar(fsl_chan, 0);
-                set_ndar(fsl_chan, 0);
-        }
+        /*
+         * If there are some link descriptors which have not been
+         * transferred, we need to start the controller
+         */
+
+        /*
+         * Move all elements from the queue of pending transactions
+         * onto the list of running transactions
+         */
+        desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
+        list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
+
+        /*
+         * Program the descriptor's address into the DMA controller,
+         * then start the DMA transaction
+         */
+        set_cdar(chan, desc->async_tx.phys);
+        dma_start(chan);
 
 out_unlock:
-        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+        spin_unlock_irqrestore(&chan->desc_lock, flags);
 }
 
 /**
  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  */
-static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
+static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
 {
-        struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
-
-#ifdef FSL_DMA_LD_DEBUG
-        struct fsl_desc_sw *ld;
-        unsigned long flags;
-
-        spin_lock_irqsave(&fsl_chan->desc_lock, flags);
-        if (list_empty(&fsl_chan->ld_queue)) {
-                spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-                return;
-        }
-
-        dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
-        list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
-                int i;
-                dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
-                                fsl_chan->id, ld->async_tx.phys);
-                for (i = 0; i < 8; i++)
-                        dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
-                                        i, *(((u32 *)&ld->hw) + i));
-        }
-        dev_dbg(fsl_chan->dev, "----------------\n");
-        spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-#endif
-
-        fsl_chan_xfer_ld_queue(fsl_chan);
+        struct fsldma_chan *chan = to_fsl_chan(dchan);
+        fsl_chan_xfer_ld_queue(chan);
 }
 
 /**
  * fsl_dma_is_complete - Determine the DMA status
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  */
-static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
+static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan,
                                         dma_cookie_t cookie,
                                         dma_cookie_t *done,
                                         dma_cookie_t *used)
 {
-        struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+        struct fsldma_chan *chan = to_fsl_chan(dchan);
         dma_cookie_t last_used;
         dma_cookie_t last_complete;
 
-        fsl_chan_ld_cleanup(fsl_chan);
+        fsl_chan_ld_cleanup(chan);
 
-        last_used = chan->cookie;
-        last_complete = fsl_chan->completed_cookie;
+        last_used = dchan->cookie;
+        last_complete = chan->completed_cookie;
 
         if (done)
                 *done = last_complete;
@@ -960,32 +990,37 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
         return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
-static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
+/*----------------------------------------------------------------------------*/
+/* Interrupt Handling                                                         */
+/*----------------------------------------------------------------------------*/
+
+static irqreturn_t fsldma_chan_irq(int irq, void *data)
 {
-        struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
-        u32 stat;
+        struct fsldma_chan *chan = data;
         int update_cookie = 0;
         int xfer_ld_q = 0;
+        u32 stat;
 
-        stat = get_sr(fsl_chan);
-        dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
-                                                fsl_chan->id, stat);
-        set_sr(fsl_chan, stat);         /* Clear the event register */
+        /* save and clear the status register */
+        stat = get_sr(chan);
+        set_sr(chan, stat);
+        dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
 
         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
         if (!stat)
                 return IRQ_NONE;
 
         if (stat & FSL_DMA_SR_TE)
-                dev_err(fsl_chan->dev, "Transfer Error!\n");
+                dev_err(chan->dev, "Transfer Error!\n");
 
-        /* Programming Error
+        /*
+         * Programming Error
          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
          * triger a PE interrupt.
          */
         if (stat & FSL_DMA_SR_PE) {
-                dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
-                if (get_bcr(fsl_chan) == 0) {
+                dev_dbg(chan->dev, "irq: Programming Error INT\n");
+                if (get_bcr(chan) == 0) {
                         /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
                          * Now, update the completed cookie, and continue the
                          * next uncompleted transfer.
@@ -996,208 +1031,296 @@ static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
                 stat &= ~FSL_DMA_SR_PE;
         }
 
-        /* If the link descriptor segment transfer finishes,
+        /*
+         * If the link descriptor segment transfer finishes,
          * we will recycle the used descriptor.
          */
         if (stat & FSL_DMA_SR_EOSI) {
-                dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
-                dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
-                        (unsigned long long)get_cdar(fsl_chan),
-                        (unsigned long long)get_ndar(fsl_chan));
+                dev_dbg(chan->dev, "irq: End-of-segments INT\n");
+                dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
+                        (unsigned long long)get_cdar(chan),
+                        (unsigned long long)get_ndar(chan));
                 stat &= ~FSL_DMA_SR_EOSI;
                 update_cookie = 1;
         }
 
-        /* For MPC8349, EOCDI event need to update cookie
+        /*
+         * For MPC8349, EOCDI event need to update cookie
          * and start the next transfer if it exist.
          */
         if (stat & FSL_DMA_SR_EOCDI) {
-                dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
+                dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
                 stat &= ~FSL_DMA_SR_EOCDI;
                 update_cookie = 1;
                 xfer_ld_q = 1;
         }
 
-        /* If it current transfer is the end-of-transfer,
+        /*
+         * If it current transfer is the end-of-transfer,
          * we should clear the Channel Start bit for
          * prepare next transfer.
          */
         if (stat & FSL_DMA_SR_EOLNI) {
-                dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
+                dev_dbg(chan->dev, "irq: End-of-link INT\n");
                 stat &= ~FSL_DMA_SR_EOLNI;
                 xfer_ld_q = 1;
         }
 
         if (update_cookie)
-                fsl_dma_update_completed_cookie(fsl_chan);
+                fsl_dma_update_completed_cookie(chan);
         if (xfer_ld_q)
-                fsl_chan_xfer_ld_queue(fsl_chan);
+                fsl_chan_xfer_ld_queue(chan);
         if (stat)
-                dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
-                                        stat);
+                dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
 
-        dev_dbg(fsl_chan->dev, "event: Exit\n");
-        tasklet_schedule(&fsl_chan->tasklet);
+        dev_dbg(chan->dev, "irq: Exit\n");
+        tasklet_schedule(&chan->tasklet);
         return IRQ_HANDLED;
 }
 
-static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
+static void dma_do_tasklet(unsigned long data)
 {
-        struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
-        u32 gsr;
-        int ch_nr;
+        struct fsldma_chan *chan = (struct fsldma_chan *)data;
+        fsl_chan_ld_cleanup(chan);
+}
+
+static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
+{
+        struct fsldma_device *fdev = data;
+        struct fsldma_chan *chan;
+        unsigned int handled = 0;
+        u32 gsr, mask;
+        int i;
 
-        gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
-                        : in_le32(fdev->reg_base);
-        ch_nr = (32 - ffs(gsr)) / 8;
+        gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
+                                                   : in_le32(fdev->regs);
+        mask = 0xff000000;
+        dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
+
+        for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+                chan = fdev->chan[i];
+                if (!chan)
+                        continue;
+
+                if (gsr & mask) {
+                        dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
+                        fsldma_chan_irq(irq, chan);
+                        handled++;
+                }
 
-        return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
-                        fdev->chan[ch_nr]) : IRQ_NONE;
+                gsr &= ~mask;
+                mask >>= 8;
+        }
+
+        return IRQ_RETVAL(handled);
 }
 
-static void dma_do_tasklet(unsigned long data)
+static void fsldma_free_irqs(struct fsldma_device *fdev)
 {
-        struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
-        fsl_chan_ld_cleanup(fsl_chan);
+        struct fsldma_chan *chan;
+        int i;
+
+        if (fdev->irq != NO_IRQ) {
+                dev_dbg(fdev->dev, "free per-controller IRQ\n");
+                free_irq(fdev->irq, fdev);
+                return;
+        }
+
+        for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+                chan = fdev->chan[i];
+                if (chan && chan->irq != NO_IRQ) {
+                        dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
+                        free_irq(chan->irq, chan);
+                }
+        }
 }
 
-static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
+static int fsldma_request_irqs(struct fsldma_device *fdev)
+{
+        struct fsldma_chan *chan;
+        int ret;
+        int i;
+
+        /* if we have a per-controller IRQ, use that */
+        if (fdev->irq != NO_IRQ) {
+                dev_dbg(fdev->dev, "request per-controller IRQ\n");
+                ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
+                                  "fsldma-controller", fdev);
+                return ret;
+        }
+
+        /* no per-controller IRQ, use the per-channel IRQs */
+        for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+                chan = fdev->chan[i];
+                if (!chan)
+                        continue;
+
+                if (chan->irq == NO_IRQ) {
+                        dev_err(fdev->dev, "no interrupts property defined for "
+                                           "DMA channel %d. Please fix your "
+                                           "device tree\n", chan->id);
+                        ret = -ENODEV;
+                        goto out_unwind;
+                }
+
+                dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
+                ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
+                                  "fsldma-chan", chan);
+                if (ret) {
+                        dev_err(fdev->dev, "unable to request IRQ for DMA "
+                                           "channel %d\n", chan->id);
+                        goto out_unwind;
+                }
+        }
+
+        return 0;
+
+out_unwind:
+        for (/* none */; i >= 0; i--) {
+                chan = fdev->chan[i];
+                if (!chan)
+                        continue;
+
+                if (chan->irq == NO_IRQ)
+                        continue;
+
+                free_irq(chan->irq, chan);
+        }
+
+        return ret;
+}
+
+/*----------------------------------------------------------------------------*/
+/* OpenFirmware Subsystem                                                     */
+/*----------------------------------------------------------------------------*/
+
+static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
         struct device_node *node, u32 feature, const char *compatible)
 {
-        struct fsl_dma_chan *new_fsl_chan;
+        struct fsldma_chan *chan;
+        struct resource res;
         int err;
 
         /* alloc channel */
-        new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
-        if (!new_fsl_chan) {
-                dev_err(fdev->dev, "No free memory for allocating "
-                                "dma channels!\n");
-                return -ENOMEM;
+        chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+        if (!chan) {
+                dev_err(fdev->dev, "no free memory for DMA channels!\n");
+                err = -ENOMEM;
+                goto out_return;
         }
 
-        /* get dma channel register base */
-        err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
-        if (err) {
-                dev_err(fdev->dev, "Can't get %s property 'reg'\n",
-                                node->full_name);
-                goto err_no_reg;
+        /* ioremap registers for use */
+        chan->regs = of_iomap(node, 0);
+        if (!chan->regs) {
+                dev_err(fdev->dev, "unable to ioremap registers\n");
+                err = -ENOMEM;
+                goto out_free_chan;
         }
 
-        new_fsl_chan->feature = feature;
+        err = of_address_to_resource(node, 0, &res);
+        if (err) {
+                dev_err(fdev->dev, "unable to find 'reg' property\n");
+                goto out_iounmap_regs;
+        }
 
+        chan->feature = feature;
         if (!fdev->feature)
-                fdev->feature = new_fsl_chan->feature;
+                fdev->feature = chan->feature;
 
-        /* If the DMA device's feature is different than its channels',
-         * report the bug.
+        /*
+         * If the DMA device's feature is different than the feature
+         * of its channels, report the bug
          */
-        WARN_ON(fdev->feature != new_fsl_chan->feature);
+        WARN_ON(fdev->feature != chan->feature);
 
-        new_fsl_chan->dev = fdev->dev;
-        new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
-                        new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
-
-        new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
-        if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
-                dev_err(fdev->dev, "There is no %d channel!\n",
-                                new_fsl_chan->id);
+        chan->dev = fdev->dev;
+        chan->id = ((res.start - 0x100) & 0xfff) >> 7;
+        if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
+                dev_err(fdev->dev, "too many channels for device\n");
                 err = -EINVAL;
-                goto err_no_chan;
+                goto out_iounmap_regs;
         }
-        fdev->chan[new_fsl_chan->id] = new_fsl_chan;
-        tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
-                        (unsigned long)new_fsl_chan);
 
-        /* Init the channel */
-        dma_init(new_fsl_chan);
+        fdev->chan[chan->id] = chan;
+        tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+
+        /* Initialize the channel */
+        dma_init(chan);
 
         /* Clear cdar registers */
-        set_cdar(new_fsl_chan, 0);
+        set_cdar(chan, 0);
 
-        switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
+        switch (chan->feature & FSL_DMA_IP_MASK) {
         case FSL_DMA_IP_85XX:
-                new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
+                chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
         case FSL_DMA_IP_83XX:
-                new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
-                new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
-                new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
-                new_fsl_chan->set_request_count = fsl_chan_set_request_count;
+                chan->toggle_ext_start = fsl_chan_toggle_ext_start;
+                chan->set_src_loop_size = fsl_chan_set_src_loop_size;
+                chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
+                chan->set_request_count = fsl_chan_set_request_count;
         }
 
-        spin_lock_init(&new_fsl_chan->desc_lock);
-        INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
+        spin_lock_init(&chan->desc_lock);
+        INIT_LIST_HEAD(&chan->ld_pending);
+        INIT_LIST_HEAD(&chan->ld_running);
+
+        chan->common.device = &fdev->common;
 
-        new_fsl_chan->common.device = &fdev->common;
+        /* find the IRQ line, if it exists in the device tree */
+        chan->irq = irq_of_parse_and_map(node, 0);
 
         /* Add the channel to DMA device channel list */
-        list_add_tail(&new_fsl_chan->common.device_node,
-                        &fdev->common.channels);
+        list_add_tail(&chan->common.device_node, &fdev->common.channels);
         fdev->common.chancnt++;
 
-        new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
-        if (new_fsl_chan->irq != NO_IRQ) {
-                err = request_irq(new_fsl_chan->irq,
-                                        &fsl_dma_chan_do_interrupt, IRQF_SHARED,
-                                        "fsldma-channel", new_fsl_chan);
-                if (err) {
-                        dev_err(fdev->dev, "DMA channel %s request_irq error "
-                                "with return %d\n", node->full_name, err);
-                        goto err_no_irq;
-                }
-        }
-
-        dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
-                 compatible,
-                 new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
+        dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
+                 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
 
         return 0;
 
-err_no_irq:
-        list_del(&new_fsl_chan->common.device_node);
-err_no_chan:
-        iounmap(new_fsl_chan->reg_base);
-err_no_reg:
-        kfree(new_fsl_chan);
+out_iounmap_regs:
+        iounmap(chan->regs);
+out_free_chan:
+        kfree(chan);
+out_return:
         return err;
 }
 
-static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
+static void fsl_dma_chan_remove(struct fsldma_chan *chan)
 {
-        if (fchan->irq != NO_IRQ)
-                free_irq(fchan->irq, fchan);
-        list_del(&fchan->common.device_node);
-        iounmap(fchan->reg_base);
-        kfree(fchan);
+        irq_dispose_mapping(chan->irq);
+        list_del(&chan->common.device_node);
+        iounmap(chan->regs);
+        kfree(chan);
 }
 
-static int __devinit of_fsl_dma_probe(struct of_device *dev,
+static int __devinit fsldma_of_probe(struct of_device *op,
                         const struct of_device_id *match)
 {
-        int err;
-        struct fsl_dma_device *fdev;
+        struct fsldma_device *fdev;
         struct device_node *child;
+        int err;
 
-        fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
+        fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
         if (!fdev) {
-                dev_err(&dev->dev, "No enough memory for 'priv'\n");
-                return -ENOMEM;
+                dev_err(&op->dev, "No enough memory for 'priv'\n");
+                err = -ENOMEM;
+                goto out_return;
         }
-        fdev->dev = &dev->dev;
+
+        fdev->dev = &op->dev;
         INIT_LIST_HEAD(&fdev->common.channels);
 
-        /* get DMA controller register base */
-        err = of_address_to_resource(dev->node, 0, &fdev->reg);
-        if (err) {
-                dev_err(&dev->dev, "Can't get %s property 'reg'\n",
-                                dev->node->full_name);
-                goto err_no_reg;
+        /* ioremap the registers for use */
+        fdev->regs = of_iomap(op->node, 0);
+        if (!fdev->regs) {
+                dev_err(&op->dev, "unable to ioremap registers\n");
+                err = -ENOMEM;
+                goto out_free_fdev;
         }
 
-        dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
-                        "controller at 0x%llx...\n",
-                        match->compatible, (unsigned long long)fdev->reg.start);
-        fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
-                                                - fdev->reg.start + 1);
+        /* map the channel IRQ if it exists, but don't hookup the handler yet */
+        fdev->irq = irq_of_parse_and_map(op->node, 0);
 
         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
         dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
@@ -1210,103 +1333,111 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev,
         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
         fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
         fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
-        fdev->common.dev = &dev->dev;
+        fdev->common.dev = &op->dev;
 
-        fdev->irq = irq_of_parse_and_map(dev->node, 0);
-        if (fdev->irq != NO_IRQ) {
-                err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
-                                        "fsldma-device", fdev);
-                if (err) {
-                        dev_err(&dev->dev, "DMA device request_irq error "
-                                "with return %d\n", err);
-                        goto err;
-                }
-        }
-
-        dev_set_drvdata(&(dev->dev), fdev);
+        dev_set_drvdata(&op->dev, fdev);
 
-        /* We cannot use of_platform_bus_probe() because there is no
-         * of_platform_bus_remove.  Instead, we manually instantiate every DMA
+        /*
+         * We cannot use of_platform_bus_probe() because there is no
+         * of_platform_bus_remove(). Instead, we manually instantiate every DMA
          * channel object.
          */
-        for_each_child_of_node(dev->node, child) {
-                if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
+        for_each_child_of_node(op->node, child) {
+                if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
                         fsl_dma_chan_probe(fdev, child,
                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
                                 "fsl,eloplus-dma-channel");
-                if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
+                }
+
+                if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
                         fsl_dma_chan_probe(fdev, child,
                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
                                 "fsl,elo-dma-channel");
+                }
+        }
+
+        /*
+         * Hookup the IRQ handler(s)
+         *
+         * If we have a per-controller interrupt, we prefer that to the
+         * per-channel interrupts to reduce the number of shared interrupt
+         * handlers on the same IRQ line
+         */
+        err = fsldma_request_irqs(fdev);
+        if (err) {
+                dev_err(fdev->dev, "unable to request IRQs\n");
+                goto out_free_fdev;
         }
 
         dma_async_device_register(&fdev->common);
         return 0;
 
-err:
-        iounmap(fdev->reg_base);
-err_no_reg:
+out_free_fdev:
+        irq_dispose_mapping(fdev->irq);
         kfree(fdev);
+out_return:
         return err;
 }
 
-static int of_fsl_dma_remove(struct of_device *of_dev)
+static int fsldma_of_remove(struct of_device *op)
 {
-        struct fsl_dma_device *fdev;
+        struct fsldma_device *fdev;
         unsigned int i;
 
-        fdev = dev_get_drvdata(&of_dev->dev);
-
+        fdev = dev_get_drvdata(&op->dev);
         dma_async_device_unregister(&fdev->common);
 
-        for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
+        fsldma_free_irqs(fdev);
+
+        for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
                 if (fdev->chan[i])
                         fsl_dma_chan_remove(fdev->chan[i]);
+        }
 
-        if (fdev->irq != NO_IRQ)
-                free_irq(fdev->irq, fdev);
-
-        iounmap(fdev->reg_base);
-
+        iounmap(fdev->regs);
+        dev_set_drvdata(&op->dev, NULL);
         kfree(fdev);
-        dev_set_drvdata(&of_dev->dev, NULL);
 
         return 0;
 }
 
-static struct of_device_id of_fsl_dma_ids[] = {
+static const struct of_device_id fsldma_of_ids[] = {
         { .compatible = "fsl,eloplus-dma", },
         { .compatible = "fsl,elo-dma", },
         {}
 };
 
-static struct of_platform_driver of_fsl_dma_driver = {
-        .name = "fsl-elo-dma",
-        .match_table = of_fsl_dma_ids,
-        .probe = of_fsl_dma_probe,
-        .remove = of_fsl_dma_remove,
+static struct of_platform_driver fsldma_of_driver = {
+        .name           = "fsl-elo-dma",
+        .match_table    = fsldma_of_ids,
+        .probe          = fsldma_of_probe,
+        .remove         = fsldma_of_remove,
 };
 
-static __init int of_fsl_dma_init(void)
+/*----------------------------------------------------------------------------*/
+/* Module Init / Exit                                                         */
+/*----------------------------------------------------------------------------*/
+
+static __init int fsldma_init(void)
 {
         int ret;
 
         pr_info("Freescale Elo / Elo Plus DMA driver\n");
 
-        ret = of_register_platform_driver(&of_fsl_dma_driver);
+        ret = of_register_platform_driver(&fsldma_of_driver);
         if (ret)
                 pr_err("fsldma: failed to register platform driver\n");
 
         return ret;
 }
 
-static void __exit of_fsl_dma_exit(void)
+static void __exit fsldma_exit(void)
 {
-        of_unregister_platform_driver(&of_fsl_dma_driver);
+        of_unregister_platform_driver(&fsldma_of_driver);
 }
 
-subsys_initcall(of_fsl_dma_init);
-module_exit(of_fsl_dma_exit);
+subsys_initcall(fsldma_init);
+module_exit(fsldma_exit);
 
 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
 MODULE_LICENSE("GPL");