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path: root/drivers/dma/amba-pl08x.c
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Diffstat (limited to 'drivers/dma/amba-pl08x.c')
-rw-r--r--drivers/dma/amba-pl08x.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index b7cbd1ab1db1..41c62fd0680d 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -882,9 +882,9 @@ static int prep_phy_channel(struct pl08x_dma_chan *plchan,
882 ch->signal = ret; 882 ch->signal = ret;
883 883
884 /* Assign the flow control signal to this channel */ 884 /* Assign the flow control signal to this channel */
885 if (txd->direction == DMA_TO_DEVICE) 885 if (txd->direction == DMA_MEM_TO_DEV)
886 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; 886 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
887 else if (txd->direction == DMA_FROM_DEVICE) 887 else if (txd->direction == DMA_DEV_TO_MEM)
888 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; 888 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
889 } 889 }
890 890
@@ -1102,10 +1102,10 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1102 1102
1103 /* Transfer direction */ 1103 /* Transfer direction */
1104 plchan->runtime_direction = config->direction; 1104 plchan->runtime_direction = config->direction;
1105 if (config->direction == DMA_TO_DEVICE) { 1105 if (config->direction == DMA_MEM_TO_DEV) {
1106 addr_width = config->dst_addr_width; 1106 addr_width = config->dst_addr_width;
1107 maxburst = config->dst_maxburst; 1107 maxburst = config->dst_maxburst;
1108 } else if (config->direction == DMA_FROM_DEVICE) { 1108 } else if (config->direction == DMA_DEV_TO_MEM) {
1109 addr_width = config->src_addr_width; 1109 addr_width = config->src_addr_width;
1110 maxburst = config->src_maxburst; 1110 maxburst = config->src_maxburst;
1111 } else { 1111 } else {
@@ -1136,7 +1136,7 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1136 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; 1136 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1137 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; 1137 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1138 1138
1139 if (plchan->runtime_direction == DMA_FROM_DEVICE) { 1139 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
1140 plchan->src_addr = config->src_addr; 1140 plchan->src_addr = config->src_addr;
1141 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | 1141 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1142 pl08x_select_bus(plchan->cd->periph_buses, 1142 pl08x_select_bus(plchan->cd->periph_buses,
@@ -1152,7 +1152,7 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1152 "configured channel %s (%s) for %s, data width %d, " 1152 "configured channel %s (%s) for %s, data width %d, "
1153 "maxburst %d words, LE, CCTL=0x%08x\n", 1153 "maxburst %d words, LE, CCTL=0x%08x\n",
1154 dma_chan_name(chan), plchan->name, 1154 dma_chan_name(chan), plchan->name,
1155 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", 1155 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
1156 addr_width, 1156 addr_width,
1157 maxburst, 1157 maxburst,
1158 cctl); 1158 cctl);
@@ -1322,7 +1322,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1322 1322
1323static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( 1323static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1324 struct dma_chan *chan, struct scatterlist *sgl, 1324 struct dma_chan *chan, struct scatterlist *sgl,
1325 unsigned int sg_len, enum dma_data_direction direction, 1325 unsigned int sg_len, enum dma_transfer_direction direction,
1326 unsigned long flags) 1326 unsigned long flags)
1327{ 1327{
1328 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1328 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
@@ -1354,10 +1354,10 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1354 */ 1354 */
1355 txd->direction = direction; 1355 txd->direction = direction;
1356 1356
1357 if (direction == DMA_TO_DEVICE) { 1357 if (direction == DMA_MEM_TO_DEV) {
1358 txd->cctl = plchan->dst_cctl; 1358 txd->cctl = plchan->dst_cctl;
1359 slave_addr = plchan->dst_addr; 1359 slave_addr = plchan->dst_addr;
1360 } else if (direction == DMA_FROM_DEVICE) { 1360 } else if (direction == DMA_DEV_TO_MEM) {
1361 txd->cctl = plchan->src_cctl; 1361 txd->cctl = plchan->src_cctl;
1362 slave_addr = plchan->src_addr; 1362 slave_addr = plchan->src_addr;
1363 } else { 1363 } else {
@@ -1368,10 +1368,10 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1368 } 1368 }
1369 1369
1370 if (plchan->cd->device_fc) 1370 if (plchan->cd->device_fc)
1371 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER_PER : 1371 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1372 PL080_FLOW_PER2MEM_PER; 1372 PL080_FLOW_PER2MEM_PER;
1373 else 1373 else
1374 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER : 1374 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1375 PL080_FLOW_PER2MEM; 1375 PL080_FLOW_PER2MEM;
1376 1376
1377 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; 1377 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
@@ -1387,7 +1387,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1387 list_add_tail(&dsg->node, &txd->dsg_list); 1387 list_add_tail(&dsg->node, &txd->dsg_list);
1388 1388
1389 dsg->len = sg_dma_len(sg); 1389 dsg->len = sg_dma_len(sg);
1390 if (direction == DMA_TO_DEVICE) { 1390 if (direction == DMA_MEM_TO_DEV) {
1391 dsg->src_addr = sg_phys(sg); 1391 dsg->src_addr = sg_phys(sg);
1392 dsg->dst_addr = slave_addr; 1392 dsg->dst_addr = slave_addr;
1393 } else { 1393 } else {