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path: root/drivers/crypto/caam/ctrl.c
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Diffstat (limited to 'drivers/crypto/caam/ctrl.c')
-rw-r--r--drivers/crypto/caam/ctrl.c39
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 066a4d4b62bf..1d8e003d2582 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -88,6 +88,14 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
88 88
89 /* Set the bit to request direct access to DECO0 */ 89 /* Set the bit to request direct access to DECO0 */
90 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; 90 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
91
92 if (ctrlpriv->virt_en == 1)
93 setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
94
95 while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
96 --timeout)
97 cpu_relax();
98
91 setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); 99 setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
92 100
93 while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) && 101 while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
@@ -130,6 +138,9 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
130 *status = rd_reg32(&topregs->deco.op_status_hi) & 138 *status = rd_reg32(&topregs->deco.op_status_hi) &
131 DECO_OP_STATUS_HI_ERR_MASK; 139 DECO_OP_STATUS_HI_ERR_MASK;
132 140
141 if (ctrlpriv->virt_en == 1)
142 clrbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
143
133 /* Mark the DECO as free */ 144 /* Mark the DECO as free */
134 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); 145 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
135 146
@@ -378,6 +389,7 @@ static int caam_probe(struct platform_device *pdev)
378#ifdef CONFIG_DEBUG_FS 389#ifdef CONFIG_DEBUG_FS
379 struct caam_perfmon *perfmon; 390 struct caam_perfmon *perfmon;
380#endif 391#endif
392 u32 scfgr, comp_params;
381 u32 cha_vid_ls; 393 u32 cha_vid_ls;
382 394
383 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private), 395 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
@@ -412,6 +424,33 @@ static int caam_probe(struct platform_device *pdev)
412 setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE | 424 setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
413 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); 425 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
414 426
427 /*
428 * Read the Compile Time paramters and SCFGR to determine
429 * if Virtualization is enabled for this platform
430 */
431 comp_params = rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms);
432 scfgr = rd_reg32(&topregs->ctrl.scfgr);
433
434 ctrlpriv->virt_en = 0;
435 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
436 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
437 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
438 */
439 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
440 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
441 (scfgr & SCFGR_VIRT_EN)))
442 ctrlpriv->virt_en = 1;
443 } else {
444 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
445 if (comp_params & CTPR_MS_VIRT_EN_POR)
446 ctrlpriv->virt_en = 1;
447 }
448
449 if (ctrlpriv->virt_en == 1)
450 setbits32(&topregs->ctrl.jrstart, JRSTART_JR0_START |
451 JRSTART_JR1_START | JRSTART_JR2_START |
452 JRSTART_JR3_START);
453
415 if (sizeof(dma_addr_t) == sizeof(u64)) 454 if (sizeof(dma_addr_t) == sizeof(u64))
416 if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) 455 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
417 dma_set_mask(dev, DMA_BIT_MASK(40)); 456 dma_set_mask(dev, DMA_BIT_MASK(40));