diff options
Diffstat (limited to 'drivers/clocksource')
-rw-r--r-- | drivers/clocksource/bcm_kona_timer.c | 9 | ||||
-rw-r--r-- | drivers/clocksource/exynos_mct.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/sh_tmu.c | 2 |
3 files changed, 7 insertions, 8 deletions
diff --git a/drivers/clocksource/bcm_kona_timer.c b/drivers/clocksource/bcm_kona_timer.c index 0595dc6c453e..f1e33d08dd83 100644 --- a/drivers/clocksource/bcm_kona_timer.c +++ b/drivers/clocksource/bcm_kona_timer.c | |||
@@ -68,9 +68,8 @@ static void kona_timer_disable_and_clear(void __iomem *base) | |||
68 | } | 68 | } |
69 | 69 | ||
70 | static void | 70 | static void |
71 | kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw) | 71 | kona_timer_get_counter(void __iomem *timer_base, uint32_t *msw, uint32_t *lsw) |
72 | { | 72 | { |
73 | void __iomem *base = IOMEM(timer_base); | ||
74 | int loop_limit = 4; | 73 | int loop_limit = 4; |
75 | 74 | ||
76 | /* | 75 | /* |
@@ -86,9 +85,9 @@ kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw) | |||
86 | */ | 85 | */ |
87 | 86 | ||
88 | while (--loop_limit) { | 87 | while (--loop_limit) { |
89 | *msw = readl(base + KONA_GPTIMER_STCHI_OFFSET); | 88 | *msw = readl(timer_base + KONA_GPTIMER_STCHI_OFFSET); |
90 | *lsw = readl(base + KONA_GPTIMER_STCLO_OFFSET); | 89 | *lsw = readl(timer_base + KONA_GPTIMER_STCLO_OFFSET); |
91 | if (*msw == readl(base + KONA_GPTIMER_STCHI_OFFSET)) | 90 | if (*msw == readl(timer_base + KONA_GPTIMER_STCHI_OFFSET)) |
92 | break; | 91 | break; |
93 | } | 92 | } |
94 | if (!loop_limit) { | 93 | if (!loop_limit) { |
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 9403061a2acc..83564c9cfdbe 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c | |||
@@ -97,8 +97,8 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset) | |||
97 | writel_relaxed(value, reg_base + offset); | 97 | writel_relaxed(value, reg_base + offset); |
98 | 98 | ||
99 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { | 99 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
100 | stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; | 100 | stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; |
101 | switch (offset & EXYNOS4_MCT_L_MASK) { | 101 | switch (offset & ~EXYNOS4_MCT_L_MASK) { |
102 | case MCT_L_TCON_OFFSET: | 102 | case MCT_L_TCON_OFFSET: |
103 | mask = 1 << 3; /* L_TCON write status */ | 103 | mask = 1 << 3; /* L_TCON write status */ |
104 | break; | 104 | break; |
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c index 0f665b8f2461..f150ca82bfaf 100644 --- a/drivers/clocksource/sh_tmu.c +++ b/drivers/clocksource/sh_tmu.c | |||
@@ -428,7 +428,7 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, | |||
428 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | 428 | ced->features = CLOCK_EVT_FEAT_PERIODIC; |
429 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | 429 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; |
430 | ced->rating = 200; | 430 | ced->rating = 200; |
431 | ced->cpumask = cpumask_of(0); | 431 | ced->cpumask = cpu_possible_mask; |
432 | ced->set_next_event = sh_tmu_clock_event_next; | 432 | ced->set_next_event = sh_tmu_clock_event_next; |
433 | ced->set_mode = sh_tmu_clock_event_mode; | 433 | ced->set_mode = sh_tmu_clock_event_mode; |
434 | ced->suspend = sh_tmu_clock_event_suspend; | 434 | ced->suspend = sh_tmu_clock_event_suspend; |