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-rw-r--r--drivers/clk/ux500/u8500_of_clk.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
index ceebce6a624f..bfbe3cae72d7 100644
--- a/drivers/clk/ux500/u8500_of_clk.c
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -7,6 +7,7 @@
7 * License terms: GNU General Public License (GPL) version 2 7 * License terms: GNU General Public License (GPL) version 2
8 */ 8 */
9 9
10#include <linux/of.h>
10#include <linux/clk.h> 11#include <linux/clk.h>
11#include <linux/clkdev.h> 12#include <linux/clkdev.h>
12#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
@@ -14,13 +15,27 @@
14#include <linux/platform_data/clk-ux500.h> 15#include <linux/platform_data/clk-ux500.h>
15#include "clk.h" 16#include "clk.h"
16 17
18static const struct of_device_id u8500_clk_of_match[] = {
19 { .compatible = "stericsson,u8500-clks", },
20 { },
21};
22
17void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 23void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
18 u32 clkrst5_base, u32 clkrst6_base) 24 u32 clkrst5_base, u32 clkrst6_base)
19{ 25{
20 struct prcmu_fw_version *fw_version; 26 struct prcmu_fw_version *fw_version;
27 struct device_node *np = NULL;
28 struct device_node *child = NULL;
21 const char *sgaclk_parent = NULL; 29 const char *sgaclk_parent = NULL;
22 struct clk *clk; 30 struct clk *clk;
23 31
32 if (of_have_populated_dt())
33 np = of_find_matching_node(NULL, u8500_clk_of_match);
34 if (!np) {
35 pr_err("Either DT or U8500 Clock node not found\n");
36 return;
37 }
38
24 /* Clock sources */ 39 /* Clock sources */
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, 40 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
26 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 41 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
@@ -378,4 +393,8 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
378 /* Periph6 */ 393 /* Periph6 */
379 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 394 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
380 clkrst6_base, BIT(0), CLK_SET_RATE_GATE); 395 clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
396
397 for_each_child_of_node(np, child) {
398 /* Place holder for supported nodes. */
399 }
381} 400}