diff options
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 35aabd37a340..6c1677ccef70 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #define GPLL_CON0 0x10150 | 36 | #define GPLL_CON0 0x10150 |
37 | #define SRC_TOP0 0x10210 | 37 | #define SRC_TOP0 0x10210 |
38 | #define SRC_TOP2 0x10218 | 38 | #define SRC_TOP2 0x10218 |
39 | #define SRC_TOP3 0x1021c | ||
39 | #define SRC_GSCL 0x10220 | 40 | #define SRC_GSCL 0x10220 |
40 | #define SRC_DISP1_0 0x1022c | 41 | #define SRC_DISP1_0 0x1022c |
41 | #define SRC_MAU 0x10240 | 42 | #define SRC_MAU 0x10240 |
@@ -139,6 +140,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = { | |||
139 | SRC_CORE1, | 140 | SRC_CORE1, |
140 | SRC_TOP0, | 141 | SRC_TOP0, |
141 | SRC_TOP2, | 142 | SRC_TOP2, |
143 | SRC_TOP3, | ||
142 | SRC_GSCL, | 144 | SRC_GSCL, |
143 | SRC_DISP1_0, | 145 | SRC_DISP1_0, |
144 | SRC_MAU, | 146 | SRC_MAU, |
@@ -195,6 +197,7 @@ PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; | |||
195 | PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; | 197 | PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; |
196 | PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; | 198 | PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; |
197 | PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; | 199 | PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; |
200 | PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; | ||
198 | PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; | 201 | PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; |
199 | PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; | 202 | PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; |
200 | PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", | 203 | PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", |
@@ -270,6 +273,8 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { | |||
270 | MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), | 273 | MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), |
271 | MUX(none, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), | 274 | MUX(none, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), |
272 | 275 | ||
276 | MUX(none, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), | ||
277 | |||
273 | MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), | 278 | MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), |
274 | MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), | 279 | MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), |
275 | MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), | 280 | MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), |
@@ -483,16 +488,20 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { | |||
483 | GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", | 488 | GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", |
484 | SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), | 489 | SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), |
485 | 490 | ||
486 | GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), | 491 | GATE(gscl0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 0), |
487 | GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), | 492 | GATE(gscl1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 0), |
488 | GATE(gscl2, "gscl2", "div_aclk266", GATE_IP_GSCL, 2, 0, 0), | 493 | GATE(gscl2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 0), |
489 | GATE(gscl3, "gscl3", "div_aclk266", GATE_IP_GSCL, 3, 0, 0), | 494 | GATE(gscl3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 0), |
490 | GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), | 495 | GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), |
491 | GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), | 496 | GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), |
492 | GATE(smmu_gscl0, "smmu_gscl0", "div_aclk266", GATE_IP_GSCL, 7, 0, 0), | 497 | GATE(smmu_gscl0, "smmu_gscl0", "mout_aclk266_gscl_sub", |
493 | GATE(smmu_gscl1, "smmu_gscl1", "div_aclk266", GATE_IP_GSCL, 8, 0, 0), | 498 | GATE_IP_GSCL, 7, 0, 0), |
494 | GATE(smmu_gscl2, "smmu_gscl2", "div_aclk266", GATE_IP_GSCL, 9, 0, 0), | 499 | GATE(smmu_gscl1, "smmu_gscl1", "mout_aclk266_gscl_sub", |
495 | GATE(smmu_gscl3, "smmu_gscl3", "div_aclk266", GATE_IP_GSCL, 10, 0, 0), | 500 | GATE_IP_GSCL, 8, 0, 0), |
501 | GATE(smmu_gscl2, "smmu_gscl2", "mout_aclk266_gscl_sub", | ||
502 | GATE_IP_GSCL, 9, 0, 0), | ||
503 | GATE(smmu_gscl3, "smmu_gscl3", "mout_aclk266_gscl_sub", | ||
504 | GATE_IP_GSCL, 10, 0, 0), | ||
496 | 505 | ||
497 | GATE(fimd1, "fimd1", "div_aclk200", GATE_IP_DISP1, 0, 0, 0), | 506 | GATE(fimd1, "fimd1", "div_aclk200", GATE_IP_DISP1, 0, 0, 0), |
498 | GATE(mie1, "mie1", "div_aclk200", GATE_IP_DISP1, 1, 0, 0), | 507 | GATE(mie1, "mie1", "div_aclk200", GATE_IP_DISP1, 1, 0, 0), |