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path: root/drivers/clk/ti
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Diffstat (limited to 'drivers/clk/ti')
-rw-r--r--drivers/clk/ti/apll.c8
-rw-r--r--drivers/clk/ti/dpll.c5
-rw-r--r--drivers/clk/ti/mux.c2
3 files changed, 7 insertions, 8 deletions
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 5428c9c547cd..72d97279eae1 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -77,13 +77,11 @@ static int dra7_apll_enable(struct clk_hw *hw)
77 if (i == MAX_APLL_WAIT_TRIES) { 77 if (i == MAX_APLL_WAIT_TRIES) {
78 pr_warn("clock: %s failed transition to '%s'\n", 78 pr_warn("clock: %s failed transition to '%s'\n",
79 clk_name, (state) ? "locked" : "bypassed"); 79 clk_name, (state) ? "locked" : "bypassed");
80 } else { 80 r = -EBUSY;
81 } else
81 pr_debug("clock: %s transition to '%s' in %d loops\n", 82 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk_name, (state) ? "locked" : "bypassed", i); 83 clk_name, (state) ? "locked" : "bypassed", i);
83 84
84 r = 0;
85 }
86
87 return r; 85 return r;
88} 86}
89 87
@@ -338,7 +336,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
338 const char *parent_name; 336 const char *parent_name;
339 u32 val; 337 u32 val;
340 338
341 ad = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 339 ad = kzalloc(sizeof(*ad), GFP_KERNEL);
342 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 340 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
343 init = kzalloc(sizeof(*init), GFP_KERNEL); 341 init = kzalloc(sizeof(*init), GFP_KERNEL);
344 342
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index abd956d5f838..79791e1bf282 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -161,7 +161,8 @@ cleanup:
161} 161}
162 162
163#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 163#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
164 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) 164 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
165 defined(CONFIG_SOC_AM43XX)
165/** 166/**
166 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock 167 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
167 * @node: device node for this clock 168 * @node: device node for this clock
@@ -322,7 +323,7 @@ CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
322 of_ti_omap4_dpll_x2_setup); 323 of_ti_omap4_dpll_x2_setup);
323#endif 324#endif
324 325
325#ifdef CONFIG_SOC_AM33XX 326#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
326static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 327static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
327{ 328{
328 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 329 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 0197a478720c..e9d650e51287 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -160,7 +160,7 @@ static void of_mux_clk_setup(struct device_node *node)
160 u8 clk_mux_flags = 0; 160 u8 clk_mux_flags = 0;
161 u32 mask = 0; 161 u32 mask = 0;
162 u32 shift = 0; 162 u32 shift = 0;
163 u32 flags = 0; 163 u32 flags = CLK_SET_RATE_NO_REPARENT;
164 164
165 num_parents = of_clk_get_parent_count(node); 165 num_parents = of_clk_get_parent_count(node);
166 if (num_parents < 2) { 166 if (num_parents < 2) {