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-rw-r--r--drivers/clk/qcom/Kconfig47
-rw-r--r--drivers/clk/qcom/Makefile14
-rw-r--r--drivers/clk/qcom/clk-branch.c159
-rw-r--r--drivers/clk/qcom/clk-branch.h56
-rw-r--r--drivers/clk/qcom/clk-pll.c222
-rw-r--r--drivers/clk/qcom/clk-pll.h66
-rw-r--r--drivers/clk/qcom/clk-rcg.c517
-rw-r--r--drivers/clk/qcom/clk-rcg.h159
-rw-r--r--drivers/clk/qcom/clk-rcg2.c291
-rw-r--r--drivers/clk/qcom/clk-regmap.c114
-rw-r--r--drivers/clk/qcom/clk-regmap.h45
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c2819
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c2993
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c2694
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c2321
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c2625
-rw-r--r--drivers/clk/qcom/reset.c63
-rw-r--r--drivers/clk/qcom/reset.h37
18 files changed, 15242 insertions, 0 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
new file mode 100644
index 000000000000..995bcfa021a4
--- /dev/null
+++ b/drivers/clk/qcom/Kconfig
@@ -0,0 +1,47 @@
1config COMMON_CLK_QCOM
2 tristate "Support for Qualcomm's clock controllers"
3 depends on OF
4 select REGMAP_MMIO
5 select RESET_CONTROLLER
6
7config MSM_GCC_8660
8 tristate "MSM8660 Global Clock Controller"
9 depends on COMMON_CLK_QCOM
10 help
11 Support for the global clock controller on msm8660 devices.
12 Say Y if you want to use peripheral devices such as UART, SPI,
13 i2c, USB, SD/eMMC, etc.
14
15config MSM_GCC_8960
16 tristate "MSM8960 Global Clock Controller"
17 depends on COMMON_CLK_QCOM
18 help
19 Support for the global clock controller on msm8960 devices.
20 Say Y if you want to use peripheral devices such as UART, SPI,
21 i2c, USB, SD/eMMC, SATA, PCIe, etc.
22
23config MSM_MMCC_8960
24 tristate "MSM8960 Multimedia Clock Controller"
25 select MSM_GCC_8960
26 depends on COMMON_CLK_QCOM
27 help
28 Support for the multimedia clock controller on msm8960 devices.
29 Say Y if you want to support multimedia devices such as display,
30 graphics, video encode/decode, camera, etc.
31
32config MSM_GCC_8974
33 tristate "MSM8974 Global Clock Controller"
34 depends on COMMON_CLK_QCOM
35 help
36 Support for the global clock controller on msm8974 devices.
37 Say Y if you want to use peripheral devices such as UART, SPI,
38 i2c, USB, SD/eMMC, SATA, PCIe, etc.
39
40config MSM_MMCC_8974
41 tristate "MSM8974 Multimedia Clock Controller"
42 select MSM_GCC_8974
43 depends on COMMON_CLK_QCOM
44 help
45 Support for the multimedia clock controller on msm8974 devices.
46 Say Y if you want to support multimedia devices such as display,
47 graphics, video encode/decode, camera, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
new file mode 100644
index 000000000000..190d38433202
--- /dev/null
+++ b/drivers/clk/qcom/Makefile
@@ -0,0 +1,14 @@
1obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
2
3clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o
4clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
5clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
6clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
7clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
8clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o
9
10obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
11obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
12obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
13obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
14obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
new file mode 100644
index 000000000000..6b4d2bcb1a53
--- /dev/null
+++ b/drivers/clk/qcom/clk-branch.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/export.h>
19#include <linux/clk-provider.h>
20#include <linux/regmap.h>
21
22#include "clk-branch.h"
23
24static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
25{
26 u32 val;
27
28 if (!br->hwcg_reg)
29 return 0;
30
31 regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
32
33 return !!(val & BIT(br->hwcg_bit));
34}
35
36static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
37{
38 bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
39 u32 val;
40
41 regmap_read(br->clkr.regmap, br->halt_reg, &val);
42
43 val &= BIT(br->halt_bit);
44 if (invert)
45 val = !val;
46
47 return !!val == !enabling;
48}
49
50#define BRANCH_CLK_OFF BIT(31)
51#define BRANCH_NOC_FSM_STATUS_SHIFT 28
52#define BRANCH_NOC_FSM_STATUS_MASK 0x7
53#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT)
54
55static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
56{
57 u32 val;
58 u32 mask;
59
60 mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT;
61 mask |= BRANCH_CLK_OFF;
62
63 regmap_read(br->clkr.regmap, br->halt_reg, &val);
64
65 if (enabling) {
66 val &= mask;
67 return (val & BRANCH_CLK_OFF) == 0 ||
68 val == BRANCH_NOC_FSM_STATUS_ON;
69 } else {
70 return val & BRANCH_CLK_OFF;
71 }
72}
73
74static int clk_branch_wait(const struct clk_branch *br, bool enabling,
75 bool (check_halt)(const struct clk_branch *, bool))
76{
77 bool voted = br->halt_check & BRANCH_VOTED;
78 const char *name = __clk_get_name(br->clkr.hw.clk);
79
80 /* Skip checking halt bit if the clock is in hardware gated mode */
81 if (clk_branch_in_hwcg_mode(br))
82 return 0;
83
84 if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
85 udelay(10);
86 } else if (br->halt_check == BRANCH_HALT_ENABLE ||
87 br->halt_check == BRANCH_HALT ||
88 (enabling && voted)) {
89 int count = 200;
90
91 while (count-- > 0) {
92 if (check_halt(br, enabling))
93 return 0;
94 udelay(1);
95 }
96 WARN(1, "%s status stuck at 'o%s'", name,
97 enabling ? "ff" : "n");
98 return -EBUSY;
99 }
100 return 0;
101}
102
103static int clk_branch_toggle(struct clk_hw *hw, bool en,
104 bool (check_halt)(const struct clk_branch *, bool))
105{
106 struct clk_branch *br = to_clk_branch(hw);
107 int ret;
108
109 if (en) {
110 ret = clk_enable_regmap(hw);
111 if (ret)
112 return ret;
113 } else {
114 clk_disable_regmap(hw);
115 }
116
117 return clk_branch_wait(br, en, check_halt);
118}
119
120static int clk_branch_enable(struct clk_hw *hw)
121{
122 return clk_branch_toggle(hw, true, clk_branch_check_halt);
123}
124
125static void clk_branch_disable(struct clk_hw *hw)
126{
127 clk_branch_toggle(hw, false, clk_branch_check_halt);
128}
129
130const struct clk_ops clk_branch_ops = {
131 .enable = clk_branch_enable,
132 .disable = clk_branch_disable,
133 .is_enabled = clk_is_enabled_regmap,
134};
135EXPORT_SYMBOL_GPL(clk_branch_ops);
136
137static int clk_branch2_enable(struct clk_hw *hw)
138{
139 return clk_branch_toggle(hw, true, clk_branch2_check_halt);
140}
141
142static void clk_branch2_disable(struct clk_hw *hw)
143{
144 clk_branch_toggle(hw, false, clk_branch2_check_halt);
145}
146
147const struct clk_ops clk_branch2_ops = {
148 .enable = clk_branch2_enable,
149 .disable = clk_branch2_disable,
150 .is_enabled = clk_is_enabled_regmap,
151};
152EXPORT_SYMBOL_GPL(clk_branch2_ops);
153
154const struct clk_ops clk_branch_simple_ops = {
155 .enable = clk_enable_regmap,
156 .disable = clk_disable_regmap,
157 .is_enabled = clk_is_enabled_regmap,
158};
159EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
new file mode 100644
index 000000000000..284df3f3c55f
--- /dev/null
+++ b/drivers/clk/qcom/clk-branch.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_BRANCH_H__
15#define __QCOM_CLK_BRANCH_H__
16
17#include <linux/clk-provider.h>
18
19#include "clk-regmap.h"
20
21/**
22 * struct clk_branch - gating clock with status bit and dynamic hardware gating
23 *
24 * @hwcg_reg: dynamic hardware clock gating register
25 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
26 * @halt_reg: halt register
27 * @halt_bit: ANDed with @halt_reg to test for clock halted
28 * @halt_check: type of halt checking to perform
29 * @clkr: handle between common and hardware-specific interfaces
30 *
31 * Clock which can gate its output.
32 */
33struct clk_branch {
34 u32 hwcg_reg;
35 u32 halt_reg;
36 u8 hwcg_bit;
37 u8 halt_bit;
38 u8 halt_check;
39#define BRANCH_VOTED BIT(7) /* Delay on disable */
40#define BRANCH_HALT 0 /* pol: 1 = halt */
41#define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED)
42#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
43#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
44#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
45
46 struct clk_regmap clkr;
47};
48
49extern const struct clk_ops clk_branch_ops;
50extern const struct clk_ops clk_branch2_ops;
51extern const struct clk_ops clk_branch_simple_ops;
52
53#define to_clk_branch(_hw) \
54 container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
55
56#endif
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
new file mode 100644
index 000000000000..0f927c538613
--- /dev/null
+++ b/drivers/clk/qcom/clk-pll.c
@@ -0,0 +1,222 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/bug.h>
18#include <linux/delay.h>
19#include <linux/export.h>
20#include <linux/clk-provider.h>
21#include <linux/regmap.h>
22
23#include <asm/div64.h>
24
25#include "clk-pll.h"
26
27#define PLL_OUTCTRL BIT(0)
28#define PLL_BYPASSNL BIT(1)
29#define PLL_RESET_N BIT(2)
30#define PLL_LOCK_COUNT_SHIFT 8
31#define PLL_LOCK_COUNT_MASK 0x3f
32#define PLL_BIAS_COUNT_SHIFT 14
33#define PLL_BIAS_COUNT_MASK 0x3f
34#define PLL_VOTE_FSM_ENA BIT(20)
35#define PLL_VOTE_FSM_RESET BIT(21)
36
37static int clk_pll_enable(struct clk_hw *hw)
38{
39 struct clk_pll *pll = to_clk_pll(hw);
40 int ret;
41 u32 mask, val;
42
43 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
45 if (ret)
46 return ret;
47
48 /* Skip if already enabled or in FSM mode */
49 if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
50 return 0;
51
52 /* Disable PLL bypass mode. */
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
54 PLL_BYPASSNL);
55 if (ret)
56 return ret;
57
58 /*
59 * H/W requires a 5us delay between disabling the bypass and
60 * de-asserting the reset. Delay 10us just to be safe.
61 */
62 udelay(10);
63
64 /* De-assert active-low PLL reset. */
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
66 PLL_RESET_N);
67 if (ret)
68 return ret;
69
70 /* Wait until PLL is locked. */
71 udelay(50);
72
73 /* Enable PLL output. */
74 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
75 PLL_OUTCTRL);
76 if (ret)
77 return ret;
78
79 return 0;
80}
81
82static void clk_pll_disable(struct clk_hw *hw)
83{
84 struct clk_pll *pll = to_clk_pll(hw);
85 u32 mask;
86 u32 val;
87
88 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
89 /* Skip if in FSM mode */
90 if (val & PLL_VOTE_FSM_ENA)
91 return;
92 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
93 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
94}
95
96static unsigned long
97clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
98{
99 struct clk_pll *pll = to_clk_pll(hw);
100 u32 l, m, n;
101 unsigned long rate;
102 u64 tmp;
103
104 regmap_read(pll->clkr.regmap, pll->l_reg, &l);
105 regmap_read(pll->clkr.regmap, pll->m_reg, &m);
106 regmap_read(pll->clkr.regmap, pll->n_reg, &n);
107
108 l &= 0x3ff;
109 m &= 0x7ffff;
110 n &= 0x7ffff;
111
112 rate = parent_rate * l;
113 if (n) {
114 tmp = parent_rate;
115 tmp *= m;
116 do_div(tmp, n);
117 rate += tmp;
118 }
119 return rate;
120}
121
122const struct clk_ops clk_pll_ops = {
123 .enable = clk_pll_enable,
124 .disable = clk_pll_disable,
125 .recalc_rate = clk_pll_recalc_rate,
126};
127EXPORT_SYMBOL_GPL(clk_pll_ops);
128
129static int wait_for_pll(struct clk_pll *pll)
130{
131 u32 val;
132 int count;
133 int ret;
134 const char *name = __clk_get_name(pll->clkr.hw.clk);
135
136 /* Wait for pll to enable. */
137 for (count = 200; count > 0; count--) {
138 ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
139 if (ret)
140 return ret;
141 if (val & BIT(pll->status_bit))
142 return 0;
143 udelay(1);
144 }
145
146 WARN(1, "%s didn't enable after voting for it!\n", name);
147 return -ETIMEDOUT;
148}
149
150static int clk_pll_vote_enable(struct clk_hw *hw)
151{
152 int ret;
153 struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
154
155 ret = clk_enable_regmap(hw);
156 if (ret)
157 return ret;
158
159 return wait_for_pll(p);
160}
161
162const struct clk_ops clk_pll_vote_ops = {
163 .enable = clk_pll_vote_enable,
164 .disable = clk_disable_regmap,
165};
166EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
167
168static void
169clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
170{
171 u32 val;
172 u32 mask;
173
174 /* De-assert reset to FSM */
175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
176
177 /* Program bias count and lock count */
178 val = 1 << PLL_BIAS_COUNT_SHIFT;
179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
181 regmap_update_bits(regmap, pll->mode_reg, mask, val);
182
183 /* Enable PLL FSM voting */
184 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,
185 PLL_VOTE_FSM_ENA);
186}
187
188static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
189 const struct pll_config *config)
190{
191 u32 val;
192 u32 mask;
193
194 regmap_write(regmap, pll->l_reg, config->l);
195 regmap_write(regmap, pll->m_reg, config->m);
196 regmap_write(regmap, pll->n_reg, config->n);
197
198 val = config->vco_val;
199 val |= config->pre_div_val;
200 val |= config->post_div_val;
201 val |= config->mn_ena_mask;
202 val |= config->main_output_mask;
203 val |= config->aux_output_mask;
204
205 mask = config->vco_mask;
206 mask |= config->pre_div_mask;
207 mask |= config->post_div_mask;
208 mask |= config->mn_ena_mask;
209 mask |= config->main_output_mask;
210 mask |= config->aux_output_mask;
211
212 regmap_update_bits(regmap, pll->config_reg, mask, val);
213}
214
215void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode)
217{
218 clk_pll_configure(pll, regmap, config);
219 if (fsm_mode)
220 clk_pll_set_fsm_mode(pll, regmap);
221}
222EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
new file mode 100644
index 000000000000..0775a99ca768
--- /dev/null
+++ b/drivers/clk/qcom/clk-pll.h
@@ -0,0 +1,66 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_PLL_H__
15#define __QCOM_CLK_PLL_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20/**
21 * struct clk_pll - phase locked loop (PLL)
22 * @l_reg: L register
23 * @m_reg: M register
24 * @n_reg: N register
25 * @config_reg: config register
26 * @mode_reg: mode register
27 * @status_reg: status register
28 * @status_bit: ANDed with @status_reg to determine if PLL is enabled
29 * @hw: handle between common and hardware-specific interfaces
30 */
31struct clk_pll {
32 u32 l_reg;
33 u32 m_reg;
34 u32 n_reg;
35 u32 config_reg;
36 u32 mode_reg;
37 u32 status_reg;
38 u8 status_bit;
39
40 struct clk_regmap clkr;
41};
42
43extern const struct clk_ops clk_pll_ops;
44extern const struct clk_ops clk_pll_vote_ops;
45
46#define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
47
48struct pll_config {
49 u16 l;
50 u32 m;
51 u32 n;
52 u32 vco_val;
53 u32 vco_mask;
54 u32 pre_div_val;
55 u32 pre_div_mask;
56 u32 post_div_val;
57 u32 post_div_mask;
58 u32 mn_ena_mask;
59 u32 main_output_mask;
60 u32 aux_output_mask;
61};
62
63void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
64 const struct pll_config *config, bool fsm_mode);
65
66#endif
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
new file mode 100644
index 000000000000..abfc2b675aea
--- /dev/null
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -0,0 +1,517 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/clk-provider.h>
19#include <linux/regmap.h>
20
21#include <asm/div64.h>
22
23#include "clk-rcg.h"
24
25static u32 ns_to_src(struct src_sel *s, u32 ns)
26{
27 ns >>= s->src_sel_shift;
28 ns &= SRC_SEL_MASK;
29 return ns;
30}
31
32static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
33{
34 u32 mask;
35
36 mask = SRC_SEL_MASK;
37 mask <<= s->src_sel_shift;
38 ns &= ~mask;
39
40 ns |= src << s->src_sel_shift;
41 return ns;
42}
43
44static u8 clk_rcg_get_parent(struct clk_hw *hw)
45{
46 struct clk_rcg *rcg = to_clk_rcg(hw);
47 int num_parents = __clk_get_num_parents(hw->clk);
48 u32 ns;
49 int i;
50
51 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
52 ns = ns_to_src(&rcg->s, ns);
53 for (i = 0; i < num_parents; i++)
54 if (ns == rcg->s.parent_map[i])
55 return i;
56
57 return -EINVAL;
58}
59
60static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
61{
62 bank &= BIT(rcg->mux_sel_bit);
63 return !!bank;
64}
65
66static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
67{
68 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
69 int num_parents = __clk_get_num_parents(hw->clk);
70 u32 ns, ctl;
71 int bank;
72 int i;
73 struct src_sel *s;
74
75 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
76 bank = reg_to_bank(rcg, ctl);
77 s = &rcg->s[bank];
78
79 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
80 ns = ns_to_src(s, ns);
81
82 for (i = 0; i < num_parents; i++)
83 if (ns == s->parent_map[i])
84 return i;
85
86 return -EINVAL;
87}
88
89static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
90{
91 struct clk_rcg *rcg = to_clk_rcg(hw);
92 u32 ns;
93
94 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
95 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
96 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
97
98 return 0;
99}
100
101static u32 md_to_m(struct mn *mn, u32 md)
102{
103 md >>= mn->m_val_shift;
104 md &= BIT(mn->width) - 1;
105 return md;
106}
107
108static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
109{
110 ns >>= p->pre_div_shift;
111 ns &= BIT(p->pre_div_width) - 1;
112 return ns;
113}
114
115static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
116{
117 u32 mask;
118
119 mask = BIT(p->pre_div_width) - 1;
120 mask <<= p->pre_div_shift;
121 ns &= ~mask;
122
123 ns |= pre_div << p->pre_div_shift;
124 return ns;
125}
126
127static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
128{
129 u32 mask, mask_w;
130
131 mask_w = BIT(mn->width) - 1;
132 mask = (mask_w << mn->m_val_shift) | mask_w;
133 md &= ~mask;
134
135 if (n) {
136 m <<= mn->m_val_shift;
137 md |= m;
138 md |= ~n & mask_w;
139 }
140
141 return md;
142}
143
144static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
145{
146 ns = ~ns >> mn->n_val_shift;
147 ns &= BIT(mn->width) - 1;
148 return ns + m;
149}
150
151static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
152{
153 val >>= mn->mnctr_mode_shift;
154 val &= MNCTR_MODE_MASK;
155 return val;
156}
157
158static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
159{
160 u32 mask;
161
162 mask = BIT(mn->width) - 1;
163 mask <<= mn->n_val_shift;
164 ns &= ~mask;
165
166 if (n) {
167 n = n - m;
168 n = ~n;
169 n &= BIT(mn->width) - 1;
170 n <<= mn->n_val_shift;
171 ns |= n;
172 }
173
174 return ns;
175}
176
177static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
178{
179 u32 mask;
180
181 mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
182 mask |= BIT(mn->mnctr_en_bit);
183 val &= ~mask;
184
185 if (n) {
186 val |= BIT(mn->mnctr_en_bit);
187 val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
188 }
189
190 return val;
191}
192
193static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
194{
195 u32 ns, md, ctl, *regp;
196 int bank, new_bank;
197 struct mn *mn;
198 struct pre_div *p;
199 struct src_sel *s;
200 bool enabled;
201 u32 md_reg;
202 u32 bank_reg;
203 bool banked_mn = !!rcg->mn[1].width;
204 struct clk_hw *hw = &rcg->clkr.hw;
205
206 enabled = __clk_is_enabled(hw->clk);
207
208 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
209 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
210
211 if (banked_mn) {
212 regp = &ctl;
213 bank_reg = rcg->clkr.enable_reg;
214 } else {
215 regp = &ns;
216 bank_reg = rcg->ns_reg;
217 }
218
219 bank = reg_to_bank(rcg, *regp);
220 new_bank = enabled ? !bank : bank;
221
222 if (banked_mn) {
223 mn = &rcg->mn[new_bank];
224 md_reg = rcg->md_reg[new_bank];
225
226 ns |= BIT(mn->mnctr_reset_bit);
227 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
228
229 regmap_read(rcg->clkr.regmap, md_reg, &md);
230 md = mn_to_md(mn, f->m, f->n, md);
231 regmap_write(rcg->clkr.regmap, md_reg, md);
232
233 ns = mn_to_ns(mn, f->m, f->n, ns);
234 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
235
236 ctl = mn_to_reg(mn, f->m, f->n, ctl);
237 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
238
239 ns &= ~BIT(mn->mnctr_reset_bit);
240 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
241 } else {
242 p = &rcg->p[new_bank];
243 ns = pre_div_to_ns(p, f->pre_div - 1, ns);
244 }
245
246 s = &rcg->s[new_bank];
247 ns = src_to_ns(s, s->parent_map[f->src], ns);
248 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
249
250 if (enabled) {
251 *regp ^= BIT(rcg->mux_sel_bit);
252 regmap_write(rcg->clkr.regmap, bank_reg, *regp);
253 }
254}
255
256static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
257{
258 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
259 u32 ns, ctl, md, reg;
260 int bank;
261 struct freq_tbl f = { 0 };
262 bool banked_mn = !!rcg->mn[1].width;
263
264 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
265 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
266 reg = banked_mn ? ctl : ns;
267
268 bank = reg_to_bank(rcg, reg);
269
270 if (banked_mn) {
271 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
272 f.m = md_to_m(&rcg->mn[bank], md);
273 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
274 } else {
275 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
276 }
277 f.src = index;
278
279 configure_bank(rcg, &f);
280
281 return 0;
282}
283
284/*
285 * Calculate m/n:d rate
286 *
287 * parent_rate m
288 * rate = ----------- x ---
289 * pre_div n
290 */
291static unsigned long
292calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
293{
294 if (pre_div)
295 rate /= pre_div + 1;
296
297 if (mode) {
298 u64 tmp = rate;
299 tmp *= m;
300 do_div(tmp, n);
301 rate = tmp;
302 }
303
304 return rate;
305}
306
307static unsigned long
308clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
309{
310 struct clk_rcg *rcg = to_clk_rcg(hw);
311 u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
312 struct mn *mn = &rcg->mn;
313
314 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
315 pre_div = ns_to_pre_div(&rcg->p, ns);
316
317 if (rcg->mn.width) {
318 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
319 m = md_to_m(mn, md);
320 n = ns_m_to_n(mn, ns, m);
321 /* MN counter mode is in hw.enable_reg sometimes */
322 if (rcg->clkr.enable_reg != rcg->ns_reg)
323 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
324 else
325 mode = ns;
326 mode = reg_to_mnctr_mode(mn, mode);
327 }
328
329 return calc_rate(parent_rate, m, n, mode, pre_div);
330}
331
332static unsigned long
333clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
334{
335 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
336 u32 m, n, pre_div, ns, md, mode, reg;
337 int bank;
338 struct mn *mn;
339 bool banked_mn = !!rcg->mn[1].width;
340
341 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
342
343 if (banked_mn)
344 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &reg);
345 else
346 reg = ns;
347
348 bank = reg_to_bank(rcg, reg);
349
350 if (banked_mn) {
351 mn = &rcg->mn[bank];
352 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
353 m = md_to_m(mn, md);
354 n = ns_m_to_n(mn, ns, m);
355 mode = reg_to_mnctr_mode(mn, reg);
356 return calc_rate(parent_rate, m, n, mode, 0);
357 } else {
358 pre_div = ns_to_pre_div(&rcg->p[bank], ns);
359 return calc_rate(parent_rate, 0, 0, 0, pre_div);
360 }
361}
362
363static const
364struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
365{
366 if (!f)
367 return NULL;
368
369 for (; f->freq; f++)
370 if (rate <= f->freq)
371 return f;
372
373 return NULL;
374}
375
376static long _freq_tbl_determine_rate(struct clk_hw *hw,
377 const struct freq_tbl *f, unsigned long rate,
378 unsigned long *p_rate, struct clk **p)
379{
380 unsigned long clk_flags;
381
382 f = find_freq(f, rate);
383 if (!f)
384 return -EINVAL;
385
386 clk_flags = __clk_get_flags(hw->clk);
387 *p = clk_get_parent_by_index(hw->clk, f->src);
388 if (clk_flags & CLK_SET_RATE_PARENT) {
389 rate = rate * f->pre_div;
390 if (f->n) {
391 u64 tmp = rate;
392 tmp = tmp * f->n;
393 do_div(tmp, f->m);
394 rate = tmp;
395 }
396 } else {
397 rate = __clk_get_rate(*p);
398 }
399 *p_rate = rate;
400
401 return f->freq;
402}
403
404static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
405 unsigned long *p_rate, struct clk **p)
406{
407 struct clk_rcg *rcg = to_clk_rcg(hw);
408
409 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
410}
411
412static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
413 unsigned long *p_rate, struct clk **p)
414{
415 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
416
417 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
418}
419
420static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long parent_rate)
422{
423 struct clk_rcg *rcg = to_clk_rcg(hw);
424 const struct freq_tbl *f;
425 u32 ns, md, ctl;
426 struct mn *mn = &rcg->mn;
427 u32 mask = 0;
428 unsigned int reset_reg;
429
430 f = find_freq(rcg->freq_tbl, rate);
431 if (!f)
432 return -EINVAL;
433
434 if (rcg->mn.reset_in_cc)
435 reset_reg = rcg->clkr.enable_reg;
436 else
437 reset_reg = rcg->ns_reg;
438
439 if (rcg->mn.width) {
440 mask = BIT(mn->mnctr_reset_bit);
441 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
442
443 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
444 md = mn_to_md(mn, f->m, f->n, md);
445 regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
446
447 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
448 /* MN counter mode is in hw.enable_reg sometimes */
449 if (rcg->clkr.enable_reg != rcg->ns_reg) {
450 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
451 ctl = mn_to_reg(mn, f->m, f->n, ctl);
452 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
453 } else {
454 ns = mn_to_reg(mn, f->m, f->n, ns);
455 }
456 ns = mn_to_ns(mn, f->m, f->n, ns);
457 } else {
458 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
459 }
460
461 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
462 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
463
464 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
465
466 return 0;
467}
468
469static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
470{
471 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
472 const struct freq_tbl *f;
473
474 f = find_freq(rcg->freq_tbl, rate);
475 if (!f)
476 return -EINVAL;
477
478 configure_bank(rcg, f);
479
480 return 0;
481}
482
483static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
484 unsigned long parent_rate)
485{
486 return __clk_dyn_rcg_set_rate(hw, rate);
487}
488
489static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
490 unsigned long rate, unsigned long parent_rate, u8 index)
491{
492 return __clk_dyn_rcg_set_rate(hw, rate);
493}
494
495const struct clk_ops clk_rcg_ops = {
496 .enable = clk_enable_regmap,
497 .disable = clk_disable_regmap,
498 .get_parent = clk_rcg_get_parent,
499 .set_parent = clk_rcg_set_parent,
500 .recalc_rate = clk_rcg_recalc_rate,
501 .determine_rate = clk_rcg_determine_rate,
502 .set_rate = clk_rcg_set_rate,
503};
504EXPORT_SYMBOL_GPL(clk_rcg_ops);
505
506const struct clk_ops clk_dyn_rcg_ops = {
507 .enable = clk_enable_regmap,
508 .is_enabled = clk_is_enabled_regmap,
509 .disable = clk_disable_regmap,
510 .get_parent = clk_dyn_rcg_get_parent,
511 .set_parent = clk_dyn_rcg_set_parent,
512 .recalc_rate = clk_dyn_rcg_recalc_rate,
513 .determine_rate = clk_dyn_rcg_determine_rate,
514 .set_rate = clk_dyn_rcg_set_rate,
515 .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
516};
517EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
new file mode 100644
index 000000000000..1d6b6dece328
--- /dev/null
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -0,0 +1,159 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_RCG_H__
15#define __QCOM_CLK_RCG_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20struct freq_tbl {
21 unsigned long freq;
22 u8 src;
23 u8 pre_div;
24 u16 m;
25 u16 n;
26};
27
28/**
29 * struct mn - M/N:D counter
30 * @mnctr_en_bit: bit to enable mn counter
31 * @mnctr_reset_bit: bit to assert mn counter reset
32 * @mnctr_mode_shift: lowest bit of mn counter mode field
33 * @n_val_shift: lowest bit of n value field
34 * @m_val_shift: lowest bit of m value field
35 * @width: number of bits in m/n/d values
36 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
37 */
38struct mn {
39 u8 mnctr_en_bit;
40 u8 mnctr_reset_bit;
41 u8 mnctr_mode_shift;
42#define MNCTR_MODE_DUAL 0x2
43#define MNCTR_MODE_MASK 0x3
44 u8 n_val_shift;
45 u8 m_val_shift;
46 u8 width;
47 bool reset_in_cc;
48};
49
50/**
51 * struct pre_div - pre-divider
52 * @pre_div_shift: lowest bit of pre divider field
53 * @pre_div_width: number of bits in predivider
54 */
55struct pre_div {
56 u8 pre_div_shift;
57 u8 pre_div_width;
58};
59
60/**
61 * struct src_sel - source selector
62 * @src_sel_shift: lowest bit of source selection field
63 * @parent_map: map from software's parent index to hardware's src_sel field
64 */
65struct src_sel {
66 u8 src_sel_shift;
67#define SRC_SEL_MASK 0x7
68 const u8 *parent_map;
69};
70
71/**
72 * struct clk_rcg - root clock generator
73 *
74 * @ns_reg: NS register
75 * @md_reg: MD register
76 * @mn: mn counter
77 * @p: pre divider
78 * @s: source selector
79 * @freq_tbl: frequency table
80 * @clkr: regmap clock handle
81 * @lock: register lock
82 *
83 */
84struct clk_rcg {
85 u32 ns_reg;
86 u32 md_reg;
87
88 struct mn mn;
89 struct pre_div p;
90 struct src_sel s;
91
92 const struct freq_tbl *freq_tbl;
93
94 struct clk_regmap clkr;
95};
96
97extern const struct clk_ops clk_rcg_ops;
98
99#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
100
101/**
102 * struct clk_dyn_rcg - root clock generator with glitch free mux
103 *
104 * @mux_sel_bit: bit to switch glitch free mux
105 * @ns_reg: NS register
106 * @md_reg: MD0 and MD1 register
107 * @mn: mn counter (banked)
108 * @s: source selector (banked)
109 * @freq_tbl: frequency table
110 * @clkr: regmap clock handle
111 * @lock: register lock
112 *
113 */
114struct clk_dyn_rcg {
115 u32 ns_reg;
116 u32 md_reg[2];
117
118 u8 mux_sel_bit;
119
120 struct mn mn[2];
121 struct pre_div p[2];
122 struct src_sel s[2];
123
124 const struct freq_tbl *freq_tbl;
125
126 struct clk_regmap clkr;
127};
128
129extern const struct clk_ops clk_dyn_rcg_ops;
130
131#define to_clk_dyn_rcg(_hw) \
132 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
133
134/**
135 * struct clk_rcg2 - root clock generator
136 *
137 * @cmd_rcgr: corresponds to *_CMD_RCGR
138 * @mnd_width: number of bits in m/n/d values
139 * @hid_width: number of bits in half integer divider
140 * @parent_map: map from software's parent index to hardware's src_sel field
141 * @freq_tbl: frequency table
142 * @clkr: regmap clock handle
143 * @lock: register lock
144 *
145 */
146struct clk_rcg2 {
147 u32 cmd_rcgr;
148 u8 mnd_width;
149 u8 hid_width;
150 const u8 *parent_map;
151 const struct freq_tbl *freq_tbl;
152 struct clk_regmap clkr;
153};
154
155#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
156
157extern const struct clk_ops clk_rcg2_ops;
158
159#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
new file mode 100644
index 000000000000..00f878a04d3f
--- /dev/null
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -0,0 +1,291 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/bug.h>
18#include <linux/export.h>
19#include <linux/clk-provider.h>
20#include <linux/delay.h>
21#include <linux/regmap.h>
22
23#include <asm/div64.h>
24
25#include "clk-rcg.h"
26
27#define CMD_REG 0x0
28#define CMD_UPDATE BIT(0)
29#define CMD_ROOT_EN BIT(1)
30#define CMD_DIRTY_CFG BIT(4)
31#define CMD_DIRTY_N BIT(5)
32#define CMD_DIRTY_M BIT(6)
33#define CMD_DIRTY_D BIT(7)
34#define CMD_ROOT_OFF BIT(31)
35
36#define CFG_REG 0x4
37#define CFG_SRC_DIV_SHIFT 0
38#define CFG_SRC_SEL_SHIFT 8
39#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
40#define CFG_MODE_SHIFT 12
41#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
42#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
43
44#define M_REG 0x8
45#define N_REG 0xc
46#define D_REG 0x10
47
48static int clk_rcg2_is_enabled(struct clk_hw *hw)
49{
50 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
51 u32 cmd;
52 int ret;
53
54 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
55 if (ret)
56 return ret;
57
58 return (cmd & CMD_ROOT_OFF) != 0;
59}
60
61static u8 clk_rcg2_get_parent(struct clk_hw *hw)
62{
63 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
64 int num_parents = __clk_get_num_parents(hw->clk);
65 u32 cfg;
66 int i, ret;
67
68 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
69 if (ret)
70 return ret;
71
72 cfg &= CFG_SRC_SEL_MASK;
73 cfg >>= CFG_SRC_SEL_SHIFT;
74
75 for (i = 0; i < num_parents; i++)
76 if (cfg == rcg->parent_map[i])
77 return i;
78
79 return -EINVAL;
80}
81
82static int update_config(struct clk_rcg2 *rcg)
83{
84 int count, ret;
85 u32 cmd;
86 struct clk_hw *hw = &rcg->clkr.hw;
87 const char *name = __clk_get_name(hw->clk);
88
89 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
90 CMD_UPDATE, CMD_UPDATE);
91 if (ret)
92 return ret;
93
94 /* Wait for update to take effect */
95 for (count = 500; count > 0; count--) {
96 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
97 if (ret)
98 return ret;
99 if (!(cmd & CMD_UPDATE))
100 return 0;
101 udelay(1);
102 }
103
104 WARN(1, "%s: rcg didn't update its configuration.", name);
105 return 0;
106}
107
108static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
109{
110 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
111 int ret;
112
113 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
114 CFG_SRC_SEL_MASK,
115 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
116 if (ret)
117 return ret;
118
119 return update_config(rcg);
120}
121
122/*
123 * Calculate m/n:d rate
124 *
125 * parent_rate m
126 * rate = ----------- x ---
127 * hid_div n
128 */
129static unsigned long
130calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
131{
132 if (hid_div) {
133 rate *= 2;
134 rate /= hid_div + 1;
135 }
136
137 if (mode) {
138 u64 tmp = rate;
139 tmp *= m;
140 do_div(tmp, n);
141 rate = tmp;
142 }
143
144 return rate;
145}
146
147static unsigned long
148clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
149{
150 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
151 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
152
153 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
154
155 if (rcg->mnd_width) {
156 mask = BIT(rcg->mnd_width) - 1;
157 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
158 m &= mask;
159 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
160 n = ~n;
161 n &= mask;
162 n += m;
163 mode = cfg & CFG_MODE_MASK;
164 mode >>= CFG_MODE_SHIFT;
165 }
166
167 mask = BIT(rcg->hid_width) - 1;
168 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
169 hid_div &= mask;
170
171 return calc_rate(parent_rate, m, n, mode, hid_div);
172}
173
174static const
175struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
176{
177 if (!f)
178 return NULL;
179
180 for (; f->freq; f++)
181 if (rate <= f->freq)
182 return f;
183
184 return NULL;
185}
186
187static long _freq_tbl_determine_rate(struct clk_hw *hw,
188 const struct freq_tbl *f, unsigned long rate,
189 unsigned long *p_rate, struct clk **p)
190{
191 unsigned long clk_flags;
192
193 f = find_freq(f, rate);
194 if (!f)
195 return -EINVAL;
196
197 clk_flags = __clk_get_flags(hw->clk);
198 *p = clk_get_parent_by_index(hw->clk, f->src);
199 if (clk_flags & CLK_SET_RATE_PARENT) {
200 if (f->pre_div) {
201 rate /= 2;
202 rate *= f->pre_div + 1;
203 }
204
205 if (f->n) {
206 u64 tmp = rate;
207 tmp = tmp * f->n;
208 do_div(tmp, f->m);
209 rate = tmp;
210 }
211 } else {
212 rate = __clk_get_rate(*p);
213 }
214 *p_rate = rate;
215
216 return f->freq;
217}
218
219static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
220 unsigned long *p_rate, struct clk **p)
221{
222 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
223
224 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
225}
226
227static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
228{
229 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
230 const struct freq_tbl *f;
231 u32 cfg, mask;
232 int ret;
233
234 f = find_freq(rcg->freq_tbl, rate);
235 if (!f)
236 return -EINVAL;
237
238 if (rcg->mnd_width && f->n) {
239 mask = BIT(rcg->mnd_width) - 1;
240 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
241 mask, f->m);
242 if (ret)
243 return ret;
244
245 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
246 mask, ~(f->n - f->m));
247 if (ret)
248 return ret;
249
250 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
251 mask, ~f->n);
252 if (ret)
253 return ret;
254 }
255
256 mask = BIT(rcg->hid_width) - 1;
257 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
258 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
259 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
260 if (rcg->mnd_width && f->n)
261 cfg |= CFG_MODE_DUAL_EDGE;
262 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
263 cfg);
264 if (ret)
265 return ret;
266
267 return update_config(rcg);
268}
269
270static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
271 unsigned long parent_rate)
272{
273 return __clk_rcg2_set_rate(hw, rate);
274}
275
276static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
277 unsigned long rate, unsigned long parent_rate, u8 index)
278{
279 return __clk_rcg2_set_rate(hw, rate);
280}
281
282const struct clk_ops clk_rcg2_ops = {
283 .is_enabled = clk_rcg2_is_enabled,
284 .get_parent = clk_rcg2_get_parent,
285 .set_parent = clk_rcg2_set_parent,
286 .recalc_rate = clk_rcg2_recalc_rate,
287 .determine_rate = clk_rcg2_determine_rate,
288 .set_rate = clk_rcg2_set_rate,
289 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
290};
291EXPORT_SYMBOL_GPL(clk_rcg2_ops);
diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c
new file mode 100644
index 000000000000..a58ba39a900c
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap.c
@@ -0,0 +1,114 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/device.h>
15#include <linux/clk-provider.h>
16#include <linux/regmap.h>
17#include <linux/export.h>
18
19#include "clk-regmap.h"
20
21/**
22 * clk_is_enabled_regmap - standard is_enabled() for regmap users
23 *
24 * @hw: clk to operate on
25 *
26 * Clocks that use regmap for their register I/O can set the
27 * enable_reg and enable_mask fields in their struct clk_regmap and then use
28 * this as their is_enabled operation, saving some code.
29 */
30int clk_is_enabled_regmap(struct clk_hw *hw)
31{
32 struct clk_regmap *rclk = to_clk_regmap(hw);
33 unsigned int val;
34 int ret;
35
36 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val);
37 if (ret != 0)
38 return ret;
39
40 if (rclk->enable_is_inverted)
41 return (val & rclk->enable_mask) == 0;
42 else
43 return (val & rclk->enable_mask) != 0;
44}
45EXPORT_SYMBOL_GPL(clk_is_enabled_regmap);
46
47/**
48 * clk_enable_regmap - standard enable() for regmap users
49 *
50 * @hw: clk to operate on
51 *
52 * Clocks that use regmap for their register I/O can set the
53 * enable_reg and enable_mask fields in their struct clk_regmap and then use
54 * this as their enable() operation, saving some code.
55 */
56int clk_enable_regmap(struct clk_hw *hw)
57{
58 struct clk_regmap *rclk = to_clk_regmap(hw);
59 unsigned int val;
60
61 if (rclk->enable_is_inverted)
62 val = 0;
63 else
64 val = rclk->enable_mask;
65
66 return regmap_update_bits(rclk->regmap, rclk->enable_reg,
67 rclk->enable_mask, val);
68}
69EXPORT_SYMBOL_GPL(clk_enable_regmap);
70
71/**
72 * clk_disable_regmap - standard disable() for regmap users
73 *
74 * @hw: clk to operate on
75 *
76 * Clocks that use regmap for their register I/O can set the
77 * enable_reg and enable_mask fields in their struct clk_regmap and then use
78 * this as their disable() operation, saving some code.
79 */
80void clk_disable_regmap(struct clk_hw *hw)
81{
82 struct clk_regmap *rclk = to_clk_regmap(hw);
83 unsigned int val;
84
85 if (rclk->enable_is_inverted)
86 val = rclk->enable_mask;
87 else
88 val = 0;
89
90 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask,
91 val);
92}
93EXPORT_SYMBOL_GPL(clk_disable_regmap);
94
95/**
96 * devm_clk_register_regmap - register a clk_regmap clock
97 *
98 * @rclk: clk to operate on
99 *
100 * Clocks that use regmap for their register I/O should register their
101 * clk_regmap struct via this function so that the regmap is initialized
102 * and so that the clock is registered with the common clock framework.
103 */
104struct clk *devm_clk_register_regmap(struct device *dev,
105 struct clk_regmap *rclk)
106{
107 if (dev && dev_get_regmap(dev, NULL))
108 rclk->regmap = dev_get_regmap(dev, NULL);
109 else if (dev && dev->parent)
110 rclk->regmap = dev_get_regmap(dev->parent, NULL);
111
112 return devm_clk_register(dev, &rclk->hw);
113}
114EXPORT_SYMBOL_GPL(devm_clk_register_regmap);
diff --git a/drivers/clk/qcom/clk-regmap.h b/drivers/clk/qcom/clk-regmap.h
new file mode 100644
index 000000000000..491a63d537df
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_REGMAP_H__
15#define __QCOM_CLK_REGMAP_H__
16
17#include <linux/clk-provider.h>
18
19struct regmap;
20
21/**
22 * struct clk_regmap - regmap supporting clock
23 * @hw: handle between common and hardware-specific interfaces
24 * @regmap: regmap to use for regmap helpers and/or by providers
25 * @enable_reg: register when using regmap enable/disable ops
26 * @enable_mask: mask when using regmap enable/disable ops
27 * @enable_is_inverted: flag to indicate set enable_mask bits to disable
28 * when using clock_enable_regmap and friends APIs.
29 */
30struct clk_regmap {
31 struct clk_hw hw;
32 struct regmap *regmap;
33 unsigned int enable_reg;
34 unsigned int enable_mask;
35 bool enable_is_inverted;
36};
37#define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw)
38
39int clk_is_enabled_regmap(struct clk_hw *hw);
40int clk_enable_regmap(struct clk_hw *hw);
41void clk_disable_regmap(struct clk_hw *hw);
42struct clk *
43devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
44
45#endif
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
new file mode 100644
index 000000000000..bc0b7f1fcfbe
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -0,0 +1,2819 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8660.h>
26#include <dt-bindings/reset/qcom,gcc-msm8660.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34static struct clk_pll pll8 = {
35 .l_reg = 0x3144,
36 .m_reg = 0x3148,
37 .n_reg = 0x314c,
38 .config_reg = 0x3154,
39 .mode_reg = 0x3140,
40 .status_reg = 0x3158,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll8",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48};
49
50static struct clk_regmap pll8_vote = {
51 .enable_reg = 0x34c0,
52 .enable_mask = BIT(8),
53 .hw.init = &(struct clk_init_data){
54 .name = "pll8_vote",
55 .parent_names = (const char *[]){ "pll8" },
56 .num_parents = 1,
57 .ops = &clk_pll_vote_ops,
58 },
59};
60
61#define P_PXO 0
62#define P_PLL8 1
63#define P_CXO 2
64
65static const u8 gcc_pxo_pll8_map[] = {
66 [P_PXO] = 0,
67 [P_PLL8] = 3,
68};
69
70static const char *gcc_pxo_pll8[] = {
71 "pxo",
72 "pll8_vote",
73};
74
75static const u8 gcc_pxo_pll8_cxo_map[] = {
76 [P_PXO] = 0,
77 [P_PLL8] = 3,
78 [P_CXO] = 5,
79};
80
81static const char *gcc_pxo_pll8_cxo[] = {
82 "pxo",
83 "pll8_vote",
84 "cxo",
85};
86
87static struct freq_tbl clk_tbl_gsbi_uart[] = {
88 { 1843200, P_PLL8, 2, 6, 625 },
89 { 3686400, P_PLL8, 2, 12, 625 },
90 { 7372800, P_PLL8, 2, 24, 625 },
91 { 14745600, P_PLL8, 2, 48, 625 },
92 { 16000000, P_PLL8, 4, 1, 6 },
93 { 24000000, P_PLL8, 4, 1, 4 },
94 { 32000000, P_PLL8, 4, 1, 3 },
95 { 40000000, P_PLL8, 1, 5, 48 },
96 { 46400000, P_PLL8, 1, 29, 240 },
97 { 48000000, P_PLL8, 4, 1, 2 },
98 { 51200000, P_PLL8, 1, 2, 15 },
99 { 56000000, P_PLL8, 1, 7, 48 },
100 { 58982400, P_PLL8, 1, 96, 625 },
101 { 64000000, P_PLL8, 2, 1, 3 },
102 { }
103};
104
105static struct clk_rcg gsbi1_uart_src = {
106 .ns_reg = 0x29d4,
107 .md_reg = 0x29d0,
108 .mn = {
109 .mnctr_en_bit = 8,
110 .mnctr_reset_bit = 7,
111 .mnctr_mode_shift = 5,
112 .n_val_shift = 16,
113 .m_val_shift = 16,
114 .width = 16,
115 },
116 .p = {
117 .pre_div_shift = 3,
118 .pre_div_width = 2,
119 },
120 .s = {
121 .src_sel_shift = 0,
122 .parent_map = gcc_pxo_pll8_map,
123 },
124 .freq_tbl = clk_tbl_gsbi_uart,
125 .clkr = {
126 .enable_reg = 0x29d4,
127 .enable_mask = BIT(11),
128 .hw.init = &(struct clk_init_data){
129 .name = "gsbi1_uart_src",
130 .parent_names = gcc_pxo_pll8,
131 .num_parents = 2,
132 .ops = &clk_rcg_ops,
133 .flags = CLK_SET_PARENT_GATE,
134 },
135 },
136};
137
138static struct clk_branch gsbi1_uart_clk = {
139 .halt_reg = 0x2fcc,
140 .halt_bit = 10,
141 .clkr = {
142 .enable_reg = 0x29d4,
143 .enable_mask = BIT(9),
144 .hw.init = &(struct clk_init_data){
145 .name = "gsbi1_uart_clk",
146 .parent_names = (const char *[]){
147 "gsbi1_uart_src",
148 },
149 .num_parents = 1,
150 .ops = &clk_branch_ops,
151 .flags = CLK_SET_RATE_PARENT,
152 },
153 },
154};
155
156static struct clk_rcg gsbi2_uart_src = {
157 .ns_reg = 0x29f4,
158 .md_reg = 0x29f0,
159 .mn = {
160 .mnctr_en_bit = 8,
161 .mnctr_reset_bit = 7,
162 .mnctr_mode_shift = 5,
163 .n_val_shift = 16,
164 .m_val_shift = 16,
165 .width = 16,
166 },
167 .p = {
168 .pre_div_shift = 3,
169 .pre_div_width = 2,
170 },
171 .s = {
172 .src_sel_shift = 0,
173 .parent_map = gcc_pxo_pll8_map,
174 },
175 .freq_tbl = clk_tbl_gsbi_uart,
176 .clkr = {
177 .enable_reg = 0x29f4,
178 .enable_mask = BIT(11),
179 .hw.init = &(struct clk_init_data){
180 .name = "gsbi2_uart_src",
181 .parent_names = gcc_pxo_pll8,
182 .num_parents = 2,
183 .ops = &clk_rcg_ops,
184 .flags = CLK_SET_PARENT_GATE,
185 },
186 },
187};
188
189static struct clk_branch gsbi2_uart_clk = {
190 .halt_reg = 0x2fcc,
191 .halt_bit = 6,
192 .clkr = {
193 .enable_reg = 0x29f4,
194 .enable_mask = BIT(9),
195 .hw.init = &(struct clk_init_data){
196 .name = "gsbi2_uart_clk",
197 .parent_names = (const char *[]){
198 "gsbi2_uart_src",
199 },
200 .num_parents = 1,
201 .ops = &clk_branch_ops,
202 .flags = CLK_SET_RATE_PARENT,
203 },
204 },
205};
206
207static struct clk_rcg gsbi3_uart_src = {
208 .ns_reg = 0x2a14,
209 .md_reg = 0x2a10,
210 .mn = {
211 .mnctr_en_bit = 8,
212 .mnctr_reset_bit = 7,
213 .mnctr_mode_shift = 5,
214 .n_val_shift = 16,
215 .m_val_shift = 16,
216 .width = 16,
217 },
218 .p = {
219 .pre_div_shift = 3,
220 .pre_div_width = 2,
221 },
222 .s = {
223 .src_sel_shift = 0,
224 .parent_map = gcc_pxo_pll8_map,
225 },
226 .freq_tbl = clk_tbl_gsbi_uart,
227 .clkr = {
228 .enable_reg = 0x2a14,
229 .enable_mask = BIT(11),
230 .hw.init = &(struct clk_init_data){
231 .name = "gsbi3_uart_src",
232 .parent_names = gcc_pxo_pll8,
233 .num_parents = 2,
234 .ops = &clk_rcg_ops,
235 .flags = CLK_SET_PARENT_GATE,
236 },
237 },
238};
239
240static struct clk_branch gsbi3_uart_clk = {
241 .halt_reg = 0x2fcc,
242 .halt_bit = 2,
243 .clkr = {
244 .enable_reg = 0x2a14,
245 .enable_mask = BIT(9),
246 .hw.init = &(struct clk_init_data){
247 .name = "gsbi3_uart_clk",
248 .parent_names = (const char *[]){
249 "gsbi3_uart_src",
250 },
251 .num_parents = 1,
252 .ops = &clk_branch_ops,
253 .flags = CLK_SET_RATE_PARENT,
254 },
255 },
256};
257
258static struct clk_rcg gsbi4_uart_src = {
259 .ns_reg = 0x2a34,
260 .md_reg = 0x2a30,
261 .mn = {
262 .mnctr_en_bit = 8,
263 .mnctr_reset_bit = 7,
264 .mnctr_mode_shift = 5,
265 .n_val_shift = 16,
266 .m_val_shift = 16,
267 .width = 16,
268 },
269 .p = {
270 .pre_div_shift = 3,
271 .pre_div_width = 2,
272 },
273 .s = {
274 .src_sel_shift = 0,
275 .parent_map = gcc_pxo_pll8_map,
276 },
277 .freq_tbl = clk_tbl_gsbi_uart,
278 .clkr = {
279 .enable_reg = 0x2a34,
280 .enable_mask = BIT(11),
281 .hw.init = &(struct clk_init_data){
282 .name = "gsbi4_uart_src",
283 .parent_names = gcc_pxo_pll8,
284 .num_parents = 2,
285 .ops = &clk_rcg_ops,
286 .flags = CLK_SET_PARENT_GATE,
287 },
288 },
289};
290
291static struct clk_branch gsbi4_uart_clk = {
292 .halt_reg = 0x2fd0,
293 .halt_bit = 26,
294 .clkr = {
295 .enable_reg = 0x2a34,
296 .enable_mask = BIT(9),
297 .hw.init = &(struct clk_init_data){
298 .name = "gsbi4_uart_clk",
299 .parent_names = (const char *[]){
300 "gsbi4_uart_src",
301 },
302 .num_parents = 1,
303 .ops = &clk_branch_ops,
304 .flags = CLK_SET_RATE_PARENT,
305 },
306 },
307};
308
309static struct clk_rcg gsbi5_uart_src = {
310 .ns_reg = 0x2a54,
311 .md_reg = 0x2a50,
312 .mn = {
313 .mnctr_en_bit = 8,
314 .mnctr_reset_bit = 7,
315 .mnctr_mode_shift = 5,
316 .n_val_shift = 16,
317 .m_val_shift = 16,
318 .width = 16,
319 },
320 .p = {
321 .pre_div_shift = 3,
322 .pre_div_width = 2,
323 },
324 .s = {
325 .src_sel_shift = 0,
326 .parent_map = gcc_pxo_pll8_map,
327 },
328 .freq_tbl = clk_tbl_gsbi_uart,
329 .clkr = {
330 .enable_reg = 0x2a54,
331 .enable_mask = BIT(11),
332 .hw.init = &(struct clk_init_data){
333 .name = "gsbi5_uart_src",
334 .parent_names = gcc_pxo_pll8,
335 .num_parents = 2,
336 .ops = &clk_rcg_ops,
337 .flags = CLK_SET_PARENT_GATE,
338 },
339 },
340};
341
342static struct clk_branch gsbi5_uart_clk = {
343 .halt_reg = 0x2fd0,
344 .halt_bit = 22,
345 .clkr = {
346 .enable_reg = 0x2a54,
347 .enable_mask = BIT(9),
348 .hw.init = &(struct clk_init_data){
349 .name = "gsbi5_uart_clk",
350 .parent_names = (const char *[]){
351 "gsbi5_uart_src",
352 },
353 .num_parents = 1,
354 .ops = &clk_branch_ops,
355 .flags = CLK_SET_RATE_PARENT,
356 },
357 },
358};
359
360static struct clk_rcg gsbi6_uart_src = {
361 .ns_reg = 0x2a74,
362 .md_reg = 0x2a70,
363 .mn = {
364 .mnctr_en_bit = 8,
365 .mnctr_reset_bit = 7,
366 .mnctr_mode_shift = 5,
367 .n_val_shift = 16,
368 .m_val_shift = 16,
369 .width = 16,
370 },
371 .p = {
372 .pre_div_shift = 3,
373 .pre_div_width = 2,
374 },
375 .s = {
376 .src_sel_shift = 0,
377 .parent_map = gcc_pxo_pll8_map,
378 },
379 .freq_tbl = clk_tbl_gsbi_uart,
380 .clkr = {
381 .enable_reg = 0x2a74,
382 .enable_mask = BIT(11),
383 .hw.init = &(struct clk_init_data){
384 .name = "gsbi6_uart_src",
385 .parent_names = gcc_pxo_pll8,
386 .num_parents = 2,
387 .ops = &clk_rcg_ops,
388 .flags = CLK_SET_PARENT_GATE,
389 },
390 },
391};
392
393static struct clk_branch gsbi6_uart_clk = {
394 .halt_reg = 0x2fd0,
395 .halt_bit = 18,
396 .clkr = {
397 .enable_reg = 0x2a74,
398 .enable_mask = BIT(9),
399 .hw.init = &(struct clk_init_data){
400 .name = "gsbi6_uart_clk",
401 .parent_names = (const char *[]){
402 "gsbi6_uart_src",
403 },
404 .num_parents = 1,
405 .ops = &clk_branch_ops,
406 .flags = CLK_SET_RATE_PARENT,
407 },
408 },
409};
410
411static struct clk_rcg gsbi7_uart_src = {
412 .ns_reg = 0x2a94,
413 .md_reg = 0x2a90,
414 .mn = {
415 .mnctr_en_bit = 8,
416 .mnctr_reset_bit = 7,
417 .mnctr_mode_shift = 5,
418 .n_val_shift = 16,
419 .m_val_shift = 16,
420 .width = 16,
421 },
422 .p = {
423 .pre_div_shift = 3,
424 .pre_div_width = 2,
425 },
426 .s = {
427 .src_sel_shift = 0,
428 .parent_map = gcc_pxo_pll8_map,
429 },
430 .freq_tbl = clk_tbl_gsbi_uart,
431 .clkr = {
432 .enable_reg = 0x2a94,
433 .enable_mask = BIT(11),
434 .hw.init = &(struct clk_init_data){
435 .name = "gsbi7_uart_src",
436 .parent_names = gcc_pxo_pll8,
437 .num_parents = 2,
438 .ops = &clk_rcg_ops,
439 .flags = CLK_SET_PARENT_GATE,
440 },
441 },
442};
443
444static struct clk_branch gsbi7_uart_clk = {
445 .halt_reg = 0x2fd0,
446 .halt_bit = 14,
447 .clkr = {
448 .enable_reg = 0x2a94,
449 .enable_mask = BIT(9),
450 .hw.init = &(struct clk_init_data){
451 .name = "gsbi7_uart_clk",
452 .parent_names = (const char *[]){
453 "gsbi7_uart_src",
454 },
455 .num_parents = 1,
456 .ops = &clk_branch_ops,
457 .flags = CLK_SET_RATE_PARENT,
458 },
459 },
460};
461
462static struct clk_rcg gsbi8_uart_src = {
463 .ns_reg = 0x2ab4,
464 .md_reg = 0x2ab0,
465 .mn = {
466 .mnctr_en_bit = 8,
467 .mnctr_reset_bit = 7,
468 .mnctr_mode_shift = 5,
469 .n_val_shift = 16,
470 .m_val_shift = 16,
471 .width = 16,
472 },
473 .p = {
474 .pre_div_shift = 3,
475 .pre_div_width = 2,
476 },
477 .s = {
478 .src_sel_shift = 0,
479 .parent_map = gcc_pxo_pll8_map,
480 },
481 .freq_tbl = clk_tbl_gsbi_uart,
482 .clkr = {
483 .enable_reg = 0x2ab4,
484 .enable_mask = BIT(11),
485 .hw.init = &(struct clk_init_data){
486 .name = "gsbi8_uart_src",
487 .parent_names = gcc_pxo_pll8,
488 .num_parents = 2,
489 .ops = &clk_rcg_ops,
490 .flags = CLK_SET_PARENT_GATE,
491 },
492 },
493};
494
495static struct clk_branch gsbi8_uart_clk = {
496 .halt_reg = 0x2fd0,
497 .halt_bit = 10,
498 .clkr = {
499 .enable_reg = 0x2ab4,
500 .enable_mask = BIT(9),
501 .hw.init = &(struct clk_init_data){
502 .name = "gsbi8_uart_clk",
503 .parent_names = (const char *[]){ "gsbi8_uart_src" },
504 .num_parents = 1,
505 .ops = &clk_branch_ops,
506 .flags = CLK_SET_RATE_PARENT,
507 },
508 },
509};
510
511static struct clk_rcg gsbi9_uart_src = {
512 .ns_reg = 0x2ad4,
513 .md_reg = 0x2ad0,
514 .mn = {
515 .mnctr_en_bit = 8,
516 .mnctr_reset_bit = 7,
517 .mnctr_mode_shift = 5,
518 .n_val_shift = 16,
519 .m_val_shift = 16,
520 .width = 16,
521 },
522 .p = {
523 .pre_div_shift = 3,
524 .pre_div_width = 2,
525 },
526 .s = {
527 .src_sel_shift = 0,
528 .parent_map = gcc_pxo_pll8_map,
529 },
530 .freq_tbl = clk_tbl_gsbi_uart,
531 .clkr = {
532 .enable_reg = 0x2ad4,
533 .enable_mask = BIT(11),
534 .hw.init = &(struct clk_init_data){
535 .name = "gsbi9_uart_src",
536 .parent_names = gcc_pxo_pll8,
537 .num_parents = 2,
538 .ops = &clk_rcg_ops,
539 .flags = CLK_SET_PARENT_GATE,
540 },
541 },
542};
543
544static struct clk_branch gsbi9_uart_clk = {
545 .halt_reg = 0x2fd0,
546 .halt_bit = 6,
547 .clkr = {
548 .enable_reg = 0x2ad4,
549 .enable_mask = BIT(9),
550 .hw.init = &(struct clk_init_data){
551 .name = "gsbi9_uart_clk",
552 .parent_names = (const char *[]){ "gsbi9_uart_src" },
553 .num_parents = 1,
554 .ops = &clk_branch_ops,
555 .flags = CLK_SET_RATE_PARENT,
556 },
557 },
558};
559
560static struct clk_rcg gsbi10_uart_src = {
561 .ns_reg = 0x2af4,
562 .md_reg = 0x2af0,
563 .mn = {
564 .mnctr_en_bit = 8,
565 .mnctr_reset_bit = 7,
566 .mnctr_mode_shift = 5,
567 .n_val_shift = 16,
568 .m_val_shift = 16,
569 .width = 16,
570 },
571 .p = {
572 .pre_div_shift = 3,
573 .pre_div_width = 2,
574 },
575 .s = {
576 .src_sel_shift = 0,
577 .parent_map = gcc_pxo_pll8_map,
578 },
579 .freq_tbl = clk_tbl_gsbi_uart,
580 .clkr = {
581 .enable_reg = 0x2af4,
582 .enable_mask = BIT(11),
583 .hw.init = &(struct clk_init_data){
584 .name = "gsbi10_uart_src",
585 .parent_names = gcc_pxo_pll8,
586 .num_parents = 2,
587 .ops = &clk_rcg_ops,
588 .flags = CLK_SET_PARENT_GATE,
589 },
590 },
591};
592
593static struct clk_branch gsbi10_uart_clk = {
594 .halt_reg = 0x2fd0,
595 .halt_bit = 2,
596 .clkr = {
597 .enable_reg = 0x2af4,
598 .enable_mask = BIT(9),
599 .hw.init = &(struct clk_init_data){
600 .name = "gsbi10_uart_clk",
601 .parent_names = (const char *[]){ "gsbi10_uart_src" },
602 .num_parents = 1,
603 .ops = &clk_branch_ops,
604 .flags = CLK_SET_RATE_PARENT,
605 },
606 },
607};
608
609static struct clk_rcg gsbi11_uart_src = {
610 .ns_reg = 0x2b14,
611 .md_reg = 0x2b10,
612 .mn = {
613 .mnctr_en_bit = 8,
614 .mnctr_reset_bit = 7,
615 .mnctr_mode_shift = 5,
616 .n_val_shift = 16,
617 .m_val_shift = 16,
618 .width = 16,
619 },
620 .p = {
621 .pre_div_shift = 3,
622 .pre_div_width = 2,
623 },
624 .s = {
625 .src_sel_shift = 0,
626 .parent_map = gcc_pxo_pll8_map,
627 },
628 .freq_tbl = clk_tbl_gsbi_uart,
629 .clkr = {
630 .enable_reg = 0x2b14,
631 .enable_mask = BIT(11),
632 .hw.init = &(struct clk_init_data){
633 .name = "gsbi11_uart_src",
634 .parent_names = gcc_pxo_pll8,
635 .num_parents = 2,
636 .ops = &clk_rcg_ops,
637 .flags = CLK_SET_PARENT_GATE,
638 },
639 },
640};
641
642static struct clk_branch gsbi11_uart_clk = {
643 .halt_reg = 0x2fd4,
644 .halt_bit = 17,
645 .clkr = {
646 .enable_reg = 0x2b14,
647 .enable_mask = BIT(9),
648 .hw.init = &(struct clk_init_data){
649 .name = "gsbi11_uart_clk",
650 .parent_names = (const char *[]){ "gsbi11_uart_src" },
651 .num_parents = 1,
652 .ops = &clk_branch_ops,
653 .flags = CLK_SET_RATE_PARENT,
654 },
655 },
656};
657
658static struct clk_rcg gsbi12_uart_src = {
659 .ns_reg = 0x2b34,
660 .md_reg = 0x2b30,
661 .mn = {
662 .mnctr_en_bit = 8,
663 .mnctr_reset_bit = 7,
664 .mnctr_mode_shift = 5,
665 .n_val_shift = 16,
666 .m_val_shift = 16,
667 .width = 16,
668 },
669 .p = {
670 .pre_div_shift = 3,
671 .pre_div_width = 2,
672 },
673 .s = {
674 .src_sel_shift = 0,
675 .parent_map = gcc_pxo_pll8_map,
676 },
677 .freq_tbl = clk_tbl_gsbi_uart,
678 .clkr = {
679 .enable_reg = 0x2b34,
680 .enable_mask = BIT(11),
681 .hw.init = &(struct clk_init_data){
682 .name = "gsbi12_uart_src",
683 .parent_names = gcc_pxo_pll8,
684 .num_parents = 2,
685 .ops = &clk_rcg_ops,
686 .flags = CLK_SET_PARENT_GATE,
687 },
688 },
689};
690
691static struct clk_branch gsbi12_uart_clk = {
692 .halt_reg = 0x2fd4,
693 .halt_bit = 13,
694 .clkr = {
695 .enable_reg = 0x2b34,
696 .enable_mask = BIT(9),
697 .hw.init = &(struct clk_init_data){
698 .name = "gsbi12_uart_clk",
699 .parent_names = (const char *[]){ "gsbi12_uart_src" },
700 .num_parents = 1,
701 .ops = &clk_branch_ops,
702 .flags = CLK_SET_RATE_PARENT,
703 },
704 },
705};
706
707static struct freq_tbl clk_tbl_gsbi_qup[] = {
708 { 1100000, P_PXO, 1, 2, 49 },
709 { 5400000, P_PXO, 1, 1, 5 },
710 { 10800000, P_PXO, 1, 2, 5 },
711 { 15060000, P_PLL8, 1, 2, 51 },
712 { 24000000, P_PLL8, 4, 1, 4 },
713 { 25600000, P_PLL8, 1, 1, 15 },
714 { 27000000, P_PXO, 1, 0, 0 },
715 { 48000000, P_PLL8, 4, 1, 2 },
716 { 51200000, P_PLL8, 1, 2, 15 },
717 { }
718};
719
720static struct clk_rcg gsbi1_qup_src = {
721 .ns_reg = 0x29cc,
722 .md_reg = 0x29c8,
723 .mn = {
724 .mnctr_en_bit = 8,
725 .mnctr_reset_bit = 7,
726 .mnctr_mode_shift = 5,
727 .n_val_shift = 16,
728 .m_val_shift = 16,
729 .width = 8,
730 },
731 .p = {
732 .pre_div_shift = 3,
733 .pre_div_width = 2,
734 },
735 .s = {
736 .src_sel_shift = 0,
737 .parent_map = gcc_pxo_pll8_map,
738 },
739 .freq_tbl = clk_tbl_gsbi_qup,
740 .clkr = {
741 .enable_reg = 0x29cc,
742 .enable_mask = BIT(11),
743 .hw.init = &(struct clk_init_data){
744 .name = "gsbi1_qup_src",
745 .parent_names = gcc_pxo_pll8,
746 .num_parents = 2,
747 .ops = &clk_rcg_ops,
748 .flags = CLK_SET_PARENT_GATE,
749 },
750 },
751};
752
753static struct clk_branch gsbi1_qup_clk = {
754 .halt_reg = 0x2fcc,
755 .halt_bit = 9,
756 .clkr = {
757 .enable_reg = 0x29cc,
758 .enable_mask = BIT(9),
759 .hw.init = &(struct clk_init_data){
760 .name = "gsbi1_qup_clk",
761 .parent_names = (const char *[]){ "gsbi1_qup_src" },
762 .num_parents = 1,
763 .ops = &clk_branch_ops,
764 .flags = CLK_SET_RATE_PARENT,
765 },
766 },
767};
768
769static struct clk_rcg gsbi2_qup_src = {
770 .ns_reg = 0x29ec,
771 .md_reg = 0x29e8,
772 .mn = {
773 .mnctr_en_bit = 8,
774 .mnctr_reset_bit = 7,
775 .mnctr_mode_shift = 5,
776 .n_val_shift = 16,
777 .m_val_shift = 16,
778 .width = 8,
779 },
780 .p = {
781 .pre_div_shift = 3,
782 .pre_div_width = 2,
783 },
784 .s = {
785 .src_sel_shift = 0,
786 .parent_map = gcc_pxo_pll8_map,
787 },
788 .freq_tbl = clk_tbl_gsbi_qup,
789 .clkr = {
790 .enable_reg = 0x29ec,
791 .enable_mask = BIT(11),
792 .hw.init = &(struct clk_init_data){
793 .name = "gsbi2_qup_src",
794 .parent_names = gcc_pxo_pll8,
795 .num_parents = 2,
796 .ops = &clk_rcg_ops,
797 .flags = CLK_SET_PARENT_GATE,
798 },
799 },
800};
801
802static struct clk_branch gsbi2_qup_clk = {
803 .halt_reg = 0x2fcc,
804 .halt_bit = 4,
805 .clkr = {
806 .enable_reg = 0x29ec,
807 .enable_mask = BIT(9),
808 .hw.init = &(struct clk_init_data){
809 .name = "gsbi2_qup_clk",
810 .parent_names = (const char *[]){ "gsbi2_qup_src" },
811 .num_parents = 1,
812 .ops = &clk_branch_ops,
813 .flags = CLK_SET_RATE_PARENT,
814 },
815 },
816};
817
818static struct clk_rcg gsbi3_qup_src = {
819 .ns_reg = 0x2a0c,
820 .md_reg = 0x2a08,
821 .mn = {
822 .mnctr_en_bit = 8,
823 .mnctr_reset_bit = 7,
824 .mnctr_mode_shift = 5,
825 .n_val_shift = 16,
826 .m_val_shift = 16,
827 .width = 8,
828 },
829 .p = {
830 .pre_div_shift = 3,
831 .pre_div_width = 2,
832 },
833 .s = {
834 .src_sel_shift = 0,
835 .parent_map = gcc_pxo_pll8_map,
836 },
837 .freq_tbl = clk_tbl_gsbi_qup,
838 .clkr = {
839 .enable_reg = 0x2a0c,
840 .enable_mask = BIT(11),
841 .hw.init = &(struct clk_init_data){
842 .name = "gsbi3_qup_src",
843 .parent_names = gcc_pxo_pll8,
844 .num_parents = 2,
845 .ops = &clk_rcg_ops,
846 .flags = CLK_SET_PARENT_GATE,
847 },
848 },
849};
850
851static struct clk_branch gsbi3_qup_clk = {
852 .halt_reg = 0x2fcc,
853 .halt_bit = 0,
854 .clkr = {
855 .enable_reg = 0x2a0c,
856 .enable_mask = BIT(9),
857 .hw.init = &(struct clk_init_data){
858 .name = "gsbi3_qup_clk",
859 .parent_names = (const char *[]){ "gsbi3_qup_src" },
860 .num_parents = 1,
861 .ops = &clk_branch_ops,
862 .flags = CLK_SET_RATE_PARENT,
863 },
864 },
865};
866
867static struct clk_rcg gsbi4_qup_src = {
868 .ns_reg = 0x2a2c,
869 .md_reg = 0x2a28,
870 .mn = {
871 .mnctr_en_bit = 8,
872 .mnctr_reset_bit = 7,
873 .mnctr_mode_shift = 5,
874 .n_val_shift = 16,
875 .m_val_shift = 16,
876 .width = 8,
877 },
878 .p = {
879 .pre_div_shift = 3,
880 .pre_div_width = 2,
881 },
882 .s = {
883 .src_sel_shift = 0,
884 .parent_map = gcc_pxo_pll8_map,
885 },
886 .freq_tbl = clk_tbl_gsbi_qup,
887 .clkr = {
888 .enable_reg = 0x2a2c,
889 .enable_mask = BIT(11),
890 .hw.init = &(struct clk_init_data){
891 .name = "gsbi4_qup_src",
892 .parent_names = gcc_pxo_pll8,
893 .num_parents = 2,
894 .ops = &clk_rcg_ops,
895 .flags = CLK_SET_PARENT_GATE,
896 },
897 },
898};
899
900static struct clk_branch gsbi4_qup_clk = {
901 .halt_reg = 0x2fd0,
902 .halt_bit = 24,
903 .clkr = {
904 .enable_reg = 0x2a2c,
905 .enable_mask = BIT(9),
906 .hw.init = &(struct clk_init_data){
907 .name = "gsbi4_qup_clk",
908 .parent_names = (const char *[]){ "gsbi4_qup_src" },
909 .num_parents = 1,
910 .ops = &clk_branch_ops,
911 .flags = CLK_SET_RATE_PARENT,
912 },
913 },
914};
915
916static struct clk_rcg gsbi5_qup_src = {
917 .ns_reg = 0x2a4c,
918 .md_reg = 0x2a48,
919 .mn = {
920 .mnctr_en_bit = 8,
921 .mnctr_reset_bit = 7,
922 .mnctr_mode_shift = 5,
923 .n_val_shift = 16,
924 .m_val_shift = 16,
925 .width = 8,
926 },
927 .p = {
928 .pre_div_shift = 3,
929 .pre_div_width = 2,
930 },
931 .s = {
932 .src_sel_shift = 0,
933 .parent_map = gcc_pxo_pll8_map,
934 },
935 .freq_tbl = clk_tbl_gsbi_qup,
936 .clkr = {
937 .enable_reg = 0x2a4c,
938 .enable_mask = BIT(11),
939 .hw.init = &(struct clk_init_data){
940 .name = "gsbi5_qup_src",
941 .parent_names = gcc_pxo_pll8,
942 .num_parents = 2,
943 .ops = &clk_rcg_ops,
944 .flags = CLK_SET_PARENT_GATE,
945 },
946 },
947};
948
949static struct clk_branch gsbi5_qup_clk = {
950 .halt_reg = 0x2fd0,
951 .halt_bit = 20,
952 .clkr = {
953 .enable_reg = 0x2a4c,
954 .enable_mask = BIT(9),
955 .hw.init = &(struct clk_init_data){
956 .name = "gsbi5_qup_clk",
957 .parent_names = (const char *[]){ "gsbi5_qup_src" },
958 .num_parents = 1,
959 .ops = &clk_branch_ops,
960 .flags = CLK_SET_RATE_PARENT,
961 },
962 },
963};
964
965static struct clk_rcg gsbi6_qup_src = {
966 .ns_reg = 0x2a6c,
967 .md_reg = 0x2a68,
968 .mn = {
969 .mnctr_en_bit = 8,
970 .mnctr_reset_bit = 7,
971 .mnctr_mode_shift = 5,
972 .n_val_shift = 16,
973 .m_val_shift = 16,
974 .width = 8,
975 },
976 .p = {
977 .pre_div_shift = 3,
978 .pre_div_width = 2,
979 },
980 .s = {
981 .src_sel_shift = 0,
982 .parent_map = gcc_pxo_pll8_map,
983 },
984 .freq_tbl = clk_tbl_gsbi_qup,
985 .clkr = {
986 .enable_reg = 0x2a6c,
987 .enable_mask = BIT(11),
988 .hw.init = &(struct clk_init_data){
989 .name = "gsbi6_qup_src",
990 .parent_names = gcc_pxo_pll8,
991 .num_parents = 2,
992 .ops = &clk_rcg_ops,
993 .flags = CLK_SET_PARENT_GATE,
994 },
995 },
996};
997
998static struct clk_branch gsbi6_qup_clk = {
999 .halt_reg = 0x2fd0,
1000 .halt_bit = 16,
1001 .clkr = {
1002 .enable_reg = 0x2a6c,
1003 .enable_mask = BIT(9),
1004 .hw.init = &(struct clk_init_data){
1005 .name = "gsbi6_qup_clk",
1006 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1007 .num_parents = 1,
1008 .ops = &clk_branch_ops,
1009 .flags = CLK_SET_RATE_PARENT,
1010 },
1011 },
1012};
1013
1014static struct clk_rcg gsbi7_qup_src = {
1015 .ns_reg = 0x2a8c,
1016 .md_reg = 0x2a88,
1017 .mn = {
1018 .mnctr_en_bit = 8,
1019 .mnctr_reset_bit = 7,
1020 .mnctr_mode_shift = 5,
1021 .n_val_shift = 16,
1022 .m_val_shift = 16,
1023 .width = 8,
1024 },
1025 .p = {
1026 .pre_div_shift = 3,
1027 .pre_div_width = 2,
1028 },
1029 .s = {
1030 .src_sel_shift = 0,
1031 .parent_map = gcc_pxo_pll8_map,
1032 },
1033 .freq_tbl = clk_tbl_gsbi_qup,
1034 .clkr = {
1035 .enable_reg = 0x2a8c,
1036 .enable_mask = BIT(11),
1037 .hw.init = &(struct clk_init_data){
1038 .name = "gsbi7_qup_src",
1039 .parent_names = gcc_pxo_pll8,
1040 .num_parents = 2,
1041 .ops = &clk_rcg_ops,
1042 .flags = CLK_SET_PARENT_GATE,
1043 },
1044 },
1045};
1046
1047static struct clk_branch gsbi7_qup_clk = {
1048 .halt_reg = 0x2fd0,
1049 .halt_bit = 12,
1050 .clkr = {
1051 .enable_reg = 0x2a8c,
1052 .enable_mask = BIT(9),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "gsbi7_qup_clk",
1055 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1056 .num_parents = 1,
1057 .ops = &clk_branch_ops,
1058 .flags = CLK_SET_RATE_PARENT,
1059 },
1060 },
1061};
1062
1063static struct clk_rcg gsbi8_qup_src = {
1064 .ns_reg = 0x2aac,
1065 .md_reg = 0x2aa8,
1066 .mn = {
1067 .mnctr_en_bit = 8,
1068 .mnctr_reset_bit = 7,
1069 .mnctr_mode_shift = 5,
1070 .n_val_shift = 16,
1071 .m_val_shift = 16,
1072 .width = 8,
1073 },
1074 .p = {
1075 .pre_div_shift = 3,
1076 .pre_div_width = 2,
1077 },
1078 .s = {
1079 .src_sel_shift = 0,
1080 .parent_map = gcc_pxo_pll8_map,
1081 },
1082 .freq_tbl = clk_tbl_gsbi_qup,
1083 .clkr = {
1084 .enable_reg = 0x2aac,
1085 .enable_mask = BIT(11),
1086 .hw.init = &(struct clk_init_data){
1087 .name = "gsbi8_qup_src",
1088 .parent_names = gcc_pxo_pll8,
1089 .num_parents = 2,
1090 .ops = &clk_rcg_ops,
1091 .flags = CLK_SET_PARENT_GATE,
1092 },
1093 },
1094};
1095
1096static struct clk_branch gsbi8_qup_clk = {
1097 .halt_reg = 0x2fd0,
1098 .halt_bit = 8,
1099 .clkr = {
1100 .enable_reg = 0x2aac,
1101 .enable_mask = BIT(9),
1102 .hw.init = &(struct clk_init_data){
1103 .name = "gsbi8_qup_clk",
1104 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1105 .num_parents = 1,
1106 .ops = &clk_branch_ops,
1107 .flags = CLK_SET_RATE_PARENT,
1108 },
1109 },
1110};
1111
1112static struct clk_rcg gsbi9_qup_src = {
1113 .ns_reg = 0x2acc,
1114 .md_reg = 0x2ac8,
1115 .mn = {
1116 .mnctr_en_bit = 8,
1117 .mnctr_reset_bit = 7,
1118 .mnctr_mode_shift = 5,
1119 .n_val_shift = 16,
1120 .m_val_shift = 16,
1121 .width = 8,
1122 },
1123 .p = {
1124 .pre_div_shift = 3,
1125 .pre_div_width = 2,
1126 },
1127 .s = {
1128 .src_sel_shift = 0,
1129 .parent_map = gcc_pxo_pll8_map,
1130 },
1131 .freq_tbl = clk_tbl_gsbi_qup,
1132 .clkr = {
1133 .enable_reg = 0x2acc,
1134 .enable_mask = BIT(11),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "gsbi9_qup_src",
1137 .parent_names = gcc_pxo_pll8,
1138 .num_parents = 2,
1139 .ops = &clk_rcg_ops,
1140 .flags = CLK_SET_PARENT_GATE,
1141 },
1142 },
1143};
1144
1145static struct clk_branch gsbi9_qup_clk = {
1146 .halt_reg = 0x2fd0,
1147 .halt_bit = 4,
1148 .clkr = {
1149 .enable_reg = 0x2acc,
1150 .enable_mask = BIT(9),
1151 .hw.init = &(struct clk_init_data){
1152 .name = "gsbi9_qup_clk",
1153 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1154 .num_parents = 1,
1155 .ops = &clk_branch_ops,
1156 .flags = CLK_SET_RATE_PARENT,
1157 },
1158 },
1159};
1160
1161static struct clk_rcg gsbi10_qup_src = {
1162 .ns_reg = 0x2aec,
1163 .md_reg = 0x2ae8,
1164 .mn = {
1165 .mnctr_en_bit = 8,
1166 .mnctr_reset_bit = 7,
1167 .mnctr_mode_shift = 5,
1168 .n_val_shift = 16,
1169 .m_val_shift = 16,
1170 .width = 8,
1171 },
1172 .p = {
1173 .pre_div_shift = 3,
1174 .pre_div_width = 2,
1175 },
1176 .s = {
1177 .src_sel_shift = 0,
1178 .parent_map = gcc_pxo_pll8_map,
1179 },
1180 .freq_tbl = clk_tbl_gsbi_qup,
1181 .clkr = {
1182 .enable_reg = 0x2aec,
1183 .enable_mask = BIT(11),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "gsbi10_qup_src",
1186 .parent_names = gcc_pxo_pll8,
1187 .num_parents = 2,
1188 .ops = &clk_rcg_ops,
1189 .flags = CLK_SET_PARENT_GATE,
1190 },
1191 },
1192};
1193
1194static struct clk_branch gsbi10_qup_clk = {
1195 .halt_reg = 0x2fd0,
1196 .halt_bit = 0,
1197 .clkr = {
1198 .enable_reg = 0x2aec,
1199 .enable_mask = BIT(9),
1200 .hw.init = &(struct clk_init_data){
1201 .name = "gsbi10_qup_clk",
1202 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1203 .num_parents = 1,
1204 .ops = &clk_branch_ops,
1205 .flags = CLK_SET_RATE_PARENT,
1206 },
1207 },
1208};
1209
1210static struct clk_rcg gsbi11_qup_src = {
1211 .ns_reg = 0x2b0c,
1212 .md_reg = 0x2b08,
1213 .mn = {
1214 .mnctr_en_bit = 8,
1215 .mnctr_reset_bit = 7,
1216 .mnctr_mode_shift = 5,
1217 .n_val_shift = 16,
1218 .m_val_shift = 16,
1219 .width = 8,
1220 },
1221 .p = {
1222 .pre_div_shift = 3,
1223 .pre_div_width = 2,
1224 },
1225 .s = {
1226 .src_sel_shift = 0,
1227 .parent_map = gcc_pxo_pll8_map,
1228 },
1229 .freq_tbl = clk_tbl_gsbi_qup,
1230 .clkr = {
1231 .enable_reg = 0x2b0c,
1232 .enable_mask = BIT(11),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gsbi11_qup_src",
1235 .parent_names = gcc_pxo_pll8,
1236 .num_parents = 2,
1237 .ops = &clk_rcg_ops,
1238 .flags = CLK_SET_PARENT_GATE,
1239 },
1240 },
1241};
1242
1243static struct clk_branch gsbi11_qup_clk = {
1244 .halt_reg = 0x2fd4,
1245 .halt_bit = 15,
1246 .clkr = {
1247 .enable_reg = 0x2b0c,
1248 .enable_mask = BIT(9),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "gsbi11_qup_clk",
1251 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1252 .num_parents = 1,
1253 .ops = &clk_branch_ops,
1254 .flags = CLK_SET_RATE_PARENT,
1255 },
1256 },
1257};
1258
1259static struct clk_rcg gsbi12_qup_src = {
1260 .ns_reg = 0x2b2c,
1261 .md_reg = 0x2b28,
1262 .mn = {
1263 .mnctr_en_bit = 8,
1264 .mnctr_reset_bit = 7,
1265 .mnctr_mode_shift = 5,
1266 .n_val_shift = 16,
1267 .m_val_shift = 16,
1268 .width = 8,
1269 },
1270 .p = {
1271 .pre_div_shift = 3,
1272 .pre_div_width = 2,
1273 },
1274 .s = {
1275 .src_sel_shift = 0,
1276 .parent_map = gcc_pxo_pll8_map,
1277 },
1278 .freq_tbl = clk_tbl_gsbi_qup,
1279 .clkr = {
1280 .enable_reg = 0x2b2c,
1281 .enable_mask = BIT(11),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "gsbi12_qup_src",
1284 .parent_names = gcc_pxo_pll8,
1285 .num_parents = 2,
1286 .ops = &clk_rcg_ops,
1287 .flags = CLK_SET_PARENT_GATE,
1288 },
1289 },
1290};
1291
1292static struct clk_branch gsbi12_qup_clk = {
1293 .halt_reg = 0x2fd4,
1294 .halt_bit = 11,
1295 .clkr = {
1296 .enable_reg = 0x2b2c,
1297 .enable_mask = BIT(9),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "gsbi12_qup_clk",
1300 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1301 .num_parents = 1,
1302 .ops = &clk_branch_ops,
1303 .flags = CLK_SET_RATE_PARENT,
1304 },
1305 },
1306};
1307
1308static const struct freq_tbl clk_tbl_gp[] = {
1309 { 9600000, P_CXO, 2, 0, 0 },
1310 { 13500000, P_PXO, 2, 0, 0 },
1311 { 19200000, P_CXO, 1, 0, 0 },
1312 { 27000000, P_PXO, 1, 0, 0 },
1313 { 64000000, P_PLL8, 2, 1, 3 },
1314 { 76800000, P_PLL8, 1, 1, 5 },
1315 { 96000000, P_PLL8, 4, 0, 0 },
1316 { 128000000, P_PLL8, 3, 0, 0 },
1317 { 192000000, P_PLL8, 2, 0, 0 },
1318 { }
1319};
1320
1321static struct clk_rcg gp0_src = {
1322 .ns_reg = 0x2d24,
1323 .md_reg = 0x2d00,
1324 .mn = {
1325 .mnctr_en_bit = 8,
1326 .mnctr_reset_bit = 7,
1327 .mnctr_mode_shift = 5,
1328 .n_val_shift = 16,
1329 .m_val_shift = 16,
1330 .width = 8,
1331 },
1332 .p = {
1333 .pre_div_shift = 3,
1334 .pre_div_width = 2,
1335 },
1336 .s = {
1337 .src_sel_shift = 0,
1338 .parent_map = gcc_pxo_pll8_cxo_map,
1339 },
1340 .freq_tbl = clk_tbl_gp,
1341 .clkr = {
1342 .enable_reg = 0x2d24,
1343 .enable_mask = BIT(11),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "gp0_src",
1346 .parent_names = gcc_pxo_pll8_cxo,
1347 .num_parents = 3,
1348 .ops = &clk_rcg_ops,
1349 .flags = CLK_SET_PARENT_GATE,
1350 },
1351 }
1352};
1353
1354static struct clk_branch gp0_clk = {
1355 .halt_reg = 0x2fd8,
1356 .halt_bit = 7,
1357 .clkr = {
1358 .enable_reg = 0x2d24,
1359 .enable_mask = BIT(9),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "gp0_clk",
1362 .parent_names = (const char *[]){ "gp0_src" },
1363 .num_parents = 1,
1364 .ops = &clk_branch_ops,
1365 .flags = CLK_SET_RATE_PARENT,
1366 },
1367 },
1368};
1369
1370static struct clk_rcg gp1_src = {
1371 .ns_reg = 0x2d44,
1372 .md_reg = 0x2d40,
1373 .mn = {
1374 .mnctr_en_bit = 8,
1375 .mnctr_reset_bit = 7,
1376 .mnctr_mode_shift = 5,
1377 .n_val_shift = 16,
1378 .m_val_shift = 16,
1379 .width = 8,
1380 },
1381 .p = {
1382 .pre_div_shift = 3,
1383 .pre_div_width = 2,
1384 },
1385 .s = {
1386 .src_sel_shift = 0,
1387 .parent_map = gcc_pxo_pll8_cxo_map,
1388 },
1389 .freq_tbl = clk_tbl_gp,
1390 .clkr = {
1391 .enable_reg = 0x2d44,
1392 .enable_mask = BIT(11),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gp1_src",
1395 .parent_names = gcc_pxo_pll8_cxo,
1396 .num_parents = 3,
1397 .ops = &clk_rcg_ops,
1398 .flags = CLK_SET_RATE_GATE,
1399 },
1400 }
1401};
1402
1403static struct clk_branch gp1_clk = {
1404 .halt_reg = 0x2fd8,
1405 .halt_bit = 6,
1406 .clkr = {
1407 .enable_reg = 0x2d44,
1408 .enable_mask = BIT(9),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gp1_clk",
1411 .parent_names = (const char *[]){ "gp1_src" },
1412 .num_parents = 1,
1413 .ops = &clk_branch_ops,
1414 .flags = CLK_SET_RATE_PARENT,
1415 },
1416 },
1417};
1418
1419static struct clk_rcg gp2_src = {
1420 .ns_reg = 0x2d64,
1421 .md_reg = 0x2d60,
1422 .mn = {
1423 .mnctr_en_bit = 8,
1424 .mnctr_reset_bit = 7,
1425 .mnctr_mode_shift = 5,
1426 .n_val_shift = 16,
1427 .m_val_shift = 16,
1428 .width = 8,
1429 },
1430 .p = {
1431 .pre_div_shift = 3,
1432 .pre_div_width = 2,
1433 },
1434 .s = {
1435 .src_sel_shift = 0,
1436 .parent_map = gcc_pxo_pll8_cxo_map,
1437 },
1438 .freq_tbl = clk_tbl_gp,
1439 .clkr = {
1440 .enable_reg = 0x2d64,
1441 .enable_mask = BIT(11),
1442 .hw.init = &(struct clk_init_data){
1443 .name = "gp2_src",
1444 .parent_names = gcc_pxo_pll8_cxo,
1445 .num_parents = 3,
1446 .ops = &clk_rcg_ops,
1447 .flags = CLK_SET_RATE_GATE,
1448 },
1449 }
1450};
1451
1452static struct clk_branch gp2_clk = {
1453 .halt_reg = 0x2fd8,
1454 .halt_bit = 5,
1455 .clkr = {
1456 .enable_reg = 0x2d64,
1457 .enable_mask = BIT(9),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "gp2_clk",
1460 .parent_names = (const char *[]){ "gp2_src" },
1461 .num_parents = 1,
1462 .ops = &clk_branch_ops,
1463 .flags = CLK_SET_RATE_PARENT,
1464 },
1465 },
1466};
1467
1468static struct clk_branch pmem_clk = {
1469 .hwcg_reg = 0x25a0,
1470 .hwcg_bit = 6,
1471 .halt_reg = 0x2fc8,
1472 .halt_bit = 20,
1473 .clkr = {
1474 .enable_reg = 0x25a0,
1475 .enable_mask = BIT(4),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "pmem_clk",
1478 .ops = &clk_branch_ops,
1479 .flags = CLK_IS_ROOT,
1480 },
1481 },
1482};
1483
1484static struct clk_rcg prng_src = {
1485 .ns_reg = 0x2e80,
1486 .p = {
1487 .pre_div_shift = 3,
1488 .pre_div_width = 4,
1489 },
1490 .s = {
1491 .src_sel_shift = 0,
1492 .parent_map = gcc_pxo_pll8_map,
1493 },
1494 .clkr.hw = {
1495 .init = &(struct clk_init_data){
1496 .name = "prng_src",
1497 .parent_names = gcc_pxo_pll8,
1498 .num_parents = 2,
1499 .ops = &clk_rcg_ops,
1500 },
1501 },
1502};
1503
1504static struct clk_branch prng_clk = {
1505 .halt_reg = 0x2fd8,
1506 .halt_check = BRANCH_HALT_VOTED,
1507 .halt_bit = 10,
1508 .clkr = {
1509 .enable_reg = 0x3080,
1510 .enable_mask = BIT(10),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "prng_clk",
1513 .parent_names = (const char *[]){ "prng_src" },
1514 .num_parents = 1,
1515 .ops = &clk_branch_ops,
1516 },
1517 },
1518};
1519
1520static const struct freq_tbl clk_tbl_sdc[] = {
1521 { 144000, P_PXO, 3, 2, 125 },
1522 { 400000, P_PLL8, 4, 1, 240 },
1523 { 16000000, P_PLL8, 4, 1, 6 },
1524 { 17070000, P_PLL8, 1, 2, 45 },
1525 { 20210000, P_PLL8, 1, 1, 19 },
1526 { 24000000, P_PLL8, 4, 1, 4 },
1527 { 48000000, P_PLL8, 4, 1, 2 },
1528 { }
1529};
1530
1531static struct clk_rcg sdc1_src = {
1532 .ns_reg = 0x282c,
1533 .md_reg = 0x2828,
1534 .mn = {
1535 .mnctr_en_bit = 8,
1536 .mnctr_reset_bit = 7,
1537 .mnctr_mode_shift = 5,
1538 .n_val_shift = 16,
1539 .m_val_shift = 16,
1540 .width = 8,
1541 },
1542 .p = {
1543 .pre_div_shift = 3,
1544 .pre_div_width = 2,
1545 },
1546 .s = {
1547 .src_sel_shift = 0,
1548 .parent_map = gcc_pxo_pll8_map,
1549 },
1550 .freq_tbl = clk_tbl_sdc,
1551 .clkr = {
1552 .enable_reg = 0x282c,
1553 .enable_mask = BIT(11),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "sdc1_src",
1556 .parent_names = gcc_pxo_pll8,
1557 .num_parents = 2,
1558 .ops = &clk_rcg_ops,
1559 .flags = CLK_SET_RATE_GATE,
1560 },
1561 }
1562};
1563
1564static struct clk_branch sdc1_clk = {
1565 .halt_reg = 0x2fc8,
1566 .halt_bit = 6,
1567 .clkr = {
1568 .enable_reg = 0x282c,
1569 .enable_mask = BIT(9),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "sdc1_clk",
1572 .parent_names = (const char *[]){ "sdc1_src" },
1573 .num_parents = 1,
1574 .ops = &clk_branch_ops,
1575 .flags = CLK_SET_RATE_PARENT,
1576 },
1577 },
1578};
1579
1580static struct clk_rcg sdc2_src = {
1581 .ns_reg = 0x284c,
1582 .md_reg = 0x2848,
1583 .mn = {
1584 .mnctr_en_bit = 8,
1585 .mnctr_reset_bit = 7,
1586 .mnctr_mode_shift = 5,
1587 .n_val_shift = 16,
1588 .m_val_shift = 16,
1589 .width = 8,
1590 },
1591 .p = {
1592 .pre_div_shift = 3,
1593 .pre_div_width = 2,
1594 },
1595 .s = {
1596 .src_sel_shift = 0,
1597 .parent_map = gcc_pxo_pll8_map,
1598 },
1599 .freq_tbl = clk_tbl_sdc,
1600 .clkr = {
1601 .enable_reg = 0x284c,
1602 .enable_mask = BIT(11),
1603 .hw.init = &(struct clk_init_data){
1604 .name = "sdc2_src",
1605 .parent_names = gcc_pxo_pll8,
1606 .num_parents = 2,
1607 .ops = &clk_rcg_ops,
1608 .flags = CLK_SET_RATE_GATE,
1609 },
1610 }
1611};
1612
1613static struct clk_branch sdc2_clk = {
1614 .halt_reg = 0x2fc8,
1615 .halt_bit = 5,
1616 .clkr = {
1617 .enable_reg = 0x284c,
1618 .enable_mask = BIT(9),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "sdc2_clk",
1621 .parent_names = (const char *[]){ "sdc2_src" },
1622 .num_parents = 1,
1623 .ops = &clk_branch_ops,
1624 .flags = CLK_SET_RATE_PARENT,
1625 },
1626 },
1627};
1628
1629static struct clk_rcg sdc3_src = {
1630 .ns_reg = 0x286c,
1631 .md_reg = 0x2868,
1632 .mn = {
1633 .mnctr_en_bit = 8,
1634 .mnctr_reset_bit = 7,
1635 .mnctr_mode_shift = 5,
1636 .n_val_shift = 16,
1637 .m_val_shift = 16,
1638 .width = 8,
1639 },
1640 .p = {
1641 .pre_div_shift = 3,
1642 .pre_div_width = 2,
1643 },
1644 .s = {
1645 .src_sel_shift = 0,
1646 .parent_map = gcc_pxo_pll8_map,
1647 },
1648 .freq_tbl = clk_tbl_sdc,
1649 .clkr = {
1650 .enable_reg = 0x286c,
1651 .enable_mask = BIT(11),
1652 .hw.init = &(struct clk_init_data){
1653 .name = "sdc3_src",
1654 .parent_names = gcc_pxo_pll8,
1655 .num_parents = 2,
1656 .ops = &clk_rcg_ops,
1657 .flags = CLK_SET_RATE_GATE,
1658 },
1659 }
1660};
1661
1662static struct clk_branch sdc3_clk = {
1663 .halt_reg = 0x2fc8,
1664 .halt_bit = 4,
1665 .clkr = {
1666 .enable_reg = 0x286c,
1667 .enable_mask = BIT(9),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "sdc3_clk",
1670 .parent_names = (const char *[]){ "sdc3_src" },
1671 .num_parents = 1,
1672 .ops = &clk_branch_ops,
1673 .flags = CLK_SET_RATE_PARENT,
1674 },
1675 },
1676};
1677
1678static struct clk_rcg sdc4_src = {
1679 .ns_reg = 0x288c,
1680 .md_reg = 0x2888,
1681 .mn = {
1682 .mnctr_en_bit = 8,
1683 .mnctr_reset_bit = 7,
1684 .mnctr_mode_shift = 5,
1685 .n_val_shift = 16,
1686 .m_val_shift = 16,
1687 .width = 8,
1688 },
1689 .p = {
1690 .pre_div_shift = 3,
1691 .pre_div_width = 2,
1692 },
1693 .s = {
1694 .src_sel_shift = 0,
1695 .parent_map = gcc_pxo_pll8_map,
1696 },
1697 .freq_tbl = clk_tbl_sdc,
1698 .clkr = {
1699 .enable_reg = 0x288c,
1700 .enable_mask = BIT(11),
1701 .hw.init = &(struct clk_init_data){
1702 .name = "sdc4_src",
1703 .parent_names = gcc_pxo_pll8,
1704 .num_parents = 2,
1705 .ops = &clk_rcg_ops,
1706 .flags = CLK_SET_RATE_GATE,
1707 },
1708 }
1709};
1710
1711static struct clk_branch sdc4_clk = {
1712 .halt_reg = 0x2fc8,
1713 .halt_bit = 3,
1714 .clkr = {
1715 .enable_reg = 0x288c,
1716 .enable_mask = BIT(9),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "sdc4_clk",
1719 .parent_names = (const char *[]){ "sdc4_src" },
1720 .num_parents = 1,
1721 .ops = &clk_branch_ops,
1722 .flags = CLK_SET_RATE_PARENT,
1723 },
1724 },
1725};
1726
1727static struct clk_rcg sdc5_src = {
1728 .ns_reg = 0x28ac,
1729 .md_reg = 0x28a8,
1730 .mn = {
1731 .mnctr_en_bit = 8,
1732 .mnctr_reset_bit = 7,
1733 .mnctr_mode_shift = 5,
1734 .n_val_shift = 16,
1735 .m_val_shift = 16,
1736 .width = 8,
1737 },
1738 .p = {
1739 .pre_div_shift = 3,
1740 .pre_div_width = 2,
1741 },
1742 .s = {
1743 .src_sel_shift = 0,
1744 .parent_map = gcc_pxo_pll8_map,
1745 },
1746 .freq_tbl = clk_tbl_sdc,
1747 .clkr = {
1748 .enable_reg = 0x28ac,
1749 .enable_mask = BIT(11),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "sdc5_src",
1752 .parent_names = gcc_pxo_pll8,
1753 .num_parents = 2,
1754 .ops = &clk_rcg_ops,
1755 .flags = CLK_SET_RATE_GATE,
1756 },
1757 }
1758};
1759
1760static struct clk_branch sdc5_clk = {
1761 .halt_reg = 0x2fc8,
1762 .halt_bit = 2,
1763 .clkr = {
1764 .enable_reg = 0x28ac,
1765 .enable_mask = BIT(9),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "sdc5_clk",
1768 .parent_names = (const char *[]){ "sdc5_src" },
1769 .num_parents = 1,
1770 .ops = &clk_branch_ops,
1771 .flags = CLK_SET_RATE_PARENT,
1772 },
1773 },
1774};
1775
1776static const struct freq_tbl clk_tbl_tsif_ref[] = {
1777 { 105000, P_PXO, 1, 1, 256 },
1778 { }
1779};
1780
1781static struct clk_rcg tsif_ref_src = {
1782 .ns_reg = 0x2710,
1783 .md_reg = 0x270c,
1784 .mn = {
1785 .mnctr_en_bit = 8,
1786 .mnctr_reset_bit = 7,
1787 .mnctr_mode_shift = 5,
1788 .n_val_shift = 16,
1789 .m_val_shift = 16,
1790 .width = 16,
1791 },
1792 .p = {
1793 .pre_div_shift = 3,
1794 .pre_div_width = 2,
1795 },
1796 .s = {
1797 .src_sel_shift = 0,
1798 .parent_map = gcc_pxo_pll8_map,
1799 },
1800 .freq_tbl = clk_tbl_tsif_ref,
1801 .clkr = {
1802 .enable_reg = 0x2710,
1803 .enable_mask = BIT(11),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "tsif_ref_src",
1806 .parent_names = gcc_pxo_pll8,
1807 .num_parents = 2,
1808 .ops = &clk_rcg_ops,
1809 .flags = CLK_SET_RATE_GATE,
1810 },
1811 }
1812};
1813
1814static struct clk_branch tsif_ref_clk = {
1815 .halt_reg = 0x2fd4,
1816 .halt_bit = 5,
1817 .clkr = {
1818 .enable_reg = 0x2710,
1819 .enable_mask = BIT(9),
1820 .hw.init = &(struct clk_init_data){
1821 .name = "tsif_ref_clk",
1822 .parent_names = (const char *[]){ "tsif_ref_src" },
1823 .num_parents = 1,
1824 .ops = &clk_branch_ops,
1825 .flags = CLK_SET_RATE_PARENT,
1826 },
1827 },
1828};
1829
1830static const struct freq_tbl clk_tbl_usb[] = {
1831 { 60000000, P_PLL8, 1, 5, 32 },
1832 { }
1833};
1834
1835static struct clk_rcg usb_hs1_xcvr_src = {
1836 .ns_reg = 0x290c,
1837 .md_reg = 0x2908,
1838 .mn = {
1839 .mnctr_en_bit = 8,
1840 .mnctr_reset_bit = 7,
1841 .mnctr_mode_shift = 5,
1842 .n_val_shift = 16,
1843 .m_val_shift = 16,
1844 .width = 8,
1845 },
1846 .p = {
1847 .pre_div_shift = 3,
1848 .pre_div_width = 2,
1849 },
1850 .s = {
1851 .src_sel_shift = 0,
1852 .parent_map = gcc_pxo_pll8_map,
1853 },
1854 .freq_tbl = clk_tbl_usb,
1855 .clkr = {
1856 .enable_reg = 0x290c,
1857 .enable_mask = BIT(11),
1858 .hw.init = &(struct clk_init_data){
1859 .name = "usb_hs1_xcvr_src",
1860 .parent_names = gcc_pxo_pll8,
1861 .num_parents = 2,
1862 .ops = &clk_rcg_ops,
1863 .flags = CLK_SET_RATE_GATE,
1864 },
1865 }
1866};
1867
1868static struct clk_branch usb_hs1_xcvr_clk = {
1869 .halt_reg = 0x2fc8,
1870 .halt_bit = 0,
1871 .clkr = {
1872 .enable_reg = 0x290c,
1873 .enable_mask = BIT(9),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "usb_hs1_xcvr_clk",
1876 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1877 .num_parents = 1,
1878 .ops = &clk_branch_ops,
1879 .flags = CLK_SET_RATE_PARENT,
1880 },
1881 },
1882};
1883
1884static struct clk_rcg usb_fs1_xcvr_fs_src = {
1885 .ns_reg = 0x2968,
1886 .md_reg = 0x2964,
1887 .mn = {
1888 .mnctr_en_bit = 8,
1889 .mnctr_reset_bit = 7,
1890 .mnctr_mode_shift = 5,
1891 .n_val_shift = 16,
1892 .m_val_shift = 16,
1893 .width = 8,
1894 },
1895 .p = {
1896 .pre_div_shift = 3,
1897 .pre_div_width = 2,
1898 },
1899 .s = {
1900 .src_sel_shift = 0,
1901 .parent_map = gcc_pxo_pll8_map,
1902 },
1903 .freq_tbl = clk_tbl_usb,
1904 .clkr = {
1905 .enable_reg = 0x2968,
1906 .enable_mask = BIT(11),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "usb_fs1_xcvr_fs_src",
1909 .parent_names = gcc_pxo_pll8,
1910 .num_parents = 2,
1911 .ops = &clk_rcg_ops,
1912 .flags = CLK_SET_RATE_GATE,
1913 },
1914 }
1915};
1916
1917static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
1918
1919static struct clk_branch usb_fs1_xcvr_fs_clk = {
1920 .halt_reg = 0x2fcc,
1921 .halt_bit = 15,
1922 .clkr = {
1923 .enable_reg = 0x2968,
1924 .enable_mask = BIT(9),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "usb_fs1_xcvr_fs_clk",
1927 .parent_names = usb_fs1_xcvr_fs_src_p,
1928 .num_parents = 1,
1929 .ops = &clk_branch_ops,
1930 .flags = CLK_SET_RATE_PARENT,
1931 },
1932 },
1933};
1934
1935static struct clk_branch usb_fs1_system_clk = {
1936 .halt_reg = 0x2fcc,
1937 .halt_bit = 16,
1938 .clkr = {
1939 .enable_reg = 0x296c,
1940 .enable_mask = BIT(4),
1941 .hw.init = &(struct clk_init_data){
1942 .parent_names = usb_fs1_xcvr_fs_src_p,
1943 .num_parents = 1,
1944 .name = "usb_fs1_system_clk",
1945 .ops = &clk_branch_ops,
1946 .flags = CLK_SET_RATE_PARENT,
1947 },
1948 },
1949};
1950
1951static struct clk_rcg usb_fs2_xcvr_fs_src = {
1952 .ns_reg = 0x2988,
1953 .md_reg = 0x2984,
1954 .mn = {
1955 .mnctr_en_bit = 8,
1956 .mnctr_reset_bit = 7,
1957 .mnctr_mode_shift = 5,
1958 .n_val_shift = 16,
1959 .m_val_shift = 16,
1960 .width = 8,
1961 },
1962 .p = {
1963 .pre_div_shift = 3,
1964 .pre_div_width = 2,
1965 },
1966 .s = {
1967 .src_sel_shift = 0,
1968 .parent_map = gcc_pxo_pll8_map,
1969 },
1970 .freq_tbl = clk_tbl_usb,
1971 .clkr = {
1972 .enable_reg = 0x2988,
1973 .enable_mask = BIT(11),
1974 .hw.init = &(struct clk_init_data){
1975 .name = "usb_fs2_xcvr_fs_src",
1976 .parent_names = gcc_pxo_pll8,
1977 .num_parents = 2,
1978 .ops = &clk_rcg_ops,
1979 .flags = CLK_SET_RATE_GATE,
1980 },
1981 }
1982};
1983
1984static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
1985
1986static struct clk_branch usb_fs2_xcvr_fs_clk = {
1987 .halt_reg = 0x2fcc,
1988 .halt_bit = 12,
1989 .clkr = {
1990 .enable_reg = 0x2988,
1991 .enable_mask = BIT(9),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "usb_fs2_xcvr_fs_clk",
1994 .parent_names = usb_fs2_xcvr_fs_src_p,
1995 .num_parents = 1,
1996 .ops = &clk_branch_ops,
1997 .flags = CLK_SET_RATE_PARENT,
1998 },
1999 },
2000};
2001
2002static struct clk_branch usb_fs2_system_clk = {
2003 .halt_reg = 0x2fcc,
2004 .halt_bit = 13,
2005 .clkr = {
2006 .enable_reg = 0x298c,
2007 .enable_mask = BIT(4),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "usb_fs2_system_clk",
2010 .parent_names = usb_fs2_xcvr_fs_src_p,
2011 .num_parents = 1,
2012 .ops = &clk_branch_ops,
2013 .flags = CLK_SET_RATE_PARENT,
2014 },
2015 },
2016};
2017
2018static struct clk_branch gsbi1_h_clk = {
2019 .halt_reg = 0x2fcc,
2020 .halt_bit = 11,
2021 .clkr = {
2022 .enable_reg = 0x29c0,
2023 .enable_mask = BIT(4),
2024 .hw.init = &(struct clk_init_data){
2025 .name = "gsbi1_h_clk",
2026 .ops = &clk_branch_ops,
2027 .flags = CLK_IS_ROOT,
2028 },
2029 },
2030};
2031
2032static struct clk_branch gsbi2_h_clk = {
2033 .halt_reg = 0x2fcc,
2034 .halt_bit = 7,
2035 .clkr = {
2036 .enable_reg = 0x29e0,
2037 .enable_mask = BIT(4),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gsbi2_h_clk",
2040 .ops = &clk_branch_ops,
2041 .flags = CLK_IS_ROOT,
2042 },
2043 },
2044};
2045
2046static struct clk_branch gsbi3_h_clk = {
2047 .halt_reg = 0x2fcc,
2048 .halt_bit = 3,
2049 .clkr = {
2050 .enable_reg = 0x2a00,
2051 .enable_mask = BIT(4),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gsbi3_h_clk",
2054 .ops = &clk_branch_ops,
2055 .flags = CLK_IS_ROOT,
2056 },
2057 },
2058};
2059
2060static struct clk_branch gsbi4_h_clk = {
2061 .halt_reg = 0x2fd0,
2062 .halt_bit = 27,
2063 .clkr = {
2064 .enable_reg = 0x2a20,
2065 .enable_mask = BIT(4),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "gsbi4_h_clk",
2068 .ops = &clk_branch_ops,
2069 .flags = CLK_IS_ROOT,
2070 },
2071 },
2072};
2073
2074static struct clk_branch gsbi5_h_clk = {
2075 .halt_reg = 0x2fd0,
2076 .halt_bit = 23,
2077 .clkr = {
2078 .enable_reg = 0x2a40,
2079 .enable_mask = BIT(4),
2080 .hw.init = &(struct clk_init_data){
2081 .name = "gsbi5_h_clk",
2082 .ops = &clk_branch_ops,
2083 .flags = CLK_IS_ROOT,
2084 },
2085 },
2086};
2087
2088static struct clk_branch gsbi6_h_clk = {
2089 .halt_reg = 0x2fd0,
2090 .halt_bit = 19,
2091 .clkr = {
2092 .enable_reg = 0x2a60,
2093 .enable_mask = BIT(4),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gsbi6_h_clk",
2096 .ops = &clk_branch_ops,
2097 .flags = CLK_IS_ROOT,
2098 },
2099 },
2100};
2101
2102static struct clk_branch gsbi7_h_clk = {
2103 .halt_reg = 0x2fd0,
2104 .halt_bit = 15,
2105 .clkr = {
2106 .enable_reg = 0x2a80,
2107 .enable_mask = BIT(4),
2108 .hw.init = &(struct clk_init_data){
2109 .name = "gsbi7_h_clk",
2110 .ops = &clk_branch_ops,
2111 .flags = CLK_IS_ROOT,
2112 },
2113 },
2114};
2115
2116static struct clk_branch gsbi8_h_clk = {
2117 .halt_reg = 0x2fd0,
2118 .halt_bit = 11,
2119 .clkr = {
2120 .enable_reg = 0x2aa0,
2121 .enable_mask = BIT(4),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "gsbi8_h_clk",
2124 .ops = &clk_branch_ops,
2125 .flags = CLK_IS_ROOT,
2126 },
2127 },
2128};
2129
2130static struct clk_branch gsbi9_h_clk = {
2131 .halt_reg = 0x2fd0,
2132 .halt_bit = 7,
2133 .clkr = {
2134 .enable_reg = 0x2ac0,
2135 .enable_mask = BIT(4),
2136 .hw.init = &(struct clk_init_data){
2137 .name = "gsbi9_h_clk",
2138 .ops = &clk_branch_ops,
2139 .flags = CLK_IS_ROOT,
2140 },
2141 },
2142};
2143
2144static struct clk_branch gsbi10_h_clk = {
2145 .halt_reg = 0x2fd0,
2146 .halt_bit = 3,
2147 .clkr = {
2148 .enable_reg = 0x2ae0,
2149 .enable_mask = BIT(4),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "gsbi10_h_clk",
2152 .ops = &clk_branch_ops,
2153 .flags = CLK_IS_ROOT,
2154 },
2155 },
2156};
2157
2158static struct clk_branch gsbi11_h_clk = {
2159 .halt_reg = 0x2fd4,
2160 .halt_bit = 18,
2161 .clkr = {
2162 .enable_reg = 0x2b00,
2163 .enable_mask = BIT(4),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gsbi11_h_clk",
2166 .ops = &clk_branch_ops,
2167 .flags = CLK_IS_ROOT,
2168 },
2169 },
2170};
2171
2172static struct clk_branch gsbi12_h_clk = {
2173 .halt_reg = 0x2fd4,
2174 .halt_bit = 14,
2175 .clkr = {
2176 .enable_reg = 0x2b20,
2177 .enable_mask = BIT(4),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gsbi12_h_clk",
2180 .ops = &clk_branch_ops,
2181 .flags = CLK_IS_ROOT,
2182 },
2183 },
2184};
2185
2186static struct clk_branch tsif_h_clk = {
2187 .halt_reg = 0x2fd4,
2188 .halt_bit = 7,
2189 .clkr = {
2190 .enable_reg = 0x2700,
2191 .enable_mask = BIT(4),
2192 .hw.init = &(struct clk_init_data){
2193 .name = "tsif_h_clk",
2194 .ops = &clk_branch_ops,
2195 .flags = CLK_IS_ROOT,
2196 },
2197 },
2198};
2199
2200static struct clk_branch usb_fs1_h_clk = {
2201 .halt_reg = 0x2fcc,
2202 .halt_bit = 17,
2203 .clkr = {
2204 .enable_reg = 0x2960,
2205 .enable_mask = BIT(4),
2206 .hw.init = &(struct clk_init_data){
2207 .name = "usb_fs1_h_clk",
2208 .ops = &clk_branch_ops,
2209 .flags = CLK_IS_ROOT,
2210 },
2211 },
2212};
2213
2214static struct clk_branch usb_fs2_h_clk = {
2215 .halt_reg = 0x2fcc,
2216 .halt_bit = 14,
2217 .clkr = {
2218 .enable_reg = 0x2980,
2219 .enable_mask = BIT(4),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "usb_fs2_h_clk",
2222 .ops = &clk_branch_ops,
2223 .flags = CLK_IS_ROOT,
2224 },
2225 },
2226};
2227
2228static struct clk_branch usb_hs1_h_clk = {
2229 .halt_reg = 0x2fc8,
2230 .halt_bit = 1,
2231 .clkr = {
2232 .enable_reg = 0x2900,
2233 .enable_mask = BIT(4),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "usb_hs1_h_clk",
2236 .ops = &clk_branch_ops,
2237 .flags = CLK_IS_ROOT,
2238 },
2239 },
2240};
2241
2242static struct clk_branch sdc1_h_clk = {
2243 .halt_reg = 0x2fc8,
2244 .halt_bit = 11,
2245 .clkr = {
2246 .enable_reg = 0x2820,
2247 .enable_mask = BIT(4),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "sdc1_h_clk",
2250 .ops = &clk_branch_ops,
2251 .flags = CLK_IS_ROOT,
2252 },
2253 },
2254};
2255
2256static struct clk_branch sdc2_h_clk = {
2257 .halt_reg = 0x2fc8,
2258 .halt_bit = 10,
2259 .clkr = {
2260 .enable_reg = 0x2840,
2261 .enable_mask = BIT(4),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "sdc2_h_clk",
2264 .ops = &clk_branch_ops,
2265 .flags = CLK_IS_ROOT,
2266 },
2267 },
2268};
2269
2270static struct clk_branch sdc3_h_clk = {
2271 .halt_reg = 0x2fc8,
2272 .halt_bit = 9,
2273 .clkr = {
2274 .enable_reg = 0x2860,
2275 .enable_mask = BIT(4),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "sdc3_h_clk",
2278 .ops = &clk_branch_ops,
2279 .flags = CLK_IS_ROOT,
2280 },
2281 },
2282};
2283
2284static struct clk_branch sdc4_h_clk = {
2285 .halt_reg = 0x2fc8,
2286 .halt_bit = 8,
2287 .clkr = {
2288 .enable_reg = 0x2880,
2289 .enable_mask = BIT(4),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "sdc4_h_clk",
2292 .ops = &clk_branch_ops,
2293 .flags = CLK_IS_ROOT,
2294 },
2295 },
2296};
2297
2298static struct clk_branch sdc5_h_clk = {
2299 .halt_reg = 0x2fc8,
2300 .halt_bit = 7,
2301 .clkr = {
2302 .enable_reg = 0x28a0,
2303 .enable_mask = BIT(4),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "sdc5_h_clk",
2306 .ops = &clk_branch_ops,
2307 .flags = CLK_IS_ROOT,
2308 },
2309 },
2310};
2311
2312static struct clk_branch adm0_clk = {
2313 .halt_reg = 0x2fdc,
2314 .halt_check = BRANCH_HALT_VOTED,
2315 .halt_bit = 14,
2316 .clkr = {
2317 .enable_reg = 0x3080,
2318 .enable_mask = BIT(2),
2319 .hw.init = &(struct clk_init_data){
2320 .name = "adm0_clk",
2321 .ops = &clk_branch_ops,
2322 .flags = CLK_IS_ROOT,
2323 },
2324 },
2325};
2326
2327static struct clk_branch adm0_pbus_clk = {
2328 .halt_reg = 0x2fdc,
2329 .halt_check = BRANCH_HALT_VOTED,
2330 .halt_bit = 13,
2331 .clkr = {
2332 .enable_reg = 0x3080,
2333 .enable_mask = BIT(3),
2334 .hw.init = &(struct clk_init_data){
2335 .name = "adm0_pbus_clk",
2336 .ops = &clk_branch_ops,
2337 .flags = CLK_IS_ROOT,
2338 },
2339 },
2340};
2341
2342static struct clk_branch adm1_clk = {
2343 .halt_reg = 0x2fdc,
2344 .halt_bit = 12,
2345 .halt_check = BRANCH_HALT_VOTED,
2346 .clkr = {
2347 .enable_reg = 0x3080,
2348 .enable_mask = BIT(4),
2349 .hw.init = &(struct clk_init_data){
2350 .name = "adm1_clk",
2351 .ops = &clk_branch_ops,
2352 .flags = CLK_IS_ROOT,
2353 },
2354 },
2355};
2356
2357static struct clk_branch adm1_pbus_clk = {
2358 .halt_reg = 0x2fdc,
2359 .halt_bit = 11,
2360 .halt_check = BRANCH_HALT_VOTED,
2361 .clkr = {
2362 .enable_reg = 0x3080,
2363 .enable_mask = BIT(5),
2364 .hw.init = &(struct clk_init_data){
2365 .name = "adm1_pbus_clk",
2366 .ops = &clk_branch_ops,
2367 .flags = CLK_IS_ROOT,
2368 },
2369 },
2370};
2371
2372static struct clk_branch modem_ahb1_h_clk = {
2373 .halt_reg = 0x2fdc,
2374 .halt_bit = 8,
2375 .halt_check = BRANCH_HALT_VOTED,
2376 .clkr = {
2377 .enable_reg = 0x3080,
2378 .enable_mask = BIT(0),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "modem_ahb1_h_clk",
2381 .ops = &clk_branch_ops,
2382 .flags = CLK_IS_ROOT,
2383 },
2384 },
2385};
2386
2387static struct clk_branch modem_ahb2_h_clk = {
2388 .halt_reg = 0x2fdc,
2389 .halt_bit = 7,
2390 .halt_check = BRANCH_HALT_VOTED,
2391 .clkr = {
2392 .enable_reg = 0x3080,
2393 .enable_mask = BIT(1),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "modem_ahb2_h_clk",
2396 .ops = &clk_branch_ops,
2397 .flags = CLK_IS_ROOT,
2398 },
2399 },
2400};
2401
2402static struct clk_branch pmic_arb0_h_clk = {
2403 .halt_reg = 0x2fd8,
2404 .halt_check = BRANCH_HALT_VOTED,
2405 .halt_bit = 22,
2406 .clkr = {
2407 .enable_reg = 0x3080,
2408 .enable_mask = BIT(8),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "pmic_arb0_h_clk",
2411 .ops = &clk_branch_ops,
2412 .flags = CLK_IS_ROOT,
2413 },
2414 },
2415};
2416
2417static struct clk_branch pmic_arb1_h_clk = {
2418 .halt_reg = 0x2fd8,
2419 .halt_check = BRANCH_HALT_VOTED,
2420 .halt_bit = 21,
2421 .clkr = {
2422 .enable_reg = 0x3080,
2423 .enable_mask = BIT(9),
2424 .hw.init = &(struct clk_init_data){
2425 .name = "pmic_arb1_h_clk",
2426 .ops = &clk_branch_ops,
2427 .flags = CLK_IS_ROOT,
2428 },
2429 },
2430};
2431
2432static struct clk_branch pmic_ssbi2_clk = {
2433 .halt_reg = 0x2fd8,
2434 .halt_check = BRANCH_HALT_VOTED,
2435 .halt_bit = 23,
2436 .clkr = {
2437 .enable_reg = 0x3080,
2438 .enable_mask = BIT(7),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "pmic_ssbi2_clk",
2441 .ops = &clk_branch_ops,
2442 .flags = CLK_IS_ROOT,
2443 },
2444 },
2445};
2446
2447static struct clk_branch rpm_msg_ram_h_clk = {
2448 .hwcg_reg = 0x27e0,
2449 .hwcg_bit = 6,
2450 .halt_reg = 0x2fd8,
2451 .halt_check = BRANCH_HALT_VOTED,
2452 .halt_bit = 12,
2453 .clkr = {
2454 .enable_reg = 0x3080,
2455 .enable_mask = BIT(6),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "rpm_msg_ram_h_clk",
2458 .ops = &clk_branch_ops,
2459 .flags = CLK_IS_ROOT,
2460 },
2461 },
2462};
2463
2464static struct clk_regmap *gcc_msm8660_clks[] = {
2465 [PLL8] = &pll8.clkr,
2466 [PLL8_VOTE] = &pll8_vote,
2467 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2468 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2469 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2470 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2471 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2472 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2473 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2474 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2475 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2476 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2477 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2478 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2479 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2480 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2481 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2482 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2483 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2484 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2485 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2486 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2487 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2488 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2489 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2490 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2491 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2492 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2493 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2494 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2495 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2496 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2497 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2498 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2499 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2500 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2501 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2502 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2503 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2504 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2505 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2506 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2507 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2508 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2509 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2510 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2511 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2512 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2513 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2514 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2515 [GP0_SRC] = &gp0_src.clkr,
2516 [GP0_CLK] = &gp0_clk.clkr,
2517 [GP1_SRC] = &gp1_src.clkr,
2518 [GP1_CLK] = &gp1_clk.clkr,
2519 [GP2_SRC] = &gp2_src.clkr,
2520 [GP2_CLK] = &gp2_clk.clkr,
2521 [PMEM_CLK] = &pmem_clk.clkr,
2522 [PRNG_SRC] = &prng_src.clkr,
2523 [PRNG_CLK] = &prng_clk.clkr,
2524 [SDC1_SRC] = &sdc1_src.clkr,
2525 [SDC1_CLK] = &sdc1_clk.clkr,
2526 [SDC2_SRC] = &sdc2_src.clkr,
2527 [SDC2_CLK] = &sdc2_clk.clkr,
2528 [SDC3_SRC] = &sdc3_src.clkr,
2529 [SDC3_CLK] = &sdc3_clk.clkr,
2530 [SDC4_SRC] = &sdc4_src.clkr,
2531 [SDC4_CLK] = &sdc4_clk.clkr,
2532 [SDC5_SRC] = &sdc5_src.clkr,
2533 [SDC5_CLK] = &sdc5_clk.clkr,
2534 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2535 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2536 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2537 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2538 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2539 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2540 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2541 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2542 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2543 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2544 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2545 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2546 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2547 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2548 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2549 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2550 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2551 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2552 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2553 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2554 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2555 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2556 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2557 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2558 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2559 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2560 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2561 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2562 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2563 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2564 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2565 [ADM0_CLK] = &adm0_clk.clkr,
2566 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2567 [ADM1_CLK] = &adm1_clk.clkr,
2568 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2569 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2570 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2571 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2572 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2573 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2574 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2575};
2576
2577static const struct qcom_reset_map gcc_msm8660_resets[] = {
2578 [AFAB_CORE_RESET] = { 0x2080, 7 },
2579 [SCSS_SYS_RESET] = { 0x20b4, 1 },
2580 [SCSS_SYS_POR_RESET] = { 0x20b4 },
2581 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2582 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2583 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2584 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2585 [SFAB_CORE_RESET] = { 0x2120, 7 },
2586 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2587 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2588 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2589 [ADM0_C2_RESET] = { 0x220c, 4 },
2590 [ADM0_C1_RESET] = { 0x220c, 3 },
2591 [ADM0_C0_RESET] = { 0x220c, 2 },
2592 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2593 [ADM0_RESET] = { 0x220c },
2594 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2595 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2596 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2597 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2598 [ADM1_C3_RESET] = { 0x226c, 5 },
2599 [ADM1_C2_RESET] = { 0x226c, 4 },
2600 [ADM1_C1_RESET] = { 0x226c, 3 },
2601 [ADM1_C0_RESET] = { 0x226c, 2 },
2602 [ADM1_PBUS_RESET] = { 0x226c, 1 },
2603 [ADM1_RESET] = { 0x226c },
2604 [IMEM0_RESET] = { 0x2280, 7 },
2605 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2606 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2607 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2608 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2609 [DFAB_CORE_RESET] = { 0x24ac, 7 },
2610 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2611 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2612 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2613 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2614 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2615 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2616 [PPSS_PROC_RESET] = { 0x2594, 1 },
2617 [PPSS_RESET] = { 0x2594 },
2618 [PMEM_RESET] = { 0x25a0, 7 },
2619 [DMA_BAM_RESET] = { 0x25c0, 7 },
2620 [SIC_RESET] = { 0x25e0, 7 },
2621 [SPS_TIC_RESET] = { 0x2600, 7 },
2622 [CFBP0_RESET] = { 0x2650, 7 },
2623 [CFBP1_RESET] = { 0x2654, 7 },
2624 [CFBP2_RESET] = { 0x2658, 7 },
2625 [EBI2_RESET] = { 0x2664, 7 },
2626 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2627 [CFPB_MASTER_RESET] = { 0x26a0, 7 },
2628 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2629 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2630 [TSIF_RESET] = { 0x2700, 7 },
2631 [CE1_RESET] = { 0x2720, 7 },
2632 [CE2_RESET] = { 0x2740, 7 },
2633 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2634 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2635 [RPM_PROC_RESET] = { 0x27c0, 7 },
2636 [RPM_BUS_RESET] = { 0x27c4, 7 },
2637 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2638 [PMIC_ARB0_RESET] = { 0x2800, 7 },
2639 [PMIC_ARB1_RESET] = { 0x2804, 7 },
2640 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2641 [SDC1_RESET] = { 0x2830 },
2642 [SDC2_RESET] = { 0x2850 },
2643 [SDC3_RESET] = { 0x2870 },
2644 [SDC4_RESET] = { 0x2890 },
2645 [SDC5_RESET] = { 0x28b0 },
2646 [USB_HS1_RESET] = { 0x2910 },
2647 [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2648 [USB_HS2_RESET] = { 0x2934 },
2649 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2650 [USB_FS1_RESET] = { 0x2974 },
2651 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2652 [USB_FS2_RESET] = { 0x2994 },
2653 [GSBI1_RESET] = { 0x29dc },
2654 [GSBI2_RESET] = { 0x29fc },
2655 [GSBI3_RESET] = { 0x2a1c },
2656 [GSBI4_RESET] = { 0x2a3c },
2657 [GSBI5_RESET] = { 0x2a5c },
2658 [GSBI6_RESET] = { 0x2a7c },
2659 [GSBI7_RESET] = { 0x2a9c },
2660 [GSBI8_RESET] = { 0x2abc },
2661 [GSBI9_RESET] = { 0x2adc },
2662 [GSBI10_RESET] = { 0x2afc },
2663 [GSBI11_RESET] = { 0x2b1c },
2664 [GSBI12_RESET] = { 0x2b3c },
2665 [SPDM_RESET] = { 0x2b6c },
2666 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2667 [TLMM_H_RESET] = { 0x2ba0, 7 },
2668 [TLMM_RESET] = { 0x2ba4, 7 },
2669 [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2670 [MARM_RESET] = { 0x2bd4 },
2671 [MAHB1_RESET] = { 0x2be4, 7 },
2672 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2673 [MAHB2_RESET] = { 0x2c20, 7 },
2674 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2675 [MODEM_RESET] = { 0x2c48 },
2676 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2677 [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2678 [MSS_SLP_RESET] = { 0x2c60, 7 },
2679 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2680 [MSS_WDOG_RESET] = { 0x2c68 },
2681 [TSSC_RESET] = { 0x2ca0, 7 },
2682 [PDM_RESET] = { 0x2cc0, 12 },
2683 [SCSS_CORE0_RESET] = { 0x2d60, 1 },
2684 [SCSS_CORE0_POR_RESET] = { 0x2d60 },
2685 [SCSS_CORE1_RESET] = { 0x2d80, 1 },
2686 [SCSS_CORE1_POR_RESET] = { 0x2d80 },
2687 [MPM_RESET] = { 0x2da4, 1 },
2688 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2689 [EBI1_RESET] = { 0x2dec, 7 },
2690 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2691 [USB_PHY0_RESET] = { 0x2e20 },
2692 [USB_PHY1_RESET] = { 0x2e40 },
2693 [PRNG_RESET] = { 0x2e80, 12 },
2694};
2695
2696static const struct regmap_config gcc_msm8660_regmap_config = {
2697 .reg_bits = 32,
2698 .reg_stride = 4,
2699 .val_bits = 32,
2700 .max_register = 0x363c,
2701 .fast_io = true,
2702};
2703
2704static const struct of_device_id gcc_msm8660_match_table[] = {
2705 { .compatible = "qcom,gcc-msm8660" },
2706 { }
2707};
2708MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2709
2710struct qcom_cc {
2711 struct qcom_reset_controller reset;
2712 struct clk_onecell_data data;
2713 struct clk *clks[];
2714};
2715
2716static int gcc_msm8660_probe(struct platform_device *pdev)
2717{
2718 void __iomem *base;
2719 struct resource *res;
2720 int i, ret;
2721 struct device *dev = &pdev->dev;
2722 struct clk *clk;
2723 struct clk_onecell_data *data;
2724 struct clk **clks;
2725 struct regmap *regmap;
2726 size_t num_clks;
2727 struct qcom_reset_controller *reset;
2728 struct qcom_cc *cc;
2729
2730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2731 base = devm_ioremap_resource(dev, res);
2732 if (IS_ERR(base))
2733 return PTR_ERR(base);
2734
2735 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8660_regmap_config);
2736 if (IS_ERR(regmap))
2737 return PTR_ERR(regmap);
2738
2739 num_clks = ARRAY_SIZE(gcc_msm8660_clks);
2740 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2741 GFP_KERNEL);
2742 if (!cc)
2743 return -ENOMEM;
2744
2745 clks = cc->clks;
2746 data = &cc->data;
2747 data->clks = clks;
2748 data->clk_num = num_clks;
2749
2750 /* Temporary until RPM clocks supported */
2751 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2752 if (IS_ERR(clk))
2753 return PTR_ERR(clk);
2754
2755 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2756 if (IS_ERR(clk))
2757 return PTR_ERR(clk);
2758
2759 for (i = 0; i < num_clks; i++) {
2760 if (!gcc_msm8660_clks[i])
2761 continue;
2762 clk = devm_clk_register_regmap(dev, gcc_msm8660_clks[i]);
2763 if (IS_ERR(clk))
2764 return PTR_ERR(clk);
2765 clks[i] = clk;
2766 }
2767
2768 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2769 if (ret)
2770 return ret;
2771
2772 reset = &cc->reset;
2773 reset->rcdev.of_node = dev->of_node;
2774 reset->rcdev.ops = &qcom_reset_ops,
2775 reset->rcdev.owner = THIS_MODULE,
2776 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8660_resets),
2777 reset->regmap = regmap;
2778 reset->reset_map = gcc_msm8660_resets,
2779 platform_set_drvdata(pdev, &reset->rcdev);
2780
2781 ret = reset_controller_register(&reset->rcdev);
2782 if (ret)
2783 of_clk_del_provider(dev->of_node);
2784
2785 return ret;
2786}
2787
2788static int gcc_msm8660_remove(struct platform_device *pdev)
2789{
2790 of_clk_del_provider(pdev->dev.of_node);
2791 reset_controller_unregister(platform_get_drvdata(pdev));
2792 return 0;
2793}
2794
2795static struct platform_driver gcc_msm8660_driver = {
2796 .probe = gcc_msm8660_probe,
2797 .remove = gcc_msm8660_remove,
2798 .driver = {
2799 .name = "gcc-msm8660",
2800 .owner = THIS_MODULE,
2801 .of_match_table = gcc_msm8660_match_table,
2802 },
2803};
2804
2805static int __init gcc_msm8660_init(void)
2806{
2807 return platform_driver_register(&gcc_msm8660_driver);
2808}
2809core_initcall(gcc_msm8660_init);
2810
2811static void __exit gcc_msm8660_exit(void)
2812{
2813 platform_driver_unregister(&gcc_msm8660_driver);
2814}
2815module_exit(gcc_msm8660_exit);
2816
2817MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2818MODULE_LICENSE("GPL v2");
2819MODULE_ALIAS("platform:gcc-msm8660");
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
new file mode 100644
index 000000000000..fd446ab2fd98
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -0,0 +1,2993 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8960.h>
26#include <dt-bindings/reset/qcom,gcc-msm8960.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34static struct clk_pll pll3 = {
35 .l_reg = 0x3164,
36 .m_reg = 0x3168,
37 .n_reg = 0x316c,
38 .config_reg = 0x3174,
39 .mode_reg = 0x3160,
40 .status_reg = 0x3178,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll3",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48};
49
50static struct clk_pll pll8 = {
51 .l_reg = 0x3144,
52 .m_reg = 0x3148,
53 .n_reg = 0x314c,
54 .config_reg = 0x3154,
55 .mode_reg = 0x3140,
56 .status_reg = 0x3158,
57 .status_bit = 16,
58 .clkr.hw.init = &(struct clk_init_data){
59 .name = "pll8",
60 .parent_names = (const char *[]){ "pxo" },
61 .num_parents = 1,
62 .ops = &clk_pll_ops,
63 },
64};
65
66static struct clk_regmap pll8_vote = {
67 .enable_reg = 0x34c0,
68 .enable_mask = BIT(8),
69 .hw.init = &(struct clk_init_data){
70 .name = "pll8_vote",
71 .parent_names = (const char *[]){ "pll8" },
72 .num_parents = 1,
73 .ops = &clk_pll_vote_ops,
74 },
75};
76
77static struct clk_pll pll14 = {
78 .l_reg = 0x31c4,
79 .m_reg = 0x31c8,
80 .n_reg = 0x31cc,
81 .config_reg = 0x31d4,
82 .mode_reg = 0x31c0,
83 .status_reg = 0x31d8,
84 .status_bit = 16,
85 .clkr.hw.init = &(struct clk_init_data){
86 .name = "pll14",
87 .parent_names = (const char *[]){ "pxo" },
88 .num_parents = 1,
89 .ops = &clk_pll_ops,
90 },
91};
92
93static struct clk_regmap pll14_vote = {
94 .enable_reg = 0x34c0,
95 .enable_mask = BIT(14),
96 .hw.init = &(struct clk_init_data){
97 .name = "pll14_vote",
98 .parent_names = (const char *[]){ "pll14" },
99 .num_parents = 1,
100 .ops = &clk_pll_vote_ops,
101 },
102};
103
104#define P_PXO 0
105#define P_PLL8 1
106#define P_CXO 2
107
108static const u8 gcc_pxo_pll8_map[] = {
109 [P_PXO] = 0,
110 [P_PLL8] = 3,
111};
112
113static const char *gcc_pxo_pll8[] = {
114 "pxo",
115 "pll8_vote",
116};
117
118static const u8 gcc_pxo_pll8_cxo_map[] = {
119 [P_PXO] = 0,
120 [P_PLL8] = 3,
121 [P_CXO] = 5,
122};
123
124static const char *gcc_pxo_pll8_cxo[] = {
125 "pxo",
126 "pll8_vote",
127 "cxo",
128};
129
130static struct freq_tbl clk_tbl_gsbi_uart[] = {
131 { 1843200, P_PLL8, 2, 6, 625 },
132 { 3686400, P_PLL8, 2, 12, 625 },
133 { 7372800, P_PLL8, 2, 24, 625 },
134 { 14745600, P_PLL8, 2, 48, 625 },
135 { 16000000, P_PLL8, 4, 1, 6 },
136 { 24000000, P_PLL8, 4, 1, 4 },
137 { 32000000, P_PLL8, 4, 1, 3 },
138 { 40000000, P_PLL8, 1, 5, 48 },
139 { 46400000, P_PLL8, 1, 29, 240 },
140 { 48000000, P_PLL8, 4, 1, 2 },
141 { 51200000, P_PLL8, 1, 2, 15 },
142 { 56000000, P_PLL8, 1, 7, 48 },
143 { 58982400, P_PLL8, 1, 96, 625 },
144 { 64000000, P_PLL8, 2, 1, 3 },
145 { }
146};
147
148static struct clk_rcg gsbi1_uart_src = {
149 .ns_reg = 0x29d4,
150 .md_reg = 0x29d0,
151 .mn = {
152 .mnctr_en_bit = 8,
153 .mnctr_reset_bit = 7,
154 .mnctr_mode_shift = 5,
155 .n_val_shift = 16,
156 .m_val_shift = 16,
157 .width = 16,
158 },
159 .p = {
160 .pre_div_shift = 3,
161 .pre_div_width = 2,
162 },
163 .s = {
164 .src_sel_shift = 0,
165 .parent_map = gcc_pxo_pll8_map,
166 },
167 .freq_tbl = clk_tbl_gsbi_uart,
168 .clkr = {
169 .enable_reg = 0x29d4,
170 .enable_mask = BIT(11),
171 .hw.init = &(struct clk_init_data){
172 .name = "gsbi1_uart_src",
173 .parent_names = gcc_pxo_pll8,
174 .num_parents = 2,
175 .ops = &clk_rcg_ops,
176 .flags = CLK_SET_PARENT_GATE,
177 },
178 },
179};
180
181static struct clk_branch gsbi1_uart_clk = {
182 .halt_reg = 0x2fcc,
183 .halt_bit = 10,
184 .clkr = {
185 .enable_reg = 0x29d4,
186 .enable_mask = BIT(9),
187 .hw.init = &(struct clk_init_data){
188 .name = "gsbi1_uart_clk",
189 .parent_names = (const char *[]){
190 "gsbi1_uart_src",
191 },
192 .num_parents = 1,
193 .ops = &clk_branch_ops,
194 .flags = CLK_SET_RATE_PARENT,
195 },
196 },
197};
198
199static struct clk_rcg gsbi2_uart_src = {
200 .ns_reg = 0x29f4,
201 .md_reg = 0x29f0,
202 .mn = {
203 .mnctr_en_bit = 8,
204 .mnctr_reset_bit = 7,
205 .mnctr_mode_shift = 5,
206 .n_val_shift = 16,
207 .m_val_shift = 16,
208 .width = 16,
209 },
210 .p = {
211 .pre_div_shift = 3,
212 .pre_div_width = 2,
213 },
214 .s = {
215 .src_sel_shift = 0,
216 .parent_map = gcc_pxo_pll8_map,
217 },
218 .freq_tbl = clk_tbl_gsbi_uart,
219 .clkr = {
220 .enable_reg = 0x29f4,
221 .enable_mask = BIT(11),
222 .hw.init = &(struct clk_init_data){
223 .name = "gsbi2_uart_src",
224 .parent_names = gcc_pxo_pll8,
225 .num_parents = 2,
226 .ops = &clk_rcg_ops,
227 .flags = CLK_SET_PARENT_GATE,
228 },
229 },
230};
231
232static struct clk_branch gsbi2_uart_clk = {
233 .halt_reg = 0x2fcc,
234 .halt_bit = 6,
235 .clkr = {
236 .enable_reg = 0x29f4,
237 .enable_mask = BIT(9),
238 .hw.init = &(struct clk_init_data){
239 .name = "gsbi2_uart_clk",
240 .parent_names = (const char *[]){
241 "gsbi2_uart_src",
242 },
243 .num_parents = 1,
244 .ops = &clk_branch_ops,
245 .flags = CLK_SET_RATE_PARENT,
246 },
247 },
248};
249
250static struct clk_rcg gsbi3_uart_src = {
251 .ns_reg = 0x2a14,
252 .md_reg = 0x2a10,
253 .mn = {
254 .mnctr_en_bit = 8,
255 .mnctr_reset_bit = 7,
256 .mnctr_mode_shift = 5,
257 .n_val_shift = 16,
258 .m_val_shift = 16,
259 .width = 16,
260 },
261 .p = {
262 .pre_div_shift = 3,
263 .pre_div_width = 2,
264 },
265 .s = {
266 .src_sel_shift = 0,
267 .parent_map = gcc_pxo_pll8_map,
268 },
269 .freq_tbl = clk_tbl_gsbi_uart,
270 .clkr = {
271 .enable_reg = 0x2a14,
272 .enable_mask = BIT(11),
273 .hw.init = &(struct clk_init_data){
274 .name = "gsbi3_uart_src",
275 .parent_names = gcc_pxo_pll8,
276 .num_parents = 2,
277 .ops = &clk_rcg_ops,
278 .flags = CLK_SET_PARENT_GATE,
279 },
280 },
281};
282
283static struct clk_branch gsbi3_uart_clk = {
284 .halt_reg = 0x2fcc,
285 .halt_bit = 2,
286 .clkr = {
287 .enable_reg = 0x2a14,
288 .enable_mask = BIT(9),
289 .hw.init = &(struct clk_init_data){
290 .name = "gsbi3_uart_clk",
291 .parent_names = (const char *[]){
292 "gsbi3_uart_src",
293 },
294 .num_parents = 1,
295 .ops = &clk_branch_ops,
296 .flags = CLK_SET_RATE_PARENT,
297 },
298 },
299};
300
301static struct clk_rcg gsbi4_uart_src = {
302 .ns_reg = 0x2a34,
303 .md_reg = 0x2a30,
304 .mn = {
305 .mnctr_en_bit = 8,
306 .mnctr_reset_bit = 7,
307 .mnctr_mode_shift = 5,
308 .n_val_shift = 16,
309 .m_val_shift = 16,
310 .width = 16,
311 },
312 .p = {
313 .pre_div_shift = 3,
314 .pre_div_width = 2,
315 },
316 .s = {
317 .src_sel_shift = 0,
318 .parent_map = gcc_pxo_pll8_map,
319 },
320 .freq_tbl = clk_tbl_gsbi_uart,
321 .clkr = {
322 .enable_reg = 0x2a34,
323 .enable_mask = BIT(11),
324 .hw.init = &(struct clk_init_data){
325 .name = "gsbi4_uart_src",
326 .parent_names = gcc_pxo_pll8,
327 .num_parents = 2,
328 .ops = &clk_rcg_ops,
329 .flags = CLK_SET_PARENT_GATE,
330 },
331 },
332};
333
334static struct clk_branch gsbi4_uart_clk = {
335 .halt_reg = 0x2fd0,
336 .halt_bit = 26,
337 .clkr = {
338 .enable_reg = 0x2a34,
339 .enable_mask = BIT(9),
340 .hw.init = &(struct clk_init_data){
341 .name = "gsbi4_uart_clk",
342 .parent_names = (const char *[]){
343 "gsbi4_uart_src",
344 },
345 .num_parents = 1,
346 .ops = &clk_branch_ops,
347 .flags = CLK_SET_RATE_PARENT,
348 },
349 },
350};
351
352static struct clk_rcg gsbi5_uart_src = {
353 .ns_reg = 0x2a54,
354 .md_reg = 0x2a50,
355 .mn = {
356 .mnctr_en_bit = 8,
357 .mnctr_reset_bit = 7,
358 .mnctr_mode_shift = 5,
359 .n_val_shift = 16,
360 .m_val_shift = 16,
361 .width = 16,
362 },
363 .p = {
364 .pre_div_shift = 3,
365 .pre_div_width = 2,
366 },
367 .s = {
368 .src_sel_shift = 0,
369 .parent_map = gcc_pxo_pll8_map,
370 },
371 .freq_tbl = clk_tbl_gsbi_uart,
372 .clkr = {
373 .enable_reg = 0x2a54,
374 .enable_mask = BIT(11),
375 .hw.init = &(struct clk_init_data){
376 .name = "gsbi5_uart_src",
377 .parent_names = gcc_pxo_pll8,
378 .num_parents = 2,
379 .ops = &clk_rcg_ops,
380 .flags = CLK_SET_PARENT_GATE,
381 },
382 },
383};
384
385static struct clk_branch gsbi5_uart_clk = {
386 .halt_reg = 0x2fd0,
387 .halt_bit = 22,
388 .clkr = {
389 .enable_reg = 0x2a54,
390 .enable_mask = BIT(9),
391 .hw.init = &(struct clk_init_data){
392 .name = "gsbi5_uart_clk",
393 .parent_names = (const char *[]){
394 "gsbi5_uart_src",
395 },
396 .num_parents = 1,
397 .ops = &clk_branch_ops,
398 .flags = CLK_SET_RATE_PARENT,
399 },
400 },
401};
402
403static struct clk_rcg gsbi6_uart_src = {
404 .ns_reg = 0x2a74,
405 .md_reg = 0x2a70,
406 .mn = {
407 .mnctr_en_bit = 8,
408 .mnctr_reset_bit = 7,
409 .mnctr_mode_shift = 5,
410 .n_val_shift = 16,
411 .m_val_shift = 16,
412 .width = 16,
413 },
414 .p = {
415 .pre_div_shift = 3,
416 .pre_div_width = 2,
417 },
418 .s = {
419 .src_sel_shift = 0,
420 .parent_map = gcc_pxo_pll8_map,
421 },
422 .freq_tbl = clk_tbl_gsbi_uart,
423 .clkr = {
424 .enable_reg = 0x2a74,
425 .enable_mask = BIT(11),
426 .hw.init = &(struct clk_init_data){
427 .name = "gsbi6_uart_src",
428 .parent_names = gcc_pxo_pll8,
429 .num_parents = 2,
430 .ops = &clk_rcg_ops,
431 .flags = CLK_SET_PARENT_GATE,
432 },
433 },
434};
435
436static struct clk_branch gsbi6_uart_clk = {
437 .halt_reg = 0x2fd0,
438 .halt_bit = 18,
439 .clkr = {
440 .enable_reg = 0x2a74,
441 .enable_mask = BIT(9),
442 .hw.init = &(struct clk_init_data){
443 .name = "gsbi6_uart_clk",
444 .parent_names = (const char *[]){
445 "gsbi6_uart_src",
446 },
447 .num_parents = 1,
448 .ops = &clk_branch_ops,
449 .flags = CLK_SET_RATE_PARENT,
450 },
451 },
452};
453
454static struct clk_rcg gsbi7_uart_src = {
455 .ns_reg = 0x2a94,
456 .md_reg = 0x2a90,
457 .mn = {
458 .mnctr_en_bit = 8,
459 .mnctr_reset_bit = 7,
460 .mnctr_mode_shift = 5,
461 .n_val_shift = 16,
462 .m_val_shift = 16,
463 .width = 16,
464 },
465 .p = {
466 .pre_div_shift = 3,
467 .pre_div_width = 2,
468 },
469 .s = {
470 .src_sel_shift = 0,
471 .parent_map = gcc_pxo_pll8_map,
472 },
473 .freq_tbl = clk_tbl_gsbi_uart,
474 .clkr = {
475 .enable_reg = 0x2a94,
476 .enable_mask = BIT(11),
477 .hw.init = &(struct clk_init_data){
478 .name = "gsbi7_uart_src",
479 .parent_names = gcc_pxo_pll8,
480 .num_parents = 2,
481 .ops = &clk_rcg_ops,
482 .flags = CLK_SET_PARENT_GATE,
483 },
484 },
485};
486
487static struct clk_branch gsbi7_uart_clk = {
488 .halt_reg = 0x2fd0,
489 .halt_bit = 14,
490 .clkr = {
491 .enable_reg = 0x2a94,
492 .enable_mask = BIT(9),
493 .hw.init = &(struct clk_init_data){
494 .name = "gsbi7_uart_clk",
495 .parent_names = (const char *[]){
496 "gsbi7_uart_src",
497 },
498 .num_parents = 1,
499 .ops = &clk_branch_ops,
500 .flags = CLK_SET_RATE_PARENT,
501 },
502 },
503};
504
505static struct clk_rcg gsbi8_uart_src = {
506 .ns_reg = 0x2ab4,
507 .md_reg = 0x2ab0,
508 .mn = {
509 .mnctr_en_bit = 8,
510 .mnctr_reset_bit = 7,
511 .mnctr_mode_shift = 5,
512 .n_val_shift = 16,
513 .m_val_shift = 16,
514 .width = 16,
515 },
516 .p = {
517 .pre_div_shift = 3,
518 .pre_div_width = 2,
519 },
520 .s = {
521 .src_sel_shift = 0,
522 .parent_map = gcc_pxo_pll8_map,
523 },
524 .freq_tbl = clk_tbl_gsbi_uart,
525 .clkr = {
526 .enable_reg = 0x2ab4,
527 .enable_mask = BIT(11),
528 .hw.init = &(struct clk_init_data){
529 .name = "gsbi8_uart_src",
530 .parent_names = gcc_pxo_pll8,
531 .num_parents = 2,
532 .ops = &clk_rcg_ops,
533 .flags = CLK_SET_PARENT_GATE,
534 },
535 },
536};
537
538static struct clk_branch gsbi8_uart_clk = {
539 .halt_reg = 0x2fd0,
540 .halt_bit = 10,
541 .clkr = {
542 .enable_reg = 0x2ab4,
543 .enable_mask = BIT(9),
544 .hw.init = &(struct clk_init_data){
545 .name = "gsbi8_uart_clk",
546 .parent_names = (const char *[]){ "gsbi8_uart_src" },
547 .num_parents = 1,
548 .ops = &clk_branch_ops,
549 .flags = CLK_SET_RATE_PARENT,
550 },
551 },
552};
553
554static struct clk_rcg gsbi9_uart_src = {
555 .ns_reg = 0x2ad4,
556 .md_reg = 0x2ad0,
557 .mn = {
558 .mnctr_en_bit = 8,
559 .mnctr_reset_bit = 7,
560 .mnctr_mode_shift = 5,
561 .n_val_shift = 16,
562 .m_val_shift = 16,
563 .width = 16,
564 },
565 .p = {
566 .pre_div_shift = 3,
567 .pre_div_width = 2,
568 },
569 .s = {
570 .src_sel_shift = 0,
571 .parent_map = gcc_pxo_pll8_map,
572 },
573 .freq_tbl = clk_tbl_gsbi_uart,
574 .clkr = {
575 .enable_reg = 0x2ad4,
576 .enable_mask = BIT(11),
577 .hw.init = &(struct clk_init_data){
578 .name = "gsbi9_uart_src",
579 .parent_names = gcc_pxo_pll8,
580 .num_parents = 2,
581 .ops = &clk_rcg_ops,
582 .flags = CLK_SET_PARENT_GATE,
583 },
584 },
585};
586
587static struct clk_branch gsbi9_uart_clk = {
588 .halt_reg = 0x2fd0,
589 .halt_bit = 6,
590 .clkr = {
591 .enable_reg = 0x2ad4,
592 .enable_mask = BIT(9),
593 .hw.init = &(struct clk_init_data){
594 .name = "gsbi9_uart_clk",
595 .parent_names = (const char *[]){ "gsbi9_uart_src" },
596 .num_parents = 1,
597 .ops = &clk_branch_ops,
598 .flags = CLK_SET_RATE_PARENT,
599 },
600 },
601};
602
603static struct clk_rcg gsbi10_uart_src = {
604 .ns_reg = 0x2af4,
605 .md_reg = 0x2af0,
606 .mn = {
607 .mnctr_en_bit = 8,
608 .mnctr_reset_bit = 7,
609 .mnctr_mode_shift = 5,
610 .n_val_shift = 16,
611 .m_val_shift = 16,
612 .width = 16,
613 },
614 .p = {
615 .pre_div_shift = 3,
616 .pre_div_width = 2,
617 },
618 .s = {
619 .src_sel_shift = 0,
620 .parent_map = gcc_pxo_pll8_map,
621 },
622 .freq_tbl = clk_tbl_gsbi_uart,
623 .clkr = {
624 .enable_reg = 0x2af4,
625 .enable_mask = BIT(11),
626 .hw.init = &(struct clk_init_data){
627 .name = "gsbi10_uart_src",
628 .parent_names = gcc_pxo_pll8,
629 .num_parents = 2,
630 .ops = &clk_rcg_ops,
631 .flags = CLK_SET_PARENT_GATE,
632 },
633 },
634};
635
636static struct clk_branch gsbi10_uart_clk = {
637 .halt_reg = 0x2fd0,
638 .halt_bit = 2,
639 .clkr = {
640 .enable_reg = 0x2af4,
641 .enable_mask = BIT(9),
642 .hw.init = &(struct clk_init_data){
643 .name = "gsbi10_uart_clk",
644 .parent_names = (const char *[]){ "gsbi10_uart_src" },
645 .num_parents = 1,
646 .ops = &clk_branch_ops,
647 .flags = CLK_SET_RATE_PARENT,
648 },
649 },
650};
651
652static struct clk_rcg gsbi11_uart_src = {
653 .ns_reg = 0x2b14,
654 .md_reg = 0x2b10,
655 .mn = {
656 .mnctr_en_bit = 8,
657 .mnctr_reset_bit = 7,
658 .mnctr_mode_shift = 5,
659 .n_val_shift = 16,
660 .m_val_shift = 16,
661 .width = 16,
662 },
663 .p = {
664 .pre_div_shift = 3,
665 .pre_div_width = 2,
666 },
667 .s = {
668 .src_sel_shift = 0,
669 .parent_map = gcc_pxo_pll8_map,
670 },
671 .freq_tbl = clk_tbl_gsbi_uart,
672 .clkr = {
673 .enable_reg = 0x2b14,
674 .enable_mask = BIT(11),
675 .hw.init = &(struct clk_init_data){
676 .name = "gsbi11_uart_src",
677 .parent_names = gcc_pxo_pll8,
678 .num_parents = 2,
679 .ops = &clk_rcg_ops,
680 .flags = CLK_SET_PARENT_GATE,
681 },
682 },
683};
684
685static struct clk_branch gsbi11_uart_clk = {
686 .halt_reg = 0x2fd4,
687 .halt_bit = 17,
688 .clkr = {
689 .enable_reg = 0x2b14,
690 .enable_mask = BIT(9),
691 .hw.init = &(struct clk_init_data){
692 .name = "gsbi11_uart_clk",
693 .parent_names = (const char *[]){ "gsbi11_uart_src" },
694 .num_parents = 1,
695 .ops = &clk_branch_ops,
696 .flags = CLK_SET_RATE_PARENT,
697 },
698 },
699};
700
701static struct clk_rcg gsbi12_uart_src = {
702 .ns_reg = 0x2b34,
703 .md_reg = 0x2b30,
704 .mn = {
705 .mnctr_en_bit = 8,
706 .mnctr_reset_bit = 7,
707 .mnctr_mode_shift = 5,
708 .n_val_shift = 16,
709 .m_val_shift = 16,
710 .width = 16,
711 },
712 .p = {
713 .pre_div_shift = 3,
714 .pre_div_width = 2,
715 },
716 .s = {
717 .src_sel_shift = 0,
718 .parent_map = gcc_pxo_pll8_map,
719 },
720 .freq_tbl = clk_tbl_gsbi_uart,
721 .clkr = {
722 .enable_reg = 0x2b34,
723 .enable_mask = BIT(11),
724 .hw.init = &(struct clk_init_data){
725 .name = "gsbi12_uart_src",
726 .parent_names = gcc_pxo_pll8,
727 .num_parents = 2,
728 .ops = &clk_rcg_ops,
729 .flags = CLK_SET_PARENT_GATE,
730 },
731 },
732};
733
734static struct clk_branch gsbi12_uart_clk = {
735 .halt_reg = 0x2fd4,
736 .halt_bit = 13,
737 .clkr = {
738 .enable_reg = 0x2b34,
739 .enable_mask = BIT(9),
740 .hw.init = &(struct clk_init_data){
741 .name = "gsbi12_uart_clk",
742 .parent_names = (const char *[]){ "gsbi12_uart_src" },
743 .num_parents = 1,
744 .ops = &clk_branch_ops,
745 .flags = CLK_SET_RATE_PARENT,
746 },
747 },
748};
749
750static struct freq_tbl clk_tbl_gsbi_qup[] = {
751 { 1100000, P_PXO, 1, 2, 49 },
752 { 5400000, P_PXO, 1, 1, 5 },
753 { 10800000, P_PXO, 1, 2, 5 },
754 { 15060000, P_PLL8, 1, 2, 51 },
755 { 24000000, P_PLL8, 4, 1, 4 },
756 { 25600000, P_PLL8, 1, 1, 15 },
757 { 27000000, P_PXO, 1, 0, 0 },
758 { 48000000, P_PLL8, 4, 1, 2 },
759 { 51200000, P_PLL8, 1, 2, 15 },
760 { }
761};
762
763static struct clk_rcg gsbi1_qup_src = {
764 .ns_reg = 0x29cc,
765 .md_reg = 0x29c8,
766 .mn = {
767 .mnctr_en_bit = 8,
768 .mnctr_reset_bit = 7,
769 .mnctr_mode_shift = 5,
770 .n_val_shift = 16,
771 .m_val_shift = 16,
772 .width = 8,
773 },
774 .p = {
775 .pre_div_shift = 3,
776 .pre_div_width = 2,
777 },
778 .s = {
779 .src_sel_shift = 0,
780 .parent_map = gcc_pxo_pll8_map,
781 },
782 .freq_tbl = clk_tbl_gsbi_qup,
783 .clkr = {
784 .enable_reg = 0x29cc,
785 .enable_mask = BIT(11),
786 .hw.init = &(struct clk_init_data){
787 .name = "gsbi1_qup_src",
788 .parent_names = gcc_pxo_pll8,
789 .num_parents = 2,
790 .ops = &clk_rcg_ops,
791 .flags = CLK_SET_PARENT_GATE,
792 },
793 },
794};
795
796static struct clk_branch gsbi1_qup_clk = {
797 .halt_reg = 0x2fcc,
798 .halt_bit = 9,
799 .clkr = {
800 .enable_reg = 0x29cc,
801 .enable_mask = BIT(9),
802 .hw.init = &(struct clk_init_data){
803 .name = "gsbi1_qup_clk",
804 .parent_names = (const char *[]){ "gsbi1_qup_src" },
805 .num_parents = 1,
806 .ops = &clk_branch_ops,
807 .flags = CLK_SET_RATE_PARENT,
808 },
809 },
810};
811
812static struct clk_rcg gsbi2_qup_src = {
813 .ns_reg = 0x29ec,
814 .md_reg = 0x29e8,
815 .mn = {
816 .mnctr_en_bit = 8,
817 .mnctr_reset_bit = 7,
818 .mnctr_mode_shift = 5,
819 .n_val_shift = 16,
820 .m_val_shift = 16,
821 .width = 8,
822 },
823 .p = {
824 .pre_div_shift = 3,
825 .pre_div_width = 2,
826 },
827 .s = {
828 .src_sel_shift = 0,
829 .parent_map = gcc_pxo_pll8_map,
830 },
831 .freq_tbl = clk_tbl_gsbi_qup,
832 .clkr = {
833 .enable_reg = 0x29ec,
834 .enable_mask = BIT(11),
835 .hw.init = &(struct clk_init_data){
836 .name = "gsbi2_qup_src",
837 .parent_names = gcc_pxo_pll8,
838 .num_parents = 2,
839 .ops = &clk_rcg_ops,
840 .flags = CLK_SET_PARENT_GATE,
841 },
842 },
843};
844
845static struct clk_branch gsbi2_qup_clk = {
846 .halt_reg = 0x2fcc,
847 .halt_bit = 4,
848 .clkr = {
849 .enable_reg = 0x29ec,
850 .enable_mask = BIT(9),
851 .hw.init = &(struct clk_init_data){
852 .name = "gsbi2_qup_clk",
853 .parent_names = (const char *[]){ "gsbi2_qup_src" },
854 .num_parents = 1,
855 .ops = &clk_branch_ops,
856 .flags = CLK_SET_RATE_PARENT,
857 },
858 },
859};
860
861static struct clk_rcg gsbi3_qup_src = {
862 .ns_reg = 0x2a0c,
863 .md_reg = 0x2a08,
864 .mn = {
865 .mnctr_en_bit = 8,
866 .mnctr_reset_bit = 7,
867 .mnctr_mode_shift = 5,
868 .n_val_shift = 16,
869 .m_val_shift = 16,
870 .width = 8,
871 },
872 .p = {
873 .pre_div_shift = 3,
874 .pre_div_width = 2,
875 },
876 .s = {
877 .src_sel_shift = 0,
878 .parent_map = gcc_pxo_pll8_map,
879 },
880 .freq_tbl = clk_tbl_gsbi_qup,
881 .clkr = {
882 .enable_reg = 0x2a0c,
883 .enable_mask = BIT(11),
884 .hw.init = &(struct clk_init_data){
885 .name = "gsbi3_qup_src",
886 .parent_names = gcc_pxo_pll8,
887 .num_parents = 2,
888 .ops = &clk_rcg_ops,
889 .flags = CLK_SET_PARENT_GATE,
890 },
891 },
892};
893
894static struct clk_branch gsbi3_qup_clk = {
895 .halt_reg = 0x2fcc,
896 .halt_bit = 0,
897 .clkr = {
898 .enable_reg = 0x2a0c,
899 .enable_mask = BIT(9),
900 .hw.init = &(struct clk_init_data){
901 .name = "gsbi3_qup_clk",
902 .parent_names = (const char *[]){ "gsbi3_qup_src" },
903 .num_parents = 1,
904 .ops = &clk_branch_ops,
905 .flags = CLK_SET_RATE_PARENT,
906 },
907 },
908};
909
910static struct clk_rcg gsbi4_qup_src = {
911 .ns_reg = 0x2a2c,
912 .md_reg = 0x2a28,
913 .mn = {
914 .mnctr_en_bit = 8,
915 .mnctr_reset_bit = 7,
916 .mnctr_mode_shift = 5,
917 .n_val_shift = 16,
918 .m_val_shift = 16,
919 .width = 8,
920 },
921 .p = {
922 .pre_div_shift = 3,
923 .pre_div_width = 2,
924 },
925 .s = {
926 .src_sel_shift = 0,
927 .parent_map = gcc_pxo_pll8_map,
928 },
929 .freq_tbl = clk_tbl_gsbi_qup,
930 .clkr = {
931 .enable_reg = 0x2a2c,
932 .enable_mask = BIT(11),
933 .hw.init = &(struct clk_init_data){
934 .name = "gsbi4_qup_src",
935 .parent_names = gcc_pxo_pll8,
936 .num_parents = 2,
937 .ops = &clk_rcg_ops,
938 .flags = CLK_SET_PARENT_GATE,
939 },
940 },
941};
942
943static struct clk_branch gsbi4_qup_clk = {
944 .halt_reg = 0x2fd0,
945 .halt_bit = 24,
946 .clkr = {
947 .enable_reg = 0x2a2c,
948 .enable_mask = BIT(9),
949 .hw.init = &(struct clk_init_data){
950 .name = "gsbi4_qup_clk",
951 .parent_names = (const char *[]){ "gsbi4_qup_src" },
952 .num_parents = 1,
953 .ops = &clk_branch_ops,
954 .flags = CLK_SET_RATE_PARENT,
955 },
956 },
957};
958
959static struct clk_rcg gsbi5_qup_src = {
960 .ns_reg = 0x2a4c,
961 .md_reg = 0x2a48,
962 .mn = {
963 .mnctr_en_bit = 8,
964 .mnctr_reset_bit = 7,
965 .mnctr_mode_shift = 5,
966 .n_val_shift = 16,
967 .m_val_shift = 16,
968 .width = 8,
969 },
970 .p = {
971 .pre_div_shift = 3,
972 .pre_div_width = 2,
973 },
974 .s = {
975 .src_sel_shift = 0,
976 .parent_map = gcc_pxo_pll8_map,
977 },
978 .freq_tbl = clk_tbl_gsbi_qup,
979 .clkr = {
980 .enable_reg = 0x2a4c,
981 .enable_mask = BIT(11),
982 .hw.init = &(struct clk_init_data){
983 .name = "gsbi5_qup_src",
984 .parent_names = gcc_pxo_pll8,
985 .num_parents = 2,
986 .ops = &clk_rcg_ops,
987 .flags = CLK_SET_PARENT_GATE,
988 },
989 },
990};
991
992static struct clk_branch gsbi5_qup_clk = {
993 .halt_reg = 0x2fd0,
994 .halt_bit = 20,
995 .clkr = {
996 .enable_reg = 0x2a4c,
997 .enable_mask = BIT(9),
998 .hw.init = &(struct clk_init_data){
999 .name = "gsbi5_qup_clk",
1000 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1001 .num_parents = 1,
1002 .ops = &clk_branch_ops,
1003 .flags = CLK_SET_RATE_PARENT,
1004 },
1005 },
1006};
1007
1008static struct clk_rcg gsbi6_qup_src = {
1009 .ns_reg = 0x2a6c,
1010 .md_reg = 0x2a68,
1011 .mn = {
1012 .mnctr_en_bit = 8,
1013 .mnctr_reset_bit = 7,
1014 .mnctr_mode_shift = 5,
1015 .n_val_shift = 16,
1016 .m_val_shift = 16,
1017 .width = 8,
1018 },
1019 .p = {
1020 .pre_div_shift = 3,
1021 .pre_div_width = 2,
1022 },
1023 .s = {
1024 .src_sel_shift = 0,
1025 .parent_map = gcc_pxo_pll8_map,
1026 },
1027 .freq_tbl = clk_tbl_gsbi_qup,
1028 .clkr = {
1029 .enable_reg = 0x2a6c,
1030 .enable_mask = BIT(11),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "gsbi6_qup_src",
1033 .parent_names = gcc_pxo_pll8,
1034 .num_parents = 2,
1035 .ops = &clk_rcg_ops,
1036 .flags = CLK_SET_PARENT_GATE,
1037 },
1038 },
1039};
1040
1041static struct clk_branch gsbi6_qup_clk = {
1042 .halt_reg = 0x2fd0,
1043 .halt_bit = 16,
1044 .clkr = {
1045 .enable_reg = 0x2a6c,
1046 .enable_mask = BIT(9),
1047 .hw.init = &(struct clk_init_data){
1048 .name = "gsbi6_qup_clk",
1049 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1050 .num_parents = 1,
1051 .ops = &clk_branch_ops,
1052 .flags = CLK_SET_RATE_PARENT,
1053 },
1054 },
1055};
1056
1057static struct clk_rcg gsbi7_qup_src = {
1058 .ns_reg = 0x2a8c,
1059 .md_reg = 0x2a88,
1060 .mn = {
1061 .mnctr_en_bit = 8,
1062 .mnctr_reset_bit = 7,
1063 .mnctr_mode_shift = 5,
1064 .n_val_shift = 16,
1065 .m_val_shift = 16,
1066 .width = 8,
1067 },
1068 .p = {
1069 .pre_div_shift = 3,
1070 .pre_div_width = 2,
1071 },
1072 .s = {
1073 .src_sel_shift = 0,
1074 .parent_map = gcc_pxo_pll8_map,
1075 },
1076 .freq_tbl = clk_tbl_gsbi_qup,
1077 .clkr = {
1078 .enable_reg = 0x2a8c,
1079 .enable_mask = BIT(11),
1080 .hw.init = &(struct clk_init_data){
1081 .name = "gsbi7_qup_src",
1082 .parent_names = gcc_pxo_pll8,
1083 .num_parents = 2,
1084 .ops = &clk_rcg_ops,
1085 .flags = CLK_SET_PARENT_GATE,
1086 },
1087 },
1088};
1089
1090static struct clk_branch gsbi7_qup_clk = {
1091 .halt_reg = 0x2fd0,
1092 .halt_bit = 12,
1093 .clkr = {
1094 .enable_reg = 0x2a8c,
1095 .enable_mask = BIT(9),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "gsbi7_qup_clk",
1098 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1099 .num_parents = 1,
1100 .ops = &clk_branch_ops,
1101 .flags = CLK_SET_RATE_PARENT,
1102 },
1103 },
1104};
1105
1106static struct clk_rcg gsbi8_qup_src = {
1107 .ns_reg = 0x2aac,
1108 .md_reg = 0x2aa8,
1109 .mn = {
1110 .mnctr_en_bit = 8,
1111 .mnctr_reset_bit = 7,
1112 .mnctr_mode_shift = 5,
1113 .n_val_shift = 16,
1114 .m_val_shift = 16,
1115 .width = 8,
1116 },
1117 .p = {
1118 .pre_div_shift = 3,
1119 .pre_div_width = 2,
1120 },
1121 .s = {
1122 .src_sel_shift = 0,
1123 .parent_map = gcc_pxo_pll8_map,
1124 },
1125 .freq_tbl = clk_tbl_gsbi_qup,
1126 .clkr = {
1127 .enable_reg = 0x2aac,
1128 .enable_mask = BIT(11),
1129 .hw.init = &(struct clk_init_data){
1130 .name = "gsbi8_qup_src",
1131 .parent_names = gcc_pxo_pll8,
1132 .num_parents = 2,
1133 .ops = &clk_rcg_ops,
1134 .flags = CLK_SET_PARENT_GATE,
1135 },
1136 },
1137};
1138
1139static struct clk_branch gsbi8_qup_clk = {
1140 .halt_reg = 0x2fd0,
1141 .halt_bit = 8,
1142 .clkr = {
1143 .enable_reg = 0x2aac,
1144 .enable_mask = BIT(9),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gsbi8_qup_clk",
1147 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1148 .num_parents = 1,
1149 .ops = &clk_branch_ops,
1150 .flags = CLK_SET_RATE_PARENT,
1151 },
1152 },
1153};
1154
1155static struct clk_rcg gsbi9_qup_src = {
1156 .ns_reg = 0x2acc,
1157 .md_reg = 0x2ac8,
1158 .mn = {
1159 .mnctr_en_bit = 8,
1160 .mnctr_reset_bit = 7,
1161 .mnctr_mode_shift = 5,
1162 .n_val_shift = 16,
1163 .m_val_shift = 16,
1164 .width = 8,
1165 },
1166 .p = {
1167 .pre_div_shift = 3,
1168 .pre_div_width = 2,
1169 },
1170 .s = {
1171 .src_sel_shift = 0,
1172 .parent_map = gcc_pxo_pll8_map,
1173 },
1174 .freq_tbl = clk_tbl_gsbi_qup,
1175 .clkr = {
1176 .enable_reg = 0x2acc,
1177 .enable_mask = BIT(11),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gsbi9_qup_src",
1180 .parent_names = gcc_pxo_pll8,
1181 .num_parents = 2,
1182 .ops = &clk_rcg_ops,
1183 .flags = CLK_SET_PARENT_GATE,
1184 },
1185 },
1186};
1187
1188static struct clk_branch gsbi9_qup_clk = {
1189 .halt_reg = 0x2fd0,
1190 .halt_bit = 4,
1191 .clkr = {
1192 .enable_reg = 0x2acc,
1193 .enable_mask = BIT(9),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "gsbi9_qup_clk",
1196 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1197 .num_parents = 1,
1198 .ops = &clk_branch_ops,
1199 .flags = CLK_SET_RATE_PARENT,
1200 },
1201 },
1202};
1203
1204static struct clk_rcg gsbi10_qup_src = {
1205 .ns_reg = 0x2aec,
1206 .md_reg = 0x2ae8,
1207 .mn = {
1208 .mnctr_en_bit = 8,
1209 .mnctr_reset_bit = 7,
1210 .mnctr_mode_shift = 5,
1211 .n_val_shift = 16,
1212 .m_val_shift = 16,
1213 .width = 8,
1214 },
1215 .p = {
1216 .pre_div_shift = 3,
1217 .pre_div_width = 2,
1218 },
1219 .s = {
1220 .src_sel_shift = 0,
1221 .parent_map = gcc_pxo_pll8_map,
1222 },
1223 .freq_tbl = clk_tbl_gsbi_qup,
1224 .clkr = {
1225 .enable_reg = 0x2aec,
1226 .enable_mask = BIT(11),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "gsbi10_qup_src",
1229 .parent_names = gcc_pxo_pll8,
1230 .num_parents = 2,
1231 .ops = &clk_rcg_ops,
1232 .flags = CLK_SET_PARENT_GATE,
1233 },
1234 },
1235};
1236
1237static struct clk_branch gsbi10_qup_clk = {
1238 .halt_reg = 0x2fd0,
1239 .halt_bit = 0,
1240 .clkr = {
1241 .enable_reg = 0x2aec,
1242 .enable_mask = BIT(9),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gsbi10_qup_clk",
1245 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1246 .num_parents = 1,
1247 .ops = &clk_branch_ops,
1248 .flags = CLK_SET_RATE_PARENT,
1249 },
1250 },
1251};
1252
1253static struct clk_rcg gsbi11_qup_src = {
1254 .ns_reg = 0x2b0c,
1255 .md_reg = 0x2b08,
1256 .mn = {
1257 .mnctr_en_bit = 8,
1258 .mnctr_reset_bit = 7,
1259 .mnctr_mode_shift = 5,
1260 .n_val_shift = 16,
1261 .m_val_shift = 16,
1262 .width = 8,
1263 },
1264 .p = {
1265 .pre_div_shift = 3,
1266 .pre_div_width = 2,
1267 },
1268 .s = {
1269 .src_sel_shift = 0,
1270 .parent_map = gcc_pxo_pll8_map,
1271 },
1272 .freq_tbl = clk_tbl_gsbi_qup,
1273 .clkr = {
1274 .enable_reg = 0x2b0c,
1275 .enable_mask = BIT(11),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gsbi11_qup_src",
1278 .parent_names = gcc_pxo_pll8,
1279 .num_parents = 2,
1280 .ops = &clk_rcg_ops,
1281 .flags = CLK_SET_PARENT_GATE,
1282 },
1283 },
1284};
1285
1286static struct clk_branch gsbi11_qup_clk = {
1287 .halt_reg = 0x2fd4,
1288 .halt_bit = 15,
1289 .clkr = {
1290 .enable_reg = 0x2b0c,
1291 .enable_mask = BIT(9),
1292 .hw.init = &(struct clk_init_data){
1293 .name = "gsbi11_qup_clk",
1294 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1295 .num_parents = 1,
1296 .ops = &clk_branch_ops,
1297 .flags = CLK_SET_RATE_PARENT,
1298 },
1299 },
1300};
1301
1302static struct clk_rcg gsbi12_qup_src = {
1303 .ns_reg = 0x2b2c,
1304 .md_reg = 0x2b28,
1305 .mn = {
1306 .mnctr_en_bit = 8,
1307 .mnctr_reset_bit = 7,
1308 .mnctr_mode_shift = 5,
1309 .n_val_shift = 16,
1310 .m_val_shift = 16,
1311 .width = 8,
1312 },
1313 .p = {
1314 .pre_div_shift = 3,
1315 .pre_div_width = 2,
1316 },
1317 .s = {
1318 .src_sel_shift = 0,
1319 .parent_map = gcc_pxo_pll8_map,
1320 },
1321 .freq_tbl = clk_tbl_gsbi_qup,
1322 .clkr = {
1323 .enable_reg = 0x2b2c,
1324 .enable_mask = BIT(11),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "gsbi12_qup_src",
1327 .parent_names = gcc_pxo_pll8,
1328 .num_parents = 2,
1329 .ops = &clk_rcg_ops,
1330 .flags = CLK_SET_PARENT_GATE,
1331 },
1332 },
1333};
1334
1335static struct clk_branch gsbi12_qup_clk = {
1336 .halt_reg = 0x2fd4,
1337 .halt_bit = 11,
1338 .clkr = {
1339 .enable_reg = 0x2b2c,
1340 .enable_mask = BIT(9),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gsbi12_qup_clk",
1343 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1344 .num_parents = 1,
1345 .ops = &clk_branch_ops,
1346 .flags = CLK_SET_RATE_PARENT,
1347 },
1348 },
1349};
1350
1351static const struct freq_tbl clk_tbl_gp[] = {
1352 { 9600000, P_CXO, 2, 0, 0 },
1353 { 13500000, P_PXO, 2, 0, 0 },
1354 { 19200000, P_CXO, 1, 0, 0 },
1355 { 27000000, P_PXO, 1, 0, 0 },
1356 { 64000000, P_PLL8, 2, 1, 3 },
1357 { 76800000, P_PLL8, 1, 1, 5 },
1358 { 96000000, P_PLL8, 4, 0, 0 },
1359 { 128000000, P_PLL8, 3, 0, 0 },
1360 { 192000000, P_PLL8, 2, 0, 0 },
1361 { }
1362};
1363
1364static struct clk_rcg gp0_src = {
1365 .ns_reg = 0x2d24,
1366 .md_reg = 0x2d00,
1367 .mn = {
1368 .mnctr_en_bit = 8,
1369 .mnctr_reset_bit = 7,
1370 .mnctr_mode_shift = 5,
1371 .n_val_shift = 16,
1372 .m_val_shift = 16,
1373 .width = 8,
1374 },
1375 .p = {
1376 .pre_div_shift = 3,
1377 .pre_div_width = 2,
1378 },
1379 .s = {
1380 .src_sel_shift = 0,
1381 .parent_map = gcc_pxo_pll8_cxo_map,
1382 },
1383 .freq_tbl = clk_tbl_gp,
1384 .clkr = {
1385 .enable_reg = 0x2d24,
1386 .enable_mask = BIT(11),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gp0_src",
1389 .parent_names = gcc_pxo_pll8_cxo,
1390 .num_parents = 3,
1391 .ops = &clk_rcg_ops,
1392 .flags = CLK_SET_PARENT_GATE,
1393 },
1394 }
1395};
1396
1397static struct clk_branch gp0_clk = {
1398 .halt_reg = 0x2fd8,
1399 .halt_bit = 7,
1400 .clkr = {
1401 .enable_reg = 0x2d24,
1402 .enable_mask = BIT(9),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gp0_clk",
1405 .parent_names = (const char *[]){ "gp0_src" },
1406 .num_parents = 1,
1407 .ops = &clk_branch_ops,
1408 .flags = CLK_SET_RATE_PARENT,
1409 },
1410 },
1411};
1412
1413static struct clk_rcg gp1_src = {
1414 .ns_reg = 0x2d44,
1415 .md_reg = 0x2d40,
1416 .mn = {
1417 .mnctr_en_bit = 8,
1418 .mnctr_reset_bit = 7,
1419 .mnctr_mode_shift = 5,
1420 .n_val_shift = 16,
1421 .m_val_shift = 16,
1422 .width = 8,
1423 },
1424 .p = {
1425 .pre_div_shift = 3,
1426 .pre_div_width = 2,
1427 },
1428 .s = {
1429 .src_sel_shift = 0,
1430 .parent_map = gcc_pxo_pll8_cxo_map,
1431 },
1432 .freq_tbl = clk_tbl_gp,
1433 .clkr = {
1434 .enable_reg = 0x2d44,
1435 .enable_mask = BIT(11),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "gp1_src",
1438 .parent_names = gcc_pxo_pll8_cxo,
1439 .num_parents = 3,
1440 .ops = &clk_rcg_ops,
1441 .flags = CLK_SET_RATE_GATE,
1442 },
1443 }
1444};
1445
1446static struct clk_branch gp1_clk = {
1447 .halt_reg = 0x2fd8,
1448 .halt_bit = 6,
1449 .clkr = {
1450 .enable_reg = 0x2d44,
1451 .enable_mask = BIT(9),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gp1_clk",
1454 .parent_names = (const char *[]){ "gp1_src" },
1455 .num_parents = 1,
1456 .ops = &clk_branch_ops,
1457 .flags = CLK_SET_RATE_PARENT,
1458 },
1459 },
1460};
1461
1462static struct clk_rcg gp2_src = {
1463 .ns_reg = 0x2d64,
1464 .md_reg = 0x2d60,
1465 .mn = {
1466 .mnctr_en_bit = 8,
1467 .mnctr_reset_bit = 7,
1468 .mnctr_mode_shift = 5,
1469 .n_val_shift = 16,
1470 .m_val_shift = 16,
1471 .width = 8,
1472 },
1473 .p = {
1474 .pre_div_shift = 3,
1475 .pre_div_width = 2,
1476 },
1477 .s = {
1478 .src_sel_shift = 0,
1479 .parent_map = gcc_pxo_pll8_cxo_map,
1480 },
1481 .freq_tbl = clk_tbl_gp,
1482 .clkr = {
1483 .enable_reg = 0x2d64,
1484 .enable_mask = BIT(11),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "gp2_src",
1487 .parent_names = gcc_pxo_pll8_cxo,
1488 .num_parents = 3,
1489 .ops = &clk_rcg_ops,
1490 .flags = CLK_SET_RATE_GATE,
1491 },
1492 }
1493};
1494
1495static struct clk_branch gp2_clk = {
1496 .halt_reg = 0x2fd8,
1497 .halt_bit = 5,
1498 .clkr = {
1499 .enable_reg = 0x2d64,
1500 .enable_mask = BIT(9),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "gp2_clk",
1503 .parent_names = (const char *[]){ "gp2_src" },
1504 .num_parents = 1,
1505 .ops = &clk_branch_ops,
1506 .flags = CLK_SET_RATE_PARENT,
1507 },
1508 },
1509};
1510
1511static struct clk_branch pmem_clk = {
1512 .hwcg_reg = 0x25a0,
1513 .hwcg_bit = 6,
1514 .halt_reg = 0x2fc8,
1515 .halt_bit = 20,
1516 .clkr = {
1517 .enable_reg = 0x25a0,
1518 .enable_mask = BIT(4),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "pmem_clk",
1521 .ops = &clk_branch_ops,
1522 .flags = CLK_IS_ROOT,
1523 },
1524 },
1525};
1526
1527static struct clk_rcg prng_src = {
1528 .ns_reg = 0x2e80,
1529 .p = {
1530 .pre_div_shift = 3,
1531 .pre_div_width = 4,
1532 },
1533 .s = {
1534 .src_sel_shift = 0,
1535 .parent_map = gcc_pxo_pll8_map,
1536 },
1537 .clkr = {
1538 .hw.init = &(struct clk_init_data){
1539 .name = "prng_src",
1540 .parent_names = gcc_pxo_pll8,
1541 .num_parents = 2,
1542 .ops = &clk_rcg_ops,
1543 },
1544 },
1545};
1546
1547static struct clk_branch prng_clk = {
1548 .halt_reg = 0x2fd8,
1549 .halt_check = BRANCH_HALT_VOTED,
1550 .halt_bit = 10,
1551 .clkr = {
1552 .enable_reg = 0x3080,
1553 .enable_mask = BIT(10),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "prng_clk",
1556 .parent_names = (const char *[]){ "prng_src" },
1557 .num_parents = 1,
1558 .ops = &clk_branch_ops,
1559 },
1560 },
1561};
1562
1563static const struct freq_tbl clk_tbl_sdc[] = {
1564 { 144000, P_PXO, 3, 2, 125 },
1565 { 400000, P_PLL8, 4, 1, 240 },
1566 { 16000000, P_PLL8, 4, 1, 6 },
1567 { 17070000, P_PLL8, 1, 2, 45 },
1568 { 20210000, P_PLL8, 1, 1, 19 },
1569 { 24000000, P_PLL8, 4, 1, 4 },
1570 { 48000000, P_PLL8, 4, 1, 2 },
1571 { 64000000, P_PLL8, 3, 1, 2 },
1572 { 96000000, P_PLL8, 4, 0, 0 },
1573 { 192000000, P_PLL8, 2, 0, 0 },
1574 { }
1575};
1576
1577static struct clk_rcg sdc1_src = {
1578 .ns_reg = 0x282c,
1579 .md_reg = 0x2828,
1580 .mn = {
1581 .mnctr_en_bit = 8,
1582 .mnctr_reset_bit = 7,
1583 .mnctr_mode_shift = 5,
1584 .n_val_shift = 16,
1585 .m_val_shift = 16,
1586 .width = 8,
1587 },
1588 .p = {
1589 .pre_div_shift = 3,
1590 .pre_div_width = 2,
1591 },
1592 .s = {
1593 .src_sel_shift = 0,
1594 .parent_map = gcc_pxo_pll8_map,
1595 },
1596 .freq_tbl = clk_tbl_sdc,
1597 .clkr = {
1598 .enable_reg = 0x282c,
1599 .enable_mask = BIT(11),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "sdc1_src",
1602 .parent_names = gcc_pxo_pll8,
1603 .num_parents = 2,
1604 .ops = &clk_rcg_ops,
1605 .flags = CLK_SET_RATE_GATE,
1606 },
1607 }
1608};
1609
1610static struct clk_branch sdc1_clk = {
1611 .halt_reg = 0x2fc8,
1612 .halt_bit = 6,
1613 .clkr = {
1614 .enable_reg = 0x282c,
1615 .enable_mask = BIT(9),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "sdc1_clk",
1618 .parent_names = (const char *[]){ "sdc1_src" },
1619 .num_parents = 1,
1620 .ops = &clk_branch_ops,
1621 .flags = CLK_SET_RATE_PARENT,
1622 },
1623 },
1624};
1625
1626static struct clk_rcg sdc2_src = {
1627 .ns_reg = 0x284c,
1628 .md_reg = 0x2848,
1629 .mn = {
1630 .mnctr_en_bit = 8,
1631 .mnctr_reset_bit = 7,
1632 .mnctr_mode_shift = 5,
1633 .n_val_shift = 16,
1634 .m_val_shift = 16,
1635 .width = 8,
1636 },
1637 .p = {
1638 .pre_div_shift = 3,
1639 .pre_div_width = 2,
1640 },
1641 .s = {
1642 .src_sel_shift = 0,
1643 .parent_map = gcc_pxo_pll8_map,
1644 },
1645 .freq_tbl = clk_tbl_sdc,
1646 .clkr = {
1647 .enable_reg = 0x284c,
1648 .enable_mask = BIT(11),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "sdc2_src",
1651 .parent_names = gcc_pxo_pll8,
1652 .num_parents = 2,
1653 .ops = &clk_rcg_ops,
1654 .flags = CLK_SET_RATE_GATE,
1655 },
1656 }
1657};
1658
1659static struct clk_branch sdc2_clk = {
1660 .halt_reg = 0x2fc8,
1661 .halt_bit = 5,
1662 .clkr = {
1663 .enable_reg = 0x284c,
1664 .enable_mask = BIT(9),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "sdc2_clk",
1667 .parent_names = (const char *[]){ "sdc2_src" },
1668 .num_parents = 1,
1669 .ops = &clk_branch_ops,
1670 .flags = CLK_SET_RATE_PARENT,
1671 },
1672 },
1673};
1674
1675static struct clk_rcg sdc3_src = {
1676 .ns_reg = 0x286c,
1677 .md_reg = 0x2868,
1678 .mn = {
1679 .mnctr_en_bit = 8,
1680 .mnctr_reset_bit = 7,
1681 .mnctr_mode_shift = 5,
1682 .n_val_shift = 16,
1683 .m_val_shift = 16,
1684 .width = 8,
1685 },
1686 .p = {
1687 .pre_div_shift = 3,
1688 .pre_div_width = 2,
1689 },
1690 .s = {
1691 .src_sel_shift = 0,
1692 .parent_map = gcc_pxo_pll8_map,
1693 },
1694 .freq_tbl = clk_tbl_sdc,
1695 .clkr = {
1696 .enable_reg = 0x286c,
1697 .enable_mask = BIT(11),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "sdc3_src",
1700 .parent_names = gcc_pxo_pll8,
1701 .num_parents = 2,
1702 .ops = &clk_rcg_ops,
1703 .flags = CLK_SET_RATE_GATE,
1704 },
1705 }
1706};
1707
1708static struct clk_branch sdc3_clk = {
1709 .halt_reg = 0x2fc8,
1710 .halt_bit = 4,
1711 .clkr = {
1712 .enable_reg = 0x286c,
1713 .enable_mask = BIT(9),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "sdc3_clk",
1716 .parent_names = (const char *[]){ "sdc3_src" },
1717 .num_parents = 1,
1718 .ops = &clk_branch_ops,
1719 .flags = CLK_SET_RATE_PARENT,
1720 },
1721 },
1722};
1723
1724static struct clk_rcg sdc4_src = {
1725 .ns_reg = 0x288c,
1726 .md_reg = 0x2888,
1727 .mn = {
1728 .mnctr_en_bit = 8,
1729 .mnctr_reset_bit = 7,
1730 .mnctr_mode_shift = 5,
1731 .n_val_shift = 16,
1732 .m_val_shift = 16,
1733 .width = 8,
1734 },
1735 .p = {
1736 .pre_div_shift = 3,
1737 .pre_div_width = 2,
1738 },
1739 .s = {
1740 .src_sel_shift = 0,
1741 .parent_map = gcc_pxo_pll8_map,
1742 },
1743 .freq_tbl = clk_tbl_sdc,
1744 .clkr = {
1745 .enable_reg = 0x288c,
1746 .enable_mask = BIT(11),
1747 .hw.init = &(struct clk_init_data){
1748 .name = "sdc4_src",
1749 .parent_names = gcc_pxo_pll8,
1750 .num_parents = 2,
1751 .ops = &clk_rcg_ops,
1752 .flags = CLK_SET_RATE_GATE,
1753 },
1754 }
1755};
1756
1757static struct clk_branch sdc4_clk = {
1758 .halt_reg = 0x2fc8,
1759 .halt_bit = 3,
1760 .clkr = {
1761 .enable_reg = 0x288c,
1762 .enable_mask = BIT(9),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "sdc4_clk",
1765 .parent_names = (const char *[]){ "sdc4_src" },
1766 .num_parents = 1,
1767 .ops = &clk_branch_ops,
1768 .flags = CLK_SET_RATE_PARENT,
1769 },
1770 },
1771};
1772
1773static struct clk_rcg sdc5_src = {
1774 .ns_reg = 0x28ac,
1775 .md_reg = 0x28a8,
1776 .mn = {
1777 .mnctr_en_bit = 8,
1778 .mnctr_reset_bit = 7,
1779 .mnctr_mode_shift = 5,
1780 .n_val_shift = 16,
1781 .m_val_shift = 16,
1782 .width = 8,
1783 },
1784 .p = {
1785 .pre_div_shift = 3,
1786 .pre_div_width = 2,
1787 },
1788 .s = {
1789 .src_sel_shift = 0,
1790 .parent_map = gcc_pxo_pll8_map,
1791 },
1792 .freq_tbl = clk_tbl_sdc,
1793 .clkr = {
1794 .enable_reg = 0x28ac,
1795 .enable_mask = BIT(11),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "sdc5_src",
1798 .parent_names = gcc_pxo_pll8,
1799 .num_parents = 2,
1800 .ops = &clk_rcg_ops,
1801 .flags = CLK_SET_RATE_GATE,
1802 },
1803 }
1804};
1805
1806static struct clk_branch sdc5_clk = {
1807 .halt_reg = 0x2fc8,
1808 .halt_bit = 2,
1809 .clkr = {
1810 .enable_reg = 0x28ac,
1811 .enable_mask = BIT(9),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "sdc5_clk",
1814 .parent_names = (const char *[]){ "sdc5_src" },
1815 .num_parents = 1,
1816 .ops = &clk_branch_ops,
1817 .flags = CLK_SET_RATE_PARENT,
1818 },
1819 },
1820};
1821
1822static const struct freq_tbl clk_tbl_tsif_ref[] = {
1823 { 105000, P_PXO, 1, 1, 256 },
1824 { }
1825};
1826
1827static struct clk_rcg tsif_ref_src = {
1828 .ns_reg = 0x2710,
1829 .md_reg = 0x270c,
1830 .mn = {
1831 .mnctr_en_bit = 8,
1832 .mnctr_reset_bit = 7,
1833 .mnctr_mode_shift = 5,
1834 .n_val_shift = 16,
1835 .m_val_shift = 16,
1836 .width = 16,
1837 },
1838 .p = {
1839 .pre_div_shift = 3,
1840 .pre_div_width = 2,
1841 },
1842 .s = {
1843 .src_sel_shift = 0,
1844 .parent_map = gcc_pxo_pll8_map,
1845 },
1846 .freq_tbl = clk_tbl_tsif_ref,
1847 .clkr = {
1848 .enable_reg = 0x2710,
1849 .enable_mask = BIT(11),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "tsif_ref_src",
1852 .parent_names = gcc_pxo_pll8,
1853 .num_parents = 2,
1854 .ops = &clk_rcg_ops,
1855 .flags = CLK_SET_RATE_GATE,
1856 },
1857 }
1858};
1859
1860static struct clk_branch tsif_ref_clk = {
1861 .halt_reg = 0x2fd4,
1862 .halt_bit = 5,
1863 .clkr = {
1864 .enable_reg = 0x2710,
1865 .enable_mask = BIT(9),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "tsif_ref_clk",
1868 .parent_names = (const char *[]){ "tsif_ref_src" },
1869 .num_parents = 1,
1870 .ops = &clk_branch_ops,
1871 .flags = CLK_SET_RATE_PARENT,
1872 },
1873 },
1874};
1875
1876static const struct freq_tbl clk_tbl_usb[] = {
1877 { 60000000, P_PLL8, 1, 5, 32 },
1878 { }
1879};
1880
1881static struct clk_rcg usb_hs1_xcvr_src = {
1882 .ns_reg = 0x290c,
1883 .md_reg = 0x2908,
1884 .mn = {
1885 .mnctr_en_bit = 8,
1886 .mnctr_reset_bit = 7,
1887 .mnctr_mode_shift = 5,
1888 .n_val_shift = 16,
1889 .m_val_shift = 16,
1890 .width = 8,
1891 },
1892 .p = {
1893 .pre_div_shift = 3,
1894 .pre_div_width = 2,
1895 },
1896 .s = {
1897 .src_sel_shift = 0,
1898 .parent_map = gcc_pxo_pll8_map,
1899 },
1900 .freq_tbl = clk_tbl_usb,
1901 .clkr = {
1902 .enable_reg = 0x290c,
1903 .enable_mask = BIT(11),
1904 .hw.init = &(struct clk_init_data){
1905 .name = "usb_hs1_xcvr_src",
1906 .parent_names = gcc_pxo_pll8,
1907 .num_parents = 2,
1908 .ops = &clk_rcg_ops,
1909 .flags = CLK_SET_RATE_GATE,
1910 },
1911 }
1912};
1913
1914static struct clk_branch usb_hs1_xcvr_clk = {
1915 .halt_reg = 0x2fc8,
1916 .halt_bit = 0,
1917 .clkr = {
1918 .enable_reg = 0x290c,
1919 .enable_mask = BIT(9),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "usb_hs1_xcvr_clk",
1922 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1923 .num_parents = 1,
1924 .ops = &clk_branch_ops,
1925 .flags = CLK_SET_RATE_PARENT,
1926 },
1927 },
1928};
1929
1930static struct clk_rcg usb_hsic_xcvr_fs_src = {
1931 .ns_reg = 0x2928,
1932 .md_reg = 0x2924,
1933 .mn = {
1934 .mnctr_en_bit = 8,
1935 .mnctr_reset_bit = 7,
1936 .mnctr_mode_shift = 5,
1937 .n_val_shift = 16,
1938 .m_val_shift = 16,
1939 .width = 8,
1940 },
1941 .p = {
1942 .pre_div_shift = 3,
1943 .pre_div_width = 2,
1944 },
1945 .s = {
1946 .src_sel_shift = 0,
1947 .parent_map = gcc_pxo_pll8_map,
1948 },
1949 .freq_tbl = clk_tbl_usb,
1950 .clkr = {
1951 .enable_reg = 0x2928,
1952 .enable_mask = BIT(11),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "usb_hsic_xcvr_fs_src",
1955 .parent_names = gcc_pxo_pll8,
1956 .num_parents = 2,
1957 .ops = &clk_rcg_ops,
1958 .flags = CLK_SET_RATE_GATE,
1959 },
1960 }
1961};
1962
1963static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
1964
1965static struct clk_branch usb_hsic_xcvr_fs_clk = {
1966 .halt_reg = 0x2fc8,
1967 .halt_bit = 2,
1968 .clkr = {
1969 .enable_reg = 0x2928,
1970 .enable_mask = BIT(9),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "usb_hsic_xcvr_fs_clk",
1973 .parent_names = usb_hsic_xcvr_fs_src_p,
1974 .num_parents = 1,
1975 .ops = &clk_branch_ops,
1976 .flags = CLK_SET_RATE_PARENT,
1977 },
1978 },
1979};
1980
1981static struct clk_branch usb_hsic_system_clk = {
1982 .halt_reg = 0x2fcc,
1983 .halt_bit = 24,
1984 .clkr = {
1985 .enable_reg = 0x292c,
1986 .enable_mask = BIT(4),
1987 .hw.init = &(struct clk_init_data){
1988 .parent_names = usb_hsic_xcvr_fs_src_p,
1989 .num_parents = 1,
1990 .name = "usb_hsic_system_clk",
1991 .ops = &clk_branch_ops,
1992 .flags = CLK_SET_RATE_PARENT,
1993 },
1994 },
1995};
1996
1997static struct clk_branch usb_hsic_hsic_clk = {
1998 .halt_reg = 0x2fcc,
1999 .halt_bit = 19,
2000 .clkr = {
2001 .enable_reg = 0x2b44,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .parent_names = (const char *[]){ "pll14_vote" },
2005 .num_parents = 1,
2006 .name = "usb_hsic_hsic_clk",
2007 .ops = &clk_branch_ops,
2008 },
2009 },
2010};
2011
2012static struct clk_branch usb_hsic_hsio_cal_clk = {
2013 .halt_reg = 0x2fcc,
2014 .halt_bit = 23,
2015 .clkr = {
2016 .enable_reg = 0x2b48,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "usb_hsic_hsio_cal_clk",
2020 .ops = &clk_branch_ops,
2021 .flags = CLK_IS_ROOT,
2022 },
2023 },
2024};
2025
2026static struct clk_rcg usb_fs1_xcvr_fs_src = {
2027 .ns_reg = 0x2968,
2028 .md_reg = 0x2964,
2029 .mn = {
2030 .mnctr_en_bit = 8,
2031 .mnctr_reset_bit = 7,
2032 .mnctr_mode_shift = 5,
2033 .n_val_shift = 16,
2034 .m_val_shift = 16,
2035 .width = 8,
2036 },
2037 .p = {
2038 .pre_div_shift = 3,
2039 .pre_div_width = 2,
2040 },
2041 .s = {
2042 .src_sel_shift = 0,
2043 .parent_map = gcc_pxo_pll8_map,
2044 },
2045 .freq_tbl = clk_tbl_usb,
2046 .clkr = {
2047 .enable_reg = 0x2968,
2048 .enable_mask = BIT(11),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "usb_fs1_xcvr_fs_src",
2051 .parent_names = gcc_pxo_pll8,
2052 .num_parents = 2,
2053 .ops = &clk_rcg_ops,
2054 .flags = CLK_SET_RATE_GATE,
2055 },
2056 }
2057};
2058
2059static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2060
2061static struct clk_branch usb_fs1_xcvr_fs_clk = {
2062 .halt_reg = 0x2fcc,
2063 .halt_bit = 15,
2064 .clkr = {
2065 .enable_reg = 0x2968,
2066 .enable_mask = BIT(9),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "usb_fs1_xcvr_fs_clk",
2069 .parent_names = usb_fs1_xcvr_fs_src_p,
2070 .num_parents = 1,
2071 .ops = &clk_branch_ops,
2072 .flags = CLK_SET_RATE_PARENT,
2073 },
2074 },
2075};
2076
2077static struct clk_branch usb_fs1_system_clk = {
2078 .halt_reg = 0x2fcc,
2079 .halt_bit = 16,
2080 .clkr = {
2081 .enable_reg = 0x296c,
2082 .enable_mask = BIT(4),
2083 .hw.init = &(struct clk_init_data){
2084 .parent_names = usb_fs1_xcvr_fs_src_p,
2085 .num_parents = 1,
2086 .name = "usb_fs1_system_clk",
2087 .ops = &clk_branch_ops,
2088 .flags = CLK_SET_RATE_PARENT,
2089 },
2090 },
2091};
2092
2093static struct clk_rcg usb_fs2_xcvr_fs_src = {
2094 .ns_reg = 0x2988,
2095 .md_reg = 0x2984,
2096 .mn = {
2097 .mnctr_en_bit = 8,
2098 .mnctr_reset_bit = 7,
2099 .mnctr_mode_shift = 5,
2100 .n_val_shift = 16,
2101 .m_val_shift = 16,
2102 .width = 8,
2103 },
2104 .p = {
2105 .pre_div_shift = 3,
2106 .pre_div_width = 2,
2107 },
2108 .s = {
2109 .src_sel_shift = 0,
2110 .parent_map = gcc_pxo_pll8_map,
2111 },
2112 .freq_tbl = clk_tbl_usb,
2113 .clkr = {
2114 .enable_reg = 0x2988,
2115 .enable_mask = BIT(11),
2116 .hw.init = &(struct clk_init_data){
2117 .name = "usb_fs2_xcvr_fs_src",
2118 .parent_names = gcc_pxo_pll8,
2119 .num_parents = 2,
2120 .ops = &clk_rcg_ops,
2121 .flags = CLK_SET_RATE_GATE,
2122 },
2123 }
2124};
2125
2126static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2127
2128static struct clk_branch usb_fs2_xcvr_fs_clk = {
2129 .halt_reg = 0x2fcc,
2130 .halt_bit = 12,
2131 .clkr = {
2132 .enable_reg = 0x2988,
2133 .enable_mask = BIT(9),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "usb_fs2_xcvr_fs_clk",
2136 .parent_names = usb_fs2_xcvr_fs_src_p,
2137 .num_parents = 1,
2138 .ops = &clk_branch_ops,
2139 .flags = CLK_SET_RATE_PARENT,
2140 },
2141 },
2142};
2143
2144static struct clk_branch usb_fs2_system_clk = {
2145 .halt_reg = 0x2fcc,
2146 .halt_bit = 13,
2147 .clkr = {
2148 .enable_reg = 0x298c,
2149 .enable_mask = BIT(4),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "usb_fs2_system_clk",
2152 .parent_names = usb_fs2_xcvr_fs_src_p,
2153 .num_parents = 1,
2154 .ops = &clk_branch_ops,
2155 .flags = CLK_SET_RATE_PARENT,
2156 },
2157 },
2158};
2159
2160static struct clk_branch ce1_core_clk = {
2161 .hwcg_reg = 0x2724,
2162 .hwcg_bit = 6,
2163 .halt_reg = 0x2fd4,
2164 .halt_bit = 27,
2165 .clkr = {
2166 .enable_reg = 0x2724,
2167 .enable_mask = BIT(4),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "ce1_core_clk",
2170 .ops = &clk_branch_ops,
2171 .flags = CLK_IS_ROOT,
2172 },
2173 },
2174};
2175
2176static struct clk_branch ce1_h_clk = {
2177 .halt_reg = 0x2fd4,
2178 .halt_bit = 1,
2179 .clkr = {
2180 .enable_reg = 0x2720,
2181 .enable_mask = BIT(4),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "ce1_h_clk",
2184 .ops = &clk_branch_ops,
2185 .flags = CLK_IS_ROOT,
2186 },
2187 },
2188};
2189
2190static struct clk_branch dma_bam_h_clk = {
2191 .hwcg_reg = 0x25c0,
2192 .hwcg_bit = 6,
2193 .halt_reg = 0x2fc8,
2194 .halt_bit = 12,
2195 .clkr = {
2196 .enable_reg = 0x25c0,
2197 .enable_mask = BIT(4),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "dma_bam_h_clk",
2200 .ops = &clk_branch_ops,
2201 .flags = CLK_IS_ROOT,
2202 },
2203 },
2204};
2205
2206static struct clk_branch gsbi1_h_clk = {
2207 .hwcg_reg = 0x29c0,
2208 .hwcg_bit = 6,
2209 .halt_reg = 0x2fcc,
2210 .halt_bit = 11,
2211 .clkr = {
2212 .enable_reg = 0x29c0,
2213 .enable_mask = BIT(4),
2214 .hw.init = &(struct clk_init_data){
2215 .name = "gsbi1_h_clk",
2216 .ops = &clk_branch_ops,
2217 .flags = CLK_IS_ROOT,
2218 },
2219 },
2220};
2221
2222static struct clk_branch gsbi2_h_clk = {
2223 .hwcg_reg = 0x29e0,
2224 .hwcg_bit = 6,
2225 .halt_reg = 0x2fcc,
2226 .halt_bit = 7,
2227 .clkr = {
2228 .enable_reg = 0x29e0,
2229 .enable_mask = BIT(4),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "gsbi2_h_clk",
2232 .ops = &clk_branch_ops,
2233 .flags = CLK_IS_ROOT,
2234 },
2235 },
2236};
2237
2238static struct clk_branch gsbi3_h_clk = {
2239 .hwcg_reg = 0x2a00,
2240 .hwcg_bit = 6,
2241 .halt_reg = 0x2fcc,
2242 .halt_bit = 3,
2243 .clkr = {
2244 .enable_reg = 0x2a00,
2245 .enable_mask = BIT(4),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "gsbi3_h_clk",
2248 .ops = &clk_branch_ops,
2249 .flags = CLK_IS_ROOT,
2250 },
2251 },
2252};
2253
2254static struct clk_branch gsbi4_h_clk = {
2255 .hwcg_reg = 0x2a20,
2256 .hwcg_bit = 6,
2257 .halt_reg = 0x2fd0,
2258 .halt_bit = 27,
2259 .clkr = {
2260 .enable_reg = 0x2a20,
2261 .enable_mask = BIT(4),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "gsbi4_h_clk",
2264 .ops = &clk_branch_ops,
2265 .flags = CLK_IS_ROOT,
2266 },
2267 },
2268};
2269
2270static struct clk_branch gsbi5_h_clk = {
2271 .hwcg_reg = 0x2a40,
2272 .hwcg_bit = 6,
2273 .halt_reg = 0x2fd0,
2274 .halt_bit = 23,
2275 .clkr = {
2276 .enable_reg = 0x2a40,
2277 .enable_mask = BIT(4),
2278 .hw.init = &(struct clk_init_data){
2279 .name = "gsbi5_h_clk",
2280 .ops = &clk_branch_ops,
2281 .flags = CLK_IS_ROOT,
2282 },
2283 },
2284};
2285
2286static struct clk_branch gsbi6_h_clk = {
2287 .hwcg_reg = 0x2a60,
2288 .hwcg_bit = 6,
2289 .halt_reg = 0x2fd0,
2290 .halt_bit = 19,
2291 .clkr = {
2292 .enable_reg = 0x2a60,
2293 .enable_mask = BIT(4),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gsbi6_h_clk",
2296 .ops = &clk_branch_ops,
2297 .flags = CLK_IS_ROOT,
2298 },
2299 },
2300};
2301
2302static struct clk_branch gsbi7_h_clk = {
2303 .hwcg_reg = 0x2a80,
2304 .hwcg_bit = 6,
2305 .halt_reg = 0x2fd0,
2306 .halt_bit = 15,
2307 .clkr = {
2308 .enable_reg = 0x2a80,
2309 .enable_mask = BIT(4),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gsbi7_h_clk",
2312 .ops = &clk_branch_ops,
2313 .flags = CLK_IS_ROOT,
2314 },
2315 },
2316};
2317
2318static struct clk_branch gsbi8_h_clk = {
2319 .hwcg_reg = 0x2aa0,
2320 .hwcg_bit = 6,
2321 .halt_reg = 0x2fd0,
2322 .halt_bit = 11,
2323 .clkr = {
2324 .enable_reg = 0x2aa0,
2325 .enable_mask = BIT(4),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gsbi8_h_clk",
2328 .ops = &clk_branch_ops,
2329 .flags = CLK_IS_ROOT,
2330 },
2331 },
2332};
2333
2334static struct clk_branch gsbi9_h_clk = {
2335 .hwcg_reg = 0x2ac0,
2336 .hwcg_bit = 6,
2337 .halt_reg = 0x2fd0,
2338 .halt_bit = 7,
2339 .clkr = {
2340 .enable_reg = 0x2ac0,
2341 .enable_mask = BIT(4),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gsbi9_h_clk",
2344 .ops = &clk_branch_ops,
2345 .flags = CLK_IS_ROOT,
2346 },
2347 },
2348};
2349
2350static struct clk_branch gsbi10_h_clk = {
2351 .hwcg_reg = 0x2ae0,
2352 .hwcg_bit = 6,
2353 .halt_reg = 0x2fd0,
2354 .halt_bit = 3,
2355 .clkr = {
2356 .enable_reg = 0x2ae0,
2357 .enable_mask = BIT(4),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gsbi10_h_clk",
2360 .ops = &clk_branch_ops,
2361 .flags = CLK_IS_ROOT,
2362 },
2363 },
2364};
2365
2366static struct clk_branch gsbi11_h_clk = {
2367 .hwcg_reg = 0x2b00,
2368 .hwcg_bit = 6,
2369 .halt_reg = 0x2fd4,
2370 .halt_bit = 18,
2371 .clkr = {
2372 .enable_reg = 0x2b00,
2373 .enable_mask = BIT(4),
2374 .hw.init = &(struct clk_init_data){
2375 .name = "gsbi11_h_clk",
2376 .ops = &clk_branch_ops,
2377 .flags = CLK_IS_ROOT,
2378 },
2379 },
2380};
2381
2382static struct clk_branch gsbi12_h_clk = {
2383 .hwcg_reg = 0x2b20,
2384 .hwcg_bit = 6,
2385 .halt_reg = 0x2fd4,
2386 .halt_bit = 14,
2387 .clkr = {
2388 .enable_reg = 0x2b20,
2389 .enable_mask = BIT(4),
2390 .hw.init = &(struct clk_init_data){
2391 .name = "gsbi12_h_clk",
2392 .ops = &clk_branch_ops,
2393 .flags = CLK_IS_ROOT,
2394 },
2395 },
2396};
2397
2398static struct clk_branch tsif_h_clk = {
2399 .hwcg_reg = 0x2700,
2400 .hwcg_bit = 6,
2401 .halt_reg = 0x2fd4,
2402 .halt_bit = 7,
2403 .clkr = {
2404 .enable_reg = 0x2700,
2405 .enable_mask = BIT(4),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "tsif_h_clk",
2408 .ops = &clk_branch_ops,
2409 .flags = CLK_IS_ROOT,
2410 },
2411 },
2412};
2413
2414static struct clk_branch usb_fs1_h_clk = {
2415 .halt_reg = 0x2fcc,
2416 .halt_bit = 17,
2417 .clkr = {
2418 .enable_reg = 0x2960,
2419 .enable_mask = BIT(4),
2420 .hw.init = &(struct clk_init_data){
2421 .name = "usb_fs1_h_clk",
2422 .ops = &clk_branch_ops,
2423 .flags = CLK_IS_ROOT,
2424 },
2425 },
2426};
2427
2428static struct clk_branch usb_fs2_h_clk = {
2429 .halt_reg = 0x2fcc,
2430 .halt_bit = 14,
2431 .clkr = {
2432 .enable_reg = 0x2980,
2433 .enable_mask = BIT(4),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "usb_fs2_h_clk",
2436 .ops = &clk_branch_ops,
2437 .flags = CLK_IS_ROOT,
2438 },
2439 },
2440};
2441
2442static struct clk_branch usb_hs1_h_clk = {
2443 .hwcg_reg = 0x2900,
2444 .hwcg_bit = 6,
2445 .halt_reg = 0x2fc8,
2446 .halt_bit = 1,
2447 .clkr = {
2448 .enable_reg = 0x2900,
2449 .enable_mask = BIT(4),
2450 .hw.init = &(struct clk_init_data){
2451 .name = "usb_hs1_h_clk",
2452 .ops = &clk_branch_ops,
2453 .flags = CLK_IS_ROOT,
2454 },
2455 },
2456};
2457
2458static struct clk_branch usb_hsic_h_clk = {
2459 .halt_reg = 0x2fcc,
2460 .halt_bit = 28,
2461 .clkr = {
2462 .enable_reg = 0x2920,
2463 .enable_mask = BIT(4),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "usb_hsic_h_clk",
2466 .ops = &clk_branch_ops,
2467 .flags = CLK_IS_ROOT,
2468 },
2469 },
2470};
2471
2472static struct clk_branch sdc1_h_clk = {
2473 .hwcg_reg = 0x2820,
2474 .hwcg_bit = 6,
2475 .halt_reg = 0x2fc8,
2476 .halt_bit = 11,
2477 .clkr = {
2478 .enable_reg = 0x2820,
2479 .enable_mask = BIT(4),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "sdc1_h_clk",
2482 .ops = &clk_branch_ops,
2483 .flags = CLK_IS_ROOT,
2484 },
2485 },
2486};
2487
2488static struct clk_branch sdc2_h_clk = {
2489 .hwcg_reg = 0x2840,
2490 .hwcg_bit = 6,
2491 .halt_reg = 0x2fc8,
2492 .halt_bit = 10,
2493 .clkr = {
2494 .enable_reg = 0x2840,
2495 .enable_mask = BIT(4),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "sdc2_h_clk",
2498 .ops = &clk_branch_ops,
2499 .flags = CLK_IS_ROOT,
2500 },
2501 },
2502};
2503
2504static struct clk_branch sdc3_h_clk = {
2505 .hwcg_reg = 0x2860,
2506 .hwcg_bit = 6,
2507 .halt_reg = 0x2fc8,
2508 .halt_bit = 9,
2509 .clkr = {
2510 .enable_reg = 0x2860,
2511 .enable_mask = BIT(4),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "sdc3_h_clk",
2514 .ops = &clk_branch_ops,
2515 .flags = CLK_IS_ROOT,
2516 },
2517 },
2518};
2519
2520static struct clk_branch sdc4_h_clk = {
2521 .hwcg_reg = 0x2880,
2522 .hwcg_bit = 6,
2523 .halt_reg = 0x2fc8,
2524 .halt_bit = 8,
2525 .clkr = {
2526 .enable_reg = 0x2880,
2527 .enable_mask = BIT(4),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "sdc4_h_clk",
2530 .ops = &clk_branch_ops,
2531 .flags = CLK_IS_ROOT,
2532 },
2533 },
2534};
2535
2536static struct clk_branch sdc5_h_clk = {
2537 .hwcg_reg = 0x28a0,
2538 .hwcg_bit = 6,
2539 .halt_reg = 0x2fc8,
2540 .halt_bit = 7,
2541 .clkr = {
2542 .enable_reg = 0x28a0,
2543 .enable_mask = BIT(4),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "sdc5_h_clk",
2546 .ops = &clk_branch_ops,
2547 .flags = CLK_IS_ROOT,
2548 },
2549 },
2550};
2551
2552static struct clk_branch adm0_clk = {
2553 .halt_reg = 0x2fdc,
2554 .halt_check = BRANCH_HALT_VOTED,
2555 .halt_bit = 14,
2556 .clkr = {
2557 .enable_reg = 0x3080,
2558 .enable_mask = BIT(2),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "adm0_clk",
2561 .ops = &clk_branch_ops,
2562 .flags = CLK_IS_ROOT,
2563 },
2564 },
2565};
2566
2567static struct clk_branch adm0_pbus_clk = {
2568 .hwcg_reg = 0x2208,
2569 .hwcg_bit = 6,
2570 .halt_reg = 0x2fdc,
2571 .halt_check = BRANCH_HALT_VOTED,
2572 .halt_bit = 13,
2573 .clkr = {
2574 .enable_reg = 0x3080,
2575 .enable_mask = BIT(3),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "adm0_pbus_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2580 },
2581 },
2582};
2583
2584static struct clk_branch pmic_arb0_h_clk = {
2585 .halt_reg = 0x2fd8,
2586 .halt_check = BRANCH_HALT_VOTED,
2587 .halt_bit = 22,
2588 .clkr = {
2589 .enable_reg = 0x3080,
2590 .enable_mask = BIT(8),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "pmic_arb0_h_clk",
2593 .ops = &clk_branch_ops,
2594 .flags = CLK_IS_ROOT,
2595 },
2596 },
2597};
2598
2599static struct clk_branch pmic_arb1_h_clk = {
2600 .halt_reg = 0x2fd8,
2601 .halt_check = BRANCH_HALT_VOTED,
2602 .halt_bit = 21,
2603 .clkr = {
2604 .enable_reg = 0x3080,
2605 .enable_mask = BIT(9),
2606 .hw.init = &(struct clk_init_data){
2607 .name = "pmic_arb1_h_clk",
2608 .ops = &clk_branch_ops,
2609 .flags = CLK_IS_ROOT,
2610 },
2611 },
2612};
2613
2614static struct clk_branch pmic_ssbi2_clk = {
2615 .halt_reg = 0x2fd8,
2616 .halt_check = BRANCH_HALT_VOTED,
2617 .halt_bit = 23,
2618 .clkr = {
2619 .enable_reg = 0x3080,
2620 .enable_mask = BIT(7),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "pmic_ssbi2_clk",
2623 .ops = &clk_branch_ops,
2624 .flags = CLK_IS_ROOT,
2625 },
2626 },
2627};
2628
2629static struct clk_branch rpm_msg_ram_h_clk = {
2630 .hwcg_reg = 0x27e0,
2631 .hwcg_bit = 6,
2632 .halt_reg = 0x2fd8,
2633 .halt_check = BRANCH_HALT_VOTED,
2634 .halt_bit = 12,
2635 .clkr = {
2636 .enable_reg = 0x3080,
2637 .enable_mask = BIT(6),
2638 .hw.init = &(struct clk_init_data){
2639 .name = "rpm_msg_ram_h_clk",
2640 .ops = &clk_branch_ops,
2641 .flags = CLK_IS_ROOT,
2642 },
2643 },
2644};
2645
2646static struct clk_regmap *gcc_msm8960_clks[] = {
2647 [PLL3] = &pll3.clkr,
2648 [PLL8] = &pll8.clkr,
2649 [PLL8_VOTE] = &pll8_vote,
2650 [PLL14] = &pll14.clkr,
2651 [PLL14_VOTE] = &pll14_vote,
2652 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2653 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2654 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2655 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2656 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2657 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2658 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2659 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2660 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2661 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2662 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2663 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2664 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2665 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2666 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2667 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2668 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2669 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2670 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2671 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2672 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2673 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2674 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2675 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2676 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2677 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2678 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2679 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2680 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2681 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2682 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2683 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2684 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2685 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2686 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2687 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2688 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2689 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2690 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2691 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2692 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2693 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2694 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2695 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2696 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2697 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2698 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2699 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2700 [GP0_SRC] = &gp0_src.clkr,
2701 [GP0_CLK] = &gp0_clk.clkr,
2702 [GP1_SRC] = &gp1_src.clkr,
2703 [GP1_CLK] = &gp1_clk.clkr,
2704 [GP2_SRC] = &gp2_src.clkr,
2705 [GP2_CLK] = &gp2_clk.clkr,
2706 [PMEM_A_CLK] = &pmem_clk.clkr,
2707 [PRNG_SRC] = &prng_src.clkr,
2708 [PRNG_CLK] = &prng_clk.clkr,
2709 [SDC1_SRC] = &sdc1_src.clkr,
2710 [SDC1_CLK] = &sdc1_clk.clkr,
2711 [SDC2_SRC] = &sdc2_src.clkr,
2712 [SDC2_CLK] = &sdc2_clk.clkr,
2713 [SDC3_SRC] = &sdc3_src.clkr,
2714 [SDC3_CLK] = &sdc3_clk.clkr,
2715 [SDC4_SRC] = &sdc4_src.clkr,
2716 [SDC4_CLK] = &sdc4_clk.clkr,
2717 [SDC5_SRC] = &sdc5_src.clkr,
2718 [SDC5_CLK] = &sdc5_clk.clkr,
2719 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2720 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2721 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2722 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2723 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
2724 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
2725 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
2726 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
2727 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
2728 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2729 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2730 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2731 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2732 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2733 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2734 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
2735 [CE1_H_CLK] = &ce1_h_clk.clkr,
2736 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2737 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2738 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2739 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2740 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2741 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2742 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2743 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2744 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2745 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2746 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2747 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2748 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2749 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2750 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2751 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2752 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2753 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
2754 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2755 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2756 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2757 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2758 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2759 [ADM0_CLK] = &adm0_clk.clkr,
2760 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2761 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2762 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2763 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2764 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2765};
2766
2767static const struct qcom_reset_map gcc_msm8960_resets[] = {
2768 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
2769 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
2770 [QDSS_STM_RESET] = { 0x2060, 6 },
2771 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2772 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2773 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2774 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2775 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
2776 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2777 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2778 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2779 [ADM0_C2_RESET] = { 0x220c, 4},
2780 [ADM0_C1_RESET] = { 0x220c, 3},
2781 [ADM0_C0_RESET] = { 0x220c, 2},
2782 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2783 [ADM0_RESET] = { 0x220c },
2784 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2785 [QDSS_POR_RESET] = { 0x2260, 4 },
2786 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2787 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2788 [QDSS_AXI_RESET] = { 0x2260, 1 },
2789 [QDSS_DBG_RESET] = { 0x2260 },
2790 [PCIE_A_RESET] = { 0x22c0, 7 },
2791 [PCIE_AUX_RESET] = { 0x22c8, 7 },
2792 [PCIE_H_RESET] = { 0x22d0, 7 },
2793 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
2794 [SFAB_PCIE_S_RESET] = { 0x22d4 },
2795 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
2796 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
2797 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
2798 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2799 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2800 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2801 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2802 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2803 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2804 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2805 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2806 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2807 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2808 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2809 [PPSS_PROC_RESET] = { 0x2594, 1 },
2810 [PPSS_RESET] = { 0x2594},
2811 [DMA_BAM_RESET] = { 0x25c0, 7 },
2812 [SIC_TIC_RESET] = { 0x2600, 7 },
2813 [SLIMBUS_H_RESET] = { 0x2620, 7 },
2814 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2815 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2816 [TSIF_H_RESET] = { 0x2700, 7 },
2817 [CE1_H_RESET] = { 0x2720, 7 },
2818 [CE1_CORE_RESET] = { 0x2724, 7 },
2819 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2820 [CE2_H_RESET] = { 0x2740, 7 },
2821 [CE2_CORE_RESET] = { 0x2744, 7 },
2822 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2823 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2824 [RPM_PROC_RESET] = { 0x27c0, 7 },
2825 [PMIC_SSBI2_RESET] = { 0x270c, 12 },
2826 [SDC1_RESET] = { 0x2830 },
2827 [SDC2_RESET] = { 0x2850 },
2828 [SDC3_RESET] = { 0x2870 },
2829 [SDC4_RESET] = { 0x2890 },
2830 [SDC5_RESET] = { 0x28b0 },
2831 [DFAB_A2_RESET] = { 0x28c0, 7 },
2832 [USB_HS1_RESET] = { 0x2910 },
2833 [USB_HSIC_RESET] = { 0x2934 },
2834 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2835 [USB_FS1_RESET] = { 0x2974 },
2836 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2837 [USB_FS2_RESET] = { 0x2994 },
2838 [GSBI1_RESET] = { 0x29dc },
2839 [GSBI2_RESET] = { 0x29fc },
2840 [GSBI3_RESET] = { 0x2a1c },
2841 [GSBI4_RESET] = { 0x2a3c },
2842 [GSBI5_RESET] = { 0x2a5c },
2843 [GSBI6_RESET] = { 0x2a7c },
2844 [GSBI7_RESET] = { 0x2a9c },
2845 [GSBI8_RESET] = { 0x2abc },
2846 [GSBI9_RESET] = { 0x2adc },
2847 [GSBI10_RESET] = { 0x2afc },
2848 [GSBI11_RESET] = { 0x2b1c },
2849 [GSBI12_RESET] = { 0x2b3c },
2850 [SPDM_RESET] = { 0x2b6c },
2851 [TLMM_H_RESET] = { 0x2ba0, 7 },
2852 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2853 [MSS_SLP_RESET] = { 0x2c60, 7 },
2854 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
2855 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
2856 [MSS_RESET] = { 0x2c64 },
2857 [SATA_H_RESET] = { 0x2c80, 7 },
2858 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
2859 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
2860 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
2861 [TSSC_RESET] = { 0x2ca0, 7 },
2862 [PDM_RESET] = { 0x2cc0, 12 },
2863 [MPM_H_RESET] = { 0x2da0, 7 },
2864 [MPM_RESET] = { 0x2da4 },
2865 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2866 [PRNG_RESET] = { 0x2e80, 12 },
2867 [RIVA_RESET] = { 0x35e0 },
2868};
2869
2870static const struct regmap_config gcc_msm8960_regmap_config = {
2871 .reg_bits = 32,
2872 .reg_stride = 4,
2873 .val_bits = 32,
2874 .max_register = 0x3660,
2875 .fast_io = true,
2876};
2877
2878static const struct of_device_id gcc_msm8960_match_table[] = {
2879 { .compatible = "qcom,gcc-msm8960" },
2880 { }
2881};
2882MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
2883
2884struct qcom_cc {
2885 struct qcom_reset_controller reset;
2886 struct clk_onecell_data data;
2887 struct clk *clks[];
2888};
2889
2890static int gcc_msm8960_probe(struct platform_device *pdev)
2891{
2892 void __iomem *base;
2893 struct resource *res;
2894 int i, ret;
2895 struct device *dev = &pdev->dev;
2896 struct clk *clk;
2897 struct clk_onecell_data *data;
2898 struct clk **clks;
2899 struct regmap *regmap;
2900 size_t num_clks;
2901 struct qcom_reset_controller *reset;
2902 struct qcom_cc *cc;
2903
2904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2905 base = devm_ioremap_resource(dev, res);
2906 if (IS_ERR(base))
2907 return PTR_ERR(base);
2908
2909 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8960_regmap_config);
2910 if (IS_ERR(regmap))
2911 return PTR_ERR(regmap);
2912
2913 num_clks = ARRAY_SIZE(gcc_msm8960_clks);
2914 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2915 GFP_KERNEL);
2916 if (!cc)
2917 return -ENOMEM;
2918
2919 clks = cc->clks;
2920 data = &cc->data;
2921 data->clks = clks;
2922 data->clk_num = num_clks;
2923
2924 /* Temporary until RPM clocks supported */
2925 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2926 if (IS_ERR(clk))
2927 return PTR_ERR(clk);
2928
2929 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2930 if (IS_ERR(clk))
2931 return PTR_ERR(clk);
2932
2933 for (i = 0; i < num_clks; i++) {
2934 if (!gcc_msm8960_clks[i])
2935 continue;
2936 clk = devm_clk_register_regmap(dev, gcc_msm8960_clks[i]);
2937 if (IS_ERR(clk))
2938 return PTR_ERR(clk);
2939 clks[i] = clk;
2940 }
2941
2942 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2943 if (ret)
2944 return ret;
2945
2946 reset = &cc->reset;
2947 reset->rcdev.of_node = dev->of_node;
2948 reset->rcdev.ops = &qcom_reset_ops,
2949 reset->rcdev.owner = THIS_MODULE,
2950 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8960_resets),
2951 reset->regmap = regmap;
2952 reset->reset_map = gcc_msm8960_resets,
2953 platform_set_drvdata(pdev, &reset->rcdev);
2954
2955 ret = reset_controller_register(&reset->rcdev);
2956 if (ret)
2957 of_clk_del_provider(dev->of_node);
2958
2959 return ret;
2960}
2961
2962static int gcc_msm8960_remove(struct platform_device *pdev)
2963{
2964 of_clk_del_provider(pdev->dev.of_node);
2965 reset_controller_unregister(platform_get_drvdata(pdev));
2966 return 0;
2967}
2968
2969static struct platform_driver gcc_msm8960_driver = {
2970 .probe = gcc_msm8960_probe,
2971 .remove = gcc_msm8960_remove,
2972 .driver = {
2973 .name = "gcc-msm8960",
2974 .owner = THIS_MODULE,
2975 .of_match_table = gcc_msm8960_match_table,
2976 },
2977};
2978
2979static int __init gcc_msm8960_init(void)
2980{
2981 return platform_driver_register(&gcc_msm8960_driver);
2982}
2983core_initcall(gcc_msm8960_init);
2984
2985static void __exit gcc_msm8960_exit(void)
2986{
2987 platform_driver_unregister(&gcc_msm8960_driver);
2988}
2989module_exit(gcc_msm8960_exit);
2990
2991MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
2992MODULE_LICENSE("GPL v2");
2993MODULE_ALIAS("platform:gcc-msm8960");
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
new file mode 100644
index 000000000000..51d457e2b959
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -0,0 +1,2694 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8974.h>
26#include <dt-bindings/reset/qcom,gcc-msm8974.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define P_XO 0
35#define P_GPLL0 1
36#define P_GPLL1 1
37
38static const u8 gcc_xo_gpll0_map[] = {
39 [P_XO] = 0,
40 [P_GPLL0] = 1,
41};
42
43static const char *gcc_xo_gpll0[] = {
44 "xo",
45 "gpll0_vote",
46};
47
48#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
49
50static struct clk_pll gpll0 = {
51 .l_reg = 0x0004,
52 .m_reg = 0x0008,
53 .n_reg = 0x000c,
54 .config_reg = 0x0014,
55 .mode_reg = 0x0000,
56 .status_reg = 0x001c,
57 .status_bit = 17,
58 .clkr.hw.init = &(struct clk_init_data){
59 .name = "gpll0",
60 .parent_names = (const char *[]){ "xo" },
61 .num_parents = 1,
62 .ops = &clk_pll_ops,
63 },
64};
65
66static struct clk_regmap gpll0_vote = {
67 .enable_reg = 0x1480,
68 .enable_mask = BIT(0),
69 .hw.init = &(struct clk_init_data){
70 .name = "gpll0_vote",
71 .parent_names = (const char *[]){ "gpll0" },
72 .num_parents = 1,
73 .ops = &clk_pll_vote_ops,
74 },
75};
76
77static struct clk_rcg2 config_noc_clk_src = {
78 .cmd_rcgr = 0x0150,
79 .hid_width = 5,
80 .parent_map = gcc_xo_gpll0_map,
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "config_noc_clk_src",
83 .parent_names = gcc_xo_gpll0,
84 .num_parents = 2,
85 .ops = &clk_rcg2_ops,
86 },
87};
88
89static struct clk_rcg2 periph_noc_clk_src = {
90 .cmd_rcgr = 0x0190,
91 .hid_width = 5,
92 .parent_map = gcc_xo_gpll0_map,
93 .clkr.hw.init = &(struct clk_init_data){
94 .name = "periph_noc_clk_src",
95 .parent_names = gcc_xo_gpll0,
96 .num_parents = 2,
97 .ops = &clk_rcg2_ops,
98 },
99};
100
101static struct clk_rcg2 system_noc_clk_src = {
102 .cmd_rcgr = 0x0120,
103 .hid_width = 5,
104 .parent_map = gcc_xo_gpll0_map,
105 .clkr.hw.init = &(struct clk_init_data){
106 .name = "system_noc_clk_src",
107 .parent_names = gcc_xo_gpll0,
108 .num_parents = 2,
109 .ops = &clk_rcg2_ops,
110 },
111};
112
113static struct clk_pll gpll1 = {
114 .l_reg = 0x0044,
115 .m_reg = 0x0048,
116 .n_reg = 0x004c,
117 .config_reg = 0x0054,
118 .mode_reg = 0x0040,
119 .status_reg = 0x005c,
120 .status_bit = 17,
121 .clkr.hw.init = &(struct clk_init_data){
122 .name = "gpll1",
123 .parent_names = (const char *[]){ "xo" },
124 .num_parents = 1,
125 .ops = &clk_pll_ops,
126 },
127};
128
129static struct clk_regmap gpll1_vote = {
130 .enable_reg = 0x1480,
131 .enable_mask = BIT(1),
132 .hw.init = &(struct clk_init_data){
133 .name = "gpll1_vote",
134 .parent_names = (const char *[]){ "gpll1" },
135 .num_parents = 1,
136 .ops = &clk_pll_vote_ops,
137 },
138};
139
140static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
141 F(125000000, P_GPLL0, 1, 5, 24),
142 { }
143};
144
145static struct clk_rcg2 usb30_master_clk_src = {
146 .cmd_rcgr = 0x03d4,
147 .mnd_width = 8,
148 .hid_width = 5,
149 .parent_map = gcc_xo_gpll0_map,
150 .freq_tbl = ftbl_gcc_usb30_master_clk,
151 .clkr.hw.init = &(struct clk_init_data){
152 .name = "usb30_master_clk_src",
153 .parent_names = gcc_xo_gpll0,
154 .num_parents = 2,
155 .ops = &clk_rcg2_ops,
156 },
157};
158
159static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
160 F(19200000, P_XO, 1, 0, 0),
161 F(37500000, P_GPLL0, 16, 0, 0),
162 F(50000000, P_GPLL0, 12, 0, 0),
163 { }
164};
165
166static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
167 .cmd_rcgr = 0x0660,
168 .hid_width = 5,
169 .parent_map = gcc_xo_gpll0_map,
170 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
171 .clkr.hw.init = &(struct clk_init_data){
172 .name = "blsp1_qup1_i2c_apps_clk_src",
173 .parent_names = gcc_xo_gpll0,
174 .num_parents = 2,
175 .ops = &clk_rcg2_ops,
176 },
177};
178
179static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
180 F(960000, P_XO, 10, 1, 2),
181 F(4800000, P_XO, 4, 0, 0),
182 F(9600000, P_XO, 2, 0, 0),
183 F(15000000, P_GPLL0, 10, 1, 4),
184 F(19200000, P_XO, 1, 0, 0),
185 F(25000000, P_GPLL0, 12, 1, 2),
186 F(50000000, P_GPLL0, 12, 0, 0),
187 { }
188};
189
190static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
191 .cmd_rcgr = 0x064c,
192 .mnd_width = 8,
193 .hid_width = 5,
194 .parent_map = gcc_xo_gpll0_map,
195 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
196 .clkr.hw.init = &(struct clk_init_data){
197 .name = "blsp1_qup1_spi_apps_clk_src",
198 .parent_names = gcc_xo_gpll0,
199 .num_parents = 2,
200 .ops = &clk_rcg2_ops,
201 },
202};
203
204static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
205 .cmd_rcgr = 0x06e0,
206 .hid_width = 5,
207 .parent_map = gcc_xo_gpll0_map,
208 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
209 .clkr.hw.init = &(struct clk_init_data){
210 .name = "blsp1_qup2_i2c_apps_clk_src",
211 .parent_names = gcc_xo_gpll0,
212 .num_parents = 2,
213 .ops = &clk_rcg2_ops,
214 },
215};
216
217static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
218 .cmd_rcgr = 0x06cc,
219 .mnd_width = 8,
220 .hid_width = 5,
221 .parent_map = gcc_xo_gpll0_map,
222 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
223 .clkr.hw.init = &(struct clk_init_data){
224 .name = "blsp1_qup2_spi_apps_clk_src",
225 .parent_names = gcc_xo_gpll0,
226 .num_parents = 2,
227 .ops = &clk_rcg2_ops,
228 },
229};
230
231static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
232 .cmd_rcgr = 0x0760,
233 .hid_width = 5,
234 .parent_map = gcc_xo_gpll0_map,
235 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
236 .clkr.hw.init = &(struct clk_init_data){
237 .name = "blsp1_qup3_i2c_apps_clk_src",
238 .parent_names = gcc_xo_gpll0,
239 .num_parents = 2,
240 .ops = &clk_rcg2_ops,
241 },
242};
243
244static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
245 .cmd_rcgr = 0x074c,
246 .mnd_width = 8,
247 .hid_width = 5,
248 .parent_map = gcc_xo_gpll0_map,
249 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "blsp1_qup3_spi_apps_clk_src",
252 .parent_names = gcc_xo_gpll0,
253 .num_parents = 2,
254 .ops = &clk_rcg2_ops,
255 },
256};
257
258static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
259 .cmd_rcgr = 0x07e0,
260 .hid_width = 5,
261 .parent_map = gcc_xo_gpll0_map,
262 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
263 .clkr.hw.init = &(struct clk_init_data){
264 .name = "blsp1_qup4_i2c_apps_clk_src",
265 .parent_names = gcc_xo_gpll0,
266 .num_parents = 2,
267 .ops = &clk_rcg2_ops,
268 },
269};
270
271static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
272 .cmd_rcgr = 0x07cc,
273 .mnd_width = 8,
274 .hid_width = 5,
275 .parent_map = gcc_xo_gpll0_map,
276 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
277 .clkr.hw.init = &(struct clk_init_data){
278 .name = "blsp1_qup4_spi_apps_clk_src",
279 .parent_names = gcc_xo_gpll0,
280 .num_parents = 2,
281 .ops = &clk_rcg2_ops,
282 },
283};
284
285static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
286 .cmd_rcgr = 0x0860,
287 .hid_width = 5,
288 .parent_map = gcc_xo_gpll0_map,
289 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
290 .clkr.hw.init = &(struct clk_init_data){
291 .name = "blsp1_qup5_i2c_apps_clk_src",
292 .parent_names = gcc_xo_gpll0,
293 .num_parents = 2,
294 .ops = &clk_rcg2_ops,
295 },
296};
297
298static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
299 .cmd_rcgr = 0x084c,
300 .mnd_width = 8,
301 .hid_width = 5,
302 .parent_map = gcc_xo_gpll0_map,
303 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
304 .clkr.hw.init = &(struct clk_init_data){
305 .name = "blsp1_qup5_spi_apps_clk_src",
306 .parent_names = gcc_xo_gpll0,
307 .num_parents = 2,
308 .ops = &clk_rcg2_ops,
309 },
310};
311
312static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
313 .cmd_rcgr = 0x08e0,
314 .hid_width = 5,
315 .parent_map = gcc_xo_gpll0_map,
316 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
317 .clkr.hw.init = &(struct clk_init_data){
318 .name = "blsp1_qup6_i2c_apps_clk_src",
319 .parent_names = gcc_xo_gpll0,
320 .num_parents = 2,
321 .ops = &clk_rcg2_ops,
322 },
323};
324
325static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
326 .cmd_rcgr = 0x08cc,
327 .mnd_width = 8,
328 .hid_width = 5,
329 .parent_map = gcc_xo_gpll0_map,
330 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
331 .clkr.hw.init = &(struct clk_init_data){
332 .name = "blsp1_qup6_spi_apps_clk_src",
333 .parent_names = gcc_xo_gpll0,
334 .num_parents = 2,
335 .ops = &clk_rcg2_ops,
336 },
337};
338
339static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
340 F(3686400, P_GPLL0, 1, 96, 15625),
341 F(7372800, P_GPLL0, 1, 192, 15625),
342 F(14745600, P_GPLL0, 1, 384, 15625),
343 F(16000000, P_GPLL0, 5, 2, 15),
344 F(19200000, P_XO, 1, 0, 0),
345 F(24000000, P_GPLL0, 5, 1, 5),
346 F(32000000, P_GPLL0, 1, 4, 75),
347 F(40000000, P_GPLL0, 15, 0, 0),
348 F(46400000, P_GPLL0, 1, 29, 375),
349 F(48000000, P_GPLL0, 12.5, 0, 0),
350 F(51200000, P_GPLL0, 1, 32, 375),
351 F(56000000, P_GPLL0, 1, 7, 75),
352 F(58982400, P_GPLL0, 1, 1536, 15625),
353 F(60000000, P_GPLL0, 10, 0, 0),
354 F(63160000, P_GPLL0, 9.5, 0, 0),
355 { }
356};
357
358static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
359 .cmd_rcgr = 0x068c,
360 .mnd_width = 16,
361 .hid_width = 5,
362 .parent_map = gcc_xo_gpll0_map,
363 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "blsp1_uart1_apps_clk_src",
366 .parent_names = gcc_xo_gpll0,
367 .num_parents = 2,
368 .ops = &clk_rcg2_ops,
369 },
370};
371
372static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
373 .cmd_rcgr = 0x070c,
374 .mnd_width = 16,
375 .hid_width = 5,
376 .parent_map = gcc_xo_gpll0_map,
377 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "blsp1_uart2_apps_clk_src",
380 .parent_names = gcc_xo_gpll0,
381 .num_parents = 2,
382 .ops = &clk_rcg2_ops,
383 },
384};
385
386static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
387 .cmd_rcgr = 0x078c,
388 .mnd_width = 16,
389 .hid_width = 5,
390 .parent_map = gcc_xo_gpll0_map,
391 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
392 .clkr.hw.init = &(struct clk_init_data){
393 .name = "blsp1_uart3_apps_clk_src",
394 .parent_names = gcc_xo_gpll0,
395 .num_parents = 2,
396 .ops = &clk_rcg2_ops,
397 },
398};
399
400static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
401 .cmd_rcgr = 0x080c,
402 .mnd_width = 16,
403 .hid_width = 5,
404 .parent_map = gcc_xo_gpll0_map,
405 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "blsp1_uart4_apps_clk_src",
408 .parent_names = gcc_xo_gpll0,
409 .num_parents = 2,
410 .ops = &clk_rcg2_ops,
411 },
412};
413
414static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
415 .cmd_rcgr = 0x088c,
416 .mnd_width = 16,
417 .hid_width = 5,
418 .parent_map = gcc_xo_gpll0_map,
419 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "blsp1_uart5_apps_clk_src",
422 .parent_names = gcc_xo_gpll0,
423 .num_parents = 2,
424 .ops = &clk_rcg2_ops,
425 },
426};
427
428static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
429 .cmd_rcgr = 0x090c,
430 .mnd_width = 16,
431 .hid_width = 5,
432 .parent_map = gcc_xo_gpll0_map,
433 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "blsp1_uart6_apps_clk_src",
436 .parent_names = gcc_xo_gpll0,
437 .num_parents = 2,
438 .ops = &clk_rcg2_ops,
439 },
440};
441
442static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
443 .cmd_rcgr = 0x09a0,
444 .hid_width = 5,
445 .parent_map = gcc_xo_gpll0_map,
446 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "blsp2_qup1_i2c_apps_clk_src",
449 .parent_names = gcc_xo_gpll0,
450 .num_parents = 2,
451 .ops = &clk_rcg2_ops,
452 },
453};
454
455static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
456 .cmd_rcgr = 0x098c,
457 .mnd_width = 8,
458 .hid_width = 5,
459 .parent_map = gcc_xo_gpll0_map,
460 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
461 .clkr.hw.init = &(struct clk_init_data){
462 .name = "blsp2_qup1_spi_apps_clk_src",
463 .parent_names = gcc_xo_gpll0,
464 .num_parents = 2,
465 .ops = &clk_rcg2_ops,
466 },
467};
468
469static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
470 .cmd_rcgr = 0x0a20,
471 .hid_width = 5,
472 .parent_map = gcc_xo_gpll0_map,
473 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
474 .clkr.hw.init = &(struct clk_init_data){
475 .name = "blsp2_qup2_i2c_apps_clk_src",
476 .parent_names = gcc_xo_gpll0,
477 .num_parents = 2,
478 .ops = &clk_rcg2_ops,
479 },
480};
481
482static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
483 .cmd_rcgr = 0x0a0c,
484 .mnd_width = 8,
485 .hid_width = 5,
486 .parent_map = gcc_xo_gpll0_map,
487 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
488 .clkr.hw.init = &(struct clk_init_data){
489 .name = "blsp2_qup2_spi_apps_clk_src",
490 .parent_names = gcc_xo_gpll0,
491 .num_parents = 2,
492 .ops = &clk_rcg2_ops,
493 },
494};
495
496static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
497 .cmd_rcgr = 0x0aa0,
498 .hid_width = 5,
499 .parent_map = gcc_xo_gpll0_map,
500 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
501 .clkr.hw.init = &(struct clk_init_data){
502 .name = "blsp2_qup3_i2c_apps_clk_src",
503 .parent_names = gcc_xo_gpll0,
504 .num_parents = 2,
505 .ops = &clk_rcg2_ops,
506 },
507};
508
509static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
510 .cmd_rcgr = 0x0a8c,
511 .mnd_width = 8,
512 .hid_width = 5,
513 .parent_map = gcc_xo_gpll0_map,
514 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "blsp2_qup3_spi_apps_clk_src",
517 .parent_names = gcc_xo_gpll0,
518 .num_parents = 2,
519 .ops = &clk_rcg2_ops,
520 },
521};
522
523static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
524 .cmd_rcgr = 0x0b20,
525 .hid_width = 5,
526 .parent_map = gcc_xo_gpll0_map,
527 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
528 .clkr.hw.init = &(struct clk_init_data){
529 .name = "blsp2_qup4_i2c_apps_clk_src",
530 .parent_names = gcc_xo_gpll0,
531 .num_parents = 2,
532 .ops = &clk_rcg2_ops,
533 },
534};
535
536static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
537 .cmd_rcgr = 0x0b0c,
538 .mnd_width = 8,
539 .hid_width = 5,
540 .parent_map = gcc_xo_gpll0_map,
541 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
542 .clkr.hw.init = &(struct clk_init_data){
543 .name = "blsp2_qup4_spi_apps_clk_src",
544 .parent_names = gcc_xo_gpll0,
545 .num_parents = 2,
546 .ops = &clk_rcg2_ops,
547 },
548};
549
550static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
551 .cmd_rcgr = 0x0ba0,
552 .hid_width = 5,
553 .parent_map = gcc_xo_gpll0_map,
554 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "blsp2_qup5_i2c_apps_clk_src",
557 .parent_names = gcc_xo_gpll0,
558 .num_parents = 2,
559 .ops = &clk_rcg2_ops,
560 },
561};
562
563static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
564 .cmd_rcgr = 0x0b8c,
565 .mnd_width = 8,
566 .hid_width = 5,
567 .parent_map = gcc_xo_gpll0_map,
568 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
569 .clkr.hw.init = &(struct clk_init_data){
570 .name = "blsp2_qup5_spi_apps_clk_src",
571 .parent_names = gcc_xo_gpll0,
572 .num_parents = 2,
573 .ops = &clk_rcg2_ops,
574 },
575};
576
577static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
578 .cmd_rcgr = 0x0c20,
579 .hid_width = 5,
580 .parent_map = gcc_xo_gpll0_map,
581 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
582 .clkr.hw.init = &(struct clk_init_data){
583 .name = "blsp2_qup6_i2c_apps_clk_src",
584 .parent_names = gcc_xo_gpll0,
585 .num_parents = 2,
586 .ops = &clk_rcg2_ops,
587 },
588};
589
590static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
591 .cmd_rcgr = 0x0c0c,
592 .mnd_width = 8,
593 .hid_width = 5,
594 .parent_map = gcc_xo_gpll0_map,
595 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
596 .clkr.hw.init = &(struct clk_init_data){
597 .name = "blsp2_qup6_spi_apps_clk_src",
598 .parent_names = gcc_xo_gpll0,
599 .num_parents = 2,
600 .ops = &clk_rcg2_ops,
601 },
602};
603
604static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
605 .cmd_rcgr = 0x09cc,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "blsp2_uart1_apps_clk_src",
612 .parent_names = gcc_xo_gpll0,
613 .num_parents = 2,
614 .ops = &clk_rcg2_ops,
615 },
616};
617
618static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
619 .cmd_rcgr = 0x0a4c,
620 .mnd_width = 16,
621 .hid_width = 5,
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "blsp2_uart2_apps_clk_src",
626 .parent_names = gcc_xo_gpll0,
627 .num_parents = 2,
628 .ops = &clk_rcg2_ops,
629 },
630};
631
632static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
633 .cmd_rcgr = 0x0acc,
634 .mnd_width = 16,
635 .hid_width = 5,
636 .parent_map = gcc_xo_gpll0_map,
637 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "blsp2_uart3_apps_clk_src",
640 .parent_names = gcc_xo_gpll0,
641 .num_parents = 2,
642 .ops = &clk_rcg2_ops,
643 },
644};
645
646static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
647 .cmd_rcgr = 0x0b4c,
648 .mnd_width = 16,
649 .hid_width = 5,
650 .parent_map = gcc_xo_gpll0_map,
651 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "blsp2_uart4_apps_clk_src",
654 .parent_names = gcc_xo_gpll0,
655 .num_parents = 2,
656 .ops = &clk_rcg2_ops,
657 },
658};
659
660static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
661 .cmd_rcgr = 0x0bcc,
662 .mnd_width = 16,
663 .hid_width = 5,
664 .parent_map = gcc_xo_gpll0_map,
665 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
666 .clkr.hw.init = &(struct clk_init_data){
667 .name = "blsp2_uart5_apps_clk_src",
668 .parent_names = gcc_xo_gpll0,
669 .num_parents = 2,
670 .ops = &clk_rcg2_ops,
671 },
672};
673
674static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
675 .cmd_rcgr = 0x0c4c,
676 .mnd_width = 16,
677 .hid_width = 5,
678 .parent_map = gcc_xo_gpll0_map,
679 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
680 .clkr.hw.init = &(struct clk_init_data){
681 .name = "blsp2_uart6_apps_clk_src",
682 .parent_names = gcc_xo_gpll0,
683 .num_parents = 2,
684 .ops = &clk_rcg2_ops,
685 },
686};
687
688static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
689 F(50000000, P_GPLL0, 12, 0, 0),
690 F(75000000, P_GPLL0, 8, 0, 0),
691 F(100000000, P_GPLL0, 6, 0, 0),
692 F(150000000, P_GPLL0, 4, 0, 0),
693 { }
694};
695
696static struct clk_rcg2 ce1_clk_src = {
697 .cmd_rcgr = 0x1050,
698 .hid_width = 5,
699 .parent_map = gcc_xo_gpll0_map,
700 .freq_tbl = ftbl_gcc_ce1_clk,
701 .clkr.hw.init = &(struct clk_init_data){
702 .name = "ce1_clk_src",
703 .parent_names = gcc_xo_gpll0,
704 .num_parents = 2,
705 .ops = &clk_rcg2_ops,
706 },
707};
708
709static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
710 F(50000000, P_GPLL0, 12, 0, 0),
711 F(75000000, P_GPLL0, 8, 0, 0),
712 F(100000000, P_GPLL0, 6, 0, 0),
713 F(150000000, P_GPLL0, 4, 0, 0),
714 { }
715};
716
717static struct clk_rcg2 ce2_clk_src = {
718 .cmd_rcgr = 0x1090,
719 .hid_width = 5,
720 .parent_map = gcc_xo_gpll0_map,
721 .freq_tbl = ftbl_gcc_ce2_clk,
722 .clkr.hw.init = &(struct clk_init_data){
723 .name = "ce2_clk_src",
724 .parent_names = gcc_xo_gpll0,
725 .num_parents = 2,
726 .ops = &clk_rcg2_ops,
727 },
728};
729
730static const struct freq_tbl ftbl_gcc_gp_clk[] = {
731 F(4800000, P_XO, 4, 0, 0),
732 F(6000000, P_GPLL0, 10, 1, 10),
733 F(6750000, P_GPLL0, 1, 1, 89),
734 F(8000000, P_GPLL0, 15, 1, 5),
735 F(9600000, P_XO, 2, 0, 0),
736 F(16000000, P_GPLL0, 1, 2, 75),
737 F(19200000, P_XO, 1, 0, 0),
738 F(24000000, P_GPLL0, 5, 1, 5),
739 { }
740};
741
742
743static struct clk_rcg2 gp1_clk_src = {
744 .cmd_rcgr = 0x1904,
745 .mnd_width = 8,
746 .hid_width = 5,
747 .parent_map = gcc_xo_gpll0_map,
748 .freq_tbl = ftbl_gcc_gp_clk,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "gp1_clk_src",
751 .parent_names = gcc_xo_gpll0,
752 .num_parents = 2,
753 .ops = &clk_rcg2_ops,
754 },
755};
756
757static struct clk_rcg2 gp2_clk_src = {
758 .cmd_rcgr = 0x1944,
759 .mnd_width = 8,
760 .hid_width = 5,
761 .parent_map = gcc_xo_gpll0_map,
762 .freq_tbl = ftbl_gcc_gp_clk,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "gp2_clk_src",
765 .parent_names = gcc_xo_gpll0,
766 .num_parents = 2,
767 .ops = &clk_rcg2_ops,
768 },
769};
770
771static struct clk_rcg2 gp3_clk_src = {
772 .cmd_rcgr = 0x1984,
773 .mnd_width = 8,
774 .hid_width = 5,
775 .parent_map = gcc_xo_gpll0_map,
776 .freq_tbl = ftbl_gcc_gp_clk,
777 .clkr.hw.init = &(struct clk_init_data){
778 .name = "gp3_clk_src",
779 .parent_names = gcc_xo_gpll0,
780 .num_parents = 2,
781 .ops = &clk_rcg2_ops,
782 },
783};
784
785static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
786 F(60000000, P_GPLL0, 10, 0, 0),
787 { }
788};
789
790static struct clk_rcg2 pdm2_clk_src = {
791 .cmd_rcgr = 0x0cd0,
792 .hid_width = 5,
793 .parent_map = gcc_xo_gpll0_map,
794 .freq_tbl = ftbl_gcc_pdm2_clk,
795 .clkr.hw.init = &(struct clk_init_data){
796 .name = "pdm2_clk_src",
797 .parent_names = gcc_xo_gpll0,
798 .num_parents = 2,
799 .ops = &clk_rcg2_ops,
800 },
801};
802
803static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
804 F(144000, P_XO, 16, 3, 25),
805 F(400000, P_XO, 12, 1, 4),
806 F(20000000, P_GPLL0, 15, 1, 2),
807 F(25000000, P_GPLL0, 12, 1, 2),
808 F(50000000, P_GPLL0, 12, 0, 0),
809 F(100000000, P_GPLL0, 6, 0, 0),
810 F(200000000, P_GPLL0, 3, 0, 0),
811 { }
812};
813
814static struct clk_rcg2 sdcc1_apps_clk_src = {
815 .cmd_rcgr = 0x04d0,
816 .mnd_width = 8,
817 .hid_width = 5,
818 .parent_map = gcc_xo_gpll0_map,
819 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "sdcc1_apps_clk_src",
822 .parent_names = gcc_xo_gpll0,
823 .num_parents = 2,
824 .ops = &clk_rcg2_ops,
825 },
826};
827
828static struct clk_rcg2 sdcc2_apps_clk_src = {
829 .cmd_rcgr = 0x0510,
830 .mnd_width = 8,
831 .hid_width = 5,
832 .parent_map = gcc_xo_gpll0_map,
833 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "sdcc2_apps_clk_src",
836 .parent_names = gcc_xo_gpll0,
837 .num_parents = 2,
838 .ops = &clk_rcg2_ops,
839 },
840};
841
842static struct clk_rcg2 sdcc3_apps_clk_src = {
843 .cmd_rcgr = 0x0550,
844 .mnd_width = 8,
845 .hid_width = 5,
846 .parent_map = gcc_xo_gpll0_map,
847 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "sdcc3_apps_clk_src",
850 .parent_names = gcc_xo_gpll0,
851 .num_parents = 2,
852 .ops = &clk_rcg2_ops,
853 },
854};
855
856static struct clk_rcg2 sdcc4_apps_clk_src = {
857 .cmd_rcgr = 0x0590,
858 .mnd_width = 8,
859 .hid_width = 5,
860 .parent_map = gcc_xo_gpll0_map,
861 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
862 .clkr.hw.init = &(struct clk_init_data){
863 .name = "sdcc4_apps_clk_src",
864 .parent_names = gcc_xo_gpll0,
865 .num_parents = 2,
866 .ops = &clk_rcg2_ops,
867 },
868};
869
870static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
871 F(105000, P_XO, 2, 1, 91),
872 { }
873};
874
875static struct clk_rcg2 tsif_ref_clk_src = {
876 .cmd_rcgr = 0x0d90,
877 .mnd_width = 8,
878 .hid_width = 5,
879 .parent_map = gcc_xo_gpll0_map,
880 .freq_tbl = ftbl_gcc_tsif_ref_clk,
881 .clkr.hw.init = &(struct clk_init_data){
882 .name = "tsif_ref_clk_src",
883 .parent_names = gcc_xo_gpll0,
884 .num_parents = 2,
885 .ops = &clk_rcg2_ops,
886 },
887};
888
889static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
890 F(60000000, P_GPLL0, 10, 0, 0),
891 { }
892};
893
894static struct clk_rcg2 usb30_mock_utmi_clk_src = {
895 .cmd_rcgr = 0x03e8,
896 .hid_width = 5,
897 .parent_map = gcc_xo_gpll0_map,
898 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
899 .clkr.hw.init = &(struct clk_init_data){
900 .name = "usb30_mock_utmi_clk_src",
901 .parent_names = gcc_xo_gpll0,
902 .num_parents = 2,
903 .ops = &clk_rcg2_ops,
904 },
905};
906
907static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
908 F(60000000, P_GPLL0, 10, 0, 0),
909 F(75000000, P_GPLL0, 8, 0, 0),
910 { }
911};
912
913static struct clk_rcg2 usb_hs_system_clk_src = {
914 .cmd_rcgr = 0x0490,
915 .hid_width = 5,
916 .parent_map = gcc_xo_gpll0_map,
917 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
918 .clkr.hw.init = &(struct clk_init_data){
919 .name = "usb_hs_system_clk_src",
920 .parent_names = gcc_xo_gpll0,
921 .num_parents = 2,
922 .ops = &clk_rcg2_ops,
923 },
924};
925
926static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
927 F(480000000, P_GPLL1, 1, 0, 0),
928 { }
929};
930
931static u8 usb_hsic_clk_src_map[] = {
932 [P_XO] = 0,
933 [P_GPLL1] = 4,
934};
935
936static struct clk_rcg2 usb_hsic_clk_src = {
937 .cmd_rcgr = 0x0440,
938 .hid_width = 5,
939 .parent_map = usb_hsic_clk_src_map,
940 .freq_tbl = ftbl_gcc_usb_hsic_clk,
941 .clkr.hw.init = &(struct clk_init_data){
942 .name = "usb_hsic_clk_src",
943 .parent_names = (const char *[]){
944 "xo",
945 "gpll1_vote",
946 },
947 .num_parents = 2,
948 .ops = &clk_rcg2_ops,
949 },
950};
951
952static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
953 F(9600000, P_XO, 2, 0, 0),
954 { }
955};
956
957static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
958 .cmd_rcgr = 0x0458,
959 .hid_width = 5,
960 .parent_map = gcc_xo_gpll0_map,
961 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
962 .clkr.hw.init = &(struct clk_init_data){
963 .name = "usb_hsic_io_cal_clk_src",
964 .parent_names = gcc_xo_gpll0,
965 .num_parents = 1,
966 .ops = &clk_rcg2_ops,
967 },
968};
969
970static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
971 F(60000000, P_GPLL0, 10, 0, 0),
972 F(75000000, P_GPLL0, 8, 0, 0),
973 { }
974};
975
976static struct clk_rcg2 usb_hsic_system_clk_src = {
977 .cmd_rcgr = 0x041c,
978 .hid_width = 5,
979 .parent_map = gcc_xo_gpll0_map,
980 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
981 .clkr.hw.init = &(struct clk_init_data){
982 .name = "usb_hsic_system_clk_src",
983 .parent_names = gcc_xo_gpll0,
984 .num_parents = 2,
985 .ops = &clk_rcg2_ops,
986 },
987};
988
989static struct clk_regmap gcc_mmss_gpll0_clk_src = {
990 .enable_reg = 0x1484,
991 .enable_mask = BIT(26),
992 .hw.init = &(struct clk_init_data){
993 .name = "mmss_gpll0_vote",
994 .parent_names = (const char *[]){
995 "gpll0_vote",
996 },
997 .num_parents = 1,
998 .ops = &clk_branch_simple_ops,
999 },
1000};
1001
1002static struct clk_branch gcc_bam_dma_ahb_clk = {
1003 .halt_reg = 0x0d44,
1004 .halt_check = BRANCH_HALT_VOTED,
1005 .clkr = {
1006 .enable_reg = 0x1484,
1007 .enable_mask = BIT(12),
1008 .hw.init = &(struct clk_init_data){
1009 .name = "gcc_bam_dma_ahb_clk",
1010 .parent_names = (const char *[]){
1011 "periph_noc_clk_src",
1012 },
1013 .num_parents = 1,
1014 .ops = &clk_branch2_ops,
1015 },
1016 },
1017};
1018
1019static struct clk_branch gcc_blsp1_ahb_clk = {
1020 .halt_reg = 0x05c4,
1021 .halt_check = BRANCH_HALT_VOTED,
1022 .clkr = {
1023 .enable_reg = 0x1484,
1024 .enable_mask = BIT(17),
1025 .hw.init = &(struct clk_init_data){
1026 .name = "gcc_blsp1_ahb_clk",
1027 .parent_names = (const char *[]){
1028 "periph_noc_clk_src",
1029 },
1030 .num_parents = 1,
1031 .ops = &clk_branch2_ops,
1032 },
1033 },
1034};
1035
1036static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1037 .halt_reg = 0x0648,
1038 .clkr = {
1039 .enable_reg = 0x0648,
1040 .enable_mask = BIT(0),
1041 .hw.init = &(struct clk_init_data){
1042 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1043 .parent_names = (const char *[]){
1044 "blsp1_qup1_i2c_apps_clk_src",
1045 },
1046 .num_parents = 1,
1047 .flags = CLK_SET_RATE_PARENT,
1048 .ops = &clk_branch2_ops,
1049 },
1050 },
1051};
1052
1053static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1054 .halt_reg = 0x0644,
1055 .clkr = {
1056 .enable_reg = 0x0644,
1057 .enable_mask = BIT(0),
1058 .hw.init = &(struct clk_init_data){
1059 .name = "gcc_blsp1_qup1_spi_apps_clk",
1060 .parent_names = (const char *[]){
1061 "blsp1_qup1_spi_apps_clk_src",
1062 },
1063 .num_parents = 1,
1064 .flags = CLK_SET_RATE_PARENT,
1065 .ops = &clk_branch2_ops,
1066 },
1067 },
1068};
1069
1070static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1071 .halt_reg = 0x06c8,
1072 .clkr = {
1073 .enable_reg = 0x06c8,
1074 .enable_mask = BIT(0),
1075 .hw.init = &(struct clk_init_data){
1076 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1077 .parent_names = (const char *[]){
1078 "blsp1_qup2_i2c_apps_clk_src",
1079 },
1080 .num_parents = 1,
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_branch2_ops,
1083 },
1084 },
1085};
1086
1087static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1088 .halt_reg = 0x06c4,
1089 .clkr = {
1090 .enable_reg = 0x06c4,
1091 .enable_mask = BIT(0),
1092 .hw.init = &(struct clk_init_data){
1093 .name = "gcc_blsp1_qup2_spi_apps_clk",
1094 .parent_names = (const char *[]){
1095 "blsp1_qup2_spi_apps_clk_src",
1096 },
1097 .num_parents = 1,
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_branch2_ops,
1100 },
1101 },
1102};
1103
1104static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1105 .halt_reg = 0x0748,
1106 .clkr = {
1107 .enable_reg = 0x0748,
1108 .enable_mask = BIT(0),
1109 .hw.init = &(struct clk_init_data){
1110 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1111 .parent_names = (const char *[]){
1112 "blsp1_qup3_i2c_apps_clk_src",
1113 },
1114 .num_parents = 1,
1115 .flags = CLK_SET_RATE_PARENT,
1116 .ops = &clk_branch2_ops,
1117 },
1118 },
1119};
1120
1121static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1122 .halt_reg = 0x0744,
1123 .clkr = {
1124 .enable_reg = 0x0744,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gcc_blsp1_qup3_spi_apps_clk",
1128 .parent_names = (const char *[]){
1129 "blsp1_qup3_spi_apps_clk_src",
1130 },
1131 .num_parents = 1,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136};
1137
1138static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1139 .halt_reg = 0x07c8,
1140 .clkr = {
1141 .enable_reg = 0x07c8,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1145 .parent_names = (const char *[]){
1146 "blsp1_qup4_i2c_apps_clk_src",
1147 },
1148 .num_parents = 1,
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1151 },
1152 },
1153};
1154
1155static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1156 .halt_reg = 0x07c4,
1157 .clkr = {
1158 .enable_reg = 0x07c4,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "gcc_blsp1_qup4_spi_apps_clk",
1162 .parent_names = (const char *[]){
1163 "blsp1_qup4_spi_apps_clk_src",
1164 },
1165 .num_parents = 1,
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1168 },
1169 },
1170};
1171
1172static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1173 .halt_reg = 0x0848,
1174 .clkr = {
1175 .enable_reg = 0x0848,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1179 .parent_names = (const char *[]){
1180 "blsp1_qup5_i2c_apps_clk_src",
1181 },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1190 .halt_reg = 0x0844,
1191 .clkr = {
1192 .enable_reg = 0x0844,
1193 .enable_mask = BIT(0),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "gcc_blsp1_qup5_spi_apps_clk",
1196 .parent_names = (const char *[]){
1197 "blsp1_qup5_spi_apps_clk_src",
1198 },
1199 .num_parents = 1,
1200 .flags = CLK_SET_RATE_PARENT,
1201 .ops = &clk_branch2_ops,
1202 },
1203 },
1204};
1205
1206static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1207 .halt_reg = 0x08c8,
1208 .clkr = {
1209 .enable_reg = 0x08c8,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1213 .parent_names = (const char *[]){
1214 "blsp1_qup6_i2c_apps_clk_src",
1215 },
1216 .num_parents = 1,
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1219 },
1220 },
1221};
1222
1223static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1224 .halt_reg = 0x08c4,
1225 .clkr = {
1226 .enable_reg = 0x08c4,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gcc_blsp1_qup6_spi_apps_clk",
1230 .parent_names = (const char *[]){
1231 "blsp1_qup6_spi_apps_clk_src",
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238};
1239
1240static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1241 .halt_reg = 0x0684,
1242 .clkr = {
1243 .enable_reg = 0x0684,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "gcc_blsp1_uart1_apps_clk",
1247 .parent_names = (const char *[]){
1248 "blsp1_uart1_apps_clk_src",
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1258 .halt_reg = 0x0704,
1259 .clkr = {
1260 .enable_reg = 0x0704,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_blsp1_uart2_apps_clk",
1264 .parent_names = (const char *[]){
1265 "blsp1_uart2_apps_clk_src",
1266 },
1267 .num_parents = 1,
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1270 },
1271 },
1272};
1273
1274static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1275 .halt_reg = 0x0784,
1276 .clkr = {
1277 .enable_reg = 0x0784,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_blsp1_uart3_apps_clk",
1281 .parent_names = (const char *[]){
1282 "blsp1_uart3_apps_clk_src",
1283 },
1284 .num_parents = 1,
1285 .flags = CLK_SET_RATE_PARENT,
1286 .ops = &clk_branch2_ops,
1287 },
1288 },
1289};
1290
1291static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1292 .halt_reg = 0x0804,
1293 .clkr = {
1294 .enable_reg = 0x0804,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_blsp1_uart4_apps_clk",
1298 .parent_names = (const char *[]){
1299 "blsp1_uart4_apps_clk_src",
1300 },
1301 .num_parents = 1,
1302 .flags = CLK_SET_RATE_PARENT,
1303 .ops = &clk_branch2_ops,
1304 },
1305 },
1306};
1307
1308static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1309 .halt_reg = 0x0884,
1310 .clkr = {
1311 .enable_reg = 0x0884,
1312 .enable_mask = BIT(0),
1313 .hw.init = &(struct clk_init_data){
1314 .name = "gcc_blsp1_uart5_apps_clk",
1315 .parent_names = (const char *[]){
1316 "blsp1_uart5_apps_clk_src",
1317 },
1318 .num_parents = 1,
1319 .flags = CLK_SET_RATE_PARENT,
1320 .ops = &clk_branch2_ops,
1321 },
1322 },
1323};
1324
1325static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1326 .halt_reg = 0x0904,
1327 .clkr = {
1328 .enable_reg = 0x0904,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "gcc_blsp1_uart6_apps_clk",
1332 .parent_names = (const char *[]){
1333 "blsp1_uart6_apps_clk_src",
1334 },
1335 .num_parents = 1,
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1338 },
1339 },
1340};
1341
1342static struct clk_branch gcc_blsp2_ahb_clk = {
1343 .halt_reg = 0x05c4,
1344 .halt_check = BRANCH_HALT_VOTED,
1345 .clkr = {
1346 .enable_reg = 0x1484,
1347 .enable_mask = BIT(15),
1348 .hw.init = &(struct clk_init_data){
1349 .name = "gcc_blsp2_ahb_clk",
1350 .parent_names = (const char *[]){
1351 "periph_noc_clk_src",
1352 },
1353 .num_parents = 1,
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357};
1358
1359static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1360 .halt_reg = 0x0988,
1361 .clkr = {
1362 .enable_reg = 0x0988,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1366 .parent_names = (const char *[]){
1367 "blsp2_qup1_i2c_apps_clk_src",
1368 },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374};
1375
1376static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1377 .halt_reg = 0x0984,
1378 .clkr = {
1379 .enable_reg = 0x0984,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gcc_blsp2_qup1_spi_apps_clk",
1383 .parent_names = (const char *[]){
1384 "blsp2_qup1_spi_apps_clk_src",
1385 },
1386 .num_parents = 1,
1387 .flags = CLK_SET_RATE_PARENT,
1388 .ops = &clk_branch2_ops,
1389 },
1390 },
1391};
1392
1393static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1394 .halt_reg = 0x0a08,
1395 .clkr = {
1396 .enable_reg = 0x0a08,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1400 .parent_names = (const char *[]){
1401 "blsp2_qup2_i2c_apps_clk_src",
1402 },
1403 .num_parents = 1,
1404 .flags = CLK_SET_RATE_PARENT,
1405 .ops = &clk_branch2_ops,
1406 },
1407 },
1408};
1409
1410static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1411 .halt_reg = 0x0a04,
1412 .clkr = {
1413 .enable_reg = 0x0a04,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data){
1416 .name = "gcc_blsp2_qup2_spi_apps_clk",
1417 .parent_names = (const char *[]){
1418 "blsp2_qup2_spi_apps_clk_src",
1419 },
1420 .num_parents = 1,
1421 .flags = CLK_SET_RATE_PARENT,
1422 .ops = &clk_branch2_ops,
1423 },
1424 },
1425};
1426
1427static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1428 .halt_reg = 0x0a88,
1429 .clkr = {
1430 .enable_reg = 0x0a88,
1431 .enable_mask = BIT(0),
1432 .hw.init = &(struct clk_init_data){
1433 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1434 .parent_names = (const char *[]){
1435 "blsp2_qup3_i2c_apps_clk_src",
1436 },
1437 .num_parents = 1,
1438 .flags = CLK_SET_RATE_PARENT,
1439 .ops = &clk_branch2_ops,
1440 },
1441 },
1442};
1443
1444static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1445 .halt_reg = 0x0a84,
1446 .clkr = {
1447 .enable_reg = 0x0a84,
1448 .enable_mask = BIT(0),
1449 .hw.init = &(struct clk_init_data){
1450 .name = "gcc_blsp2_qup3_spi_apps_clk",
1451 .parent_names = (const char *[]){
1452 "blsp2_qup3_spi_apps_clk_src",
1453 },
1454 .num_parents = 1,
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1462 .halt_reg = 0x0b08,
1463 .clkr = {
1464 .enable_reg = 0x0b08,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1468 .parent_names = (const char *[]){
1469 "blsp2_qup4_i2c_apps_clk_src",
1470 },
1471 .num_parents = 1,
1472 .flags = CLK_SET_RATE_PARENT,
1473 .ops = &clk_branch2_ops,
1474 },
1475 },
1476};
1477
1478static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1479 .halt_reg = 0x0b04,
1480 .clkr = {
1481 .enable_reg = 0x0b04,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(struct clk_init_data){
1484 .name = "gcc_blsp2_qup4_spi_apps_clk",
1485 .parent_names = (const char *[]){
1486 "blsp2_qup4_spi_apps_clk_src",
1487 },
1488 .num_parents = 1,
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1491 },
1492 },
1493};
1494
1495static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1496 .halt_reg = 0x0b88,
1497 .clkr = {
1498 .enable_reg = 0x0b88,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1502 .parent_names = (const char *[]){
1503 "blsp2_qup5_i2c_apps_clk_src",
1504 },
1505 .num_parents = 1,
1506 .flags = CLK_SET_RATE_PARENT,
1507 .ops = &clk_branch2_ops,
1508 },
1509 },
1510};
1511
1512static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1513 .halt_reg = 0x0b84,
1514 .clkr = {
1515 .enable_reg = 0x0b84,
1516 .enable_mask = BIT(0),
1517 .hw.init = &(struct clk_init_data){
1518 .name = "gcc_blsp2_qup5_spi_apps_clk",
1519 .parent_names = (const char *[]){
1520 "blsp2_qup5_spi_apps_clk_src",
1521 },
1522 .num_parents = 1,
1523 .flags = CLK_SET_RATE_PARENT,
1524 .ops = &clk_branch2_ops,
1525 },
1526 },
1527};
1528
1529static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1530 .halt_reg = 0x0c08,
1531 .clkr = {
1532 .enable_reg = 0x0c08,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1536 .parent_names = (const char *[]){
1537 "blsp2_qup6_i2c_apps_clk_src",
1538 },
1539 .num_parents = 1,
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1542 },
1543 },
1544};
1545
1546static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1547 .halt_reg = 0x0c04,
1548 .clkr = {
1549 .enable_reg = 0x0c04,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(struct clk_init_data){
1552 .name = "gcc_blsp2_qup6_spi_apps_clk",
1553 .parent_names = (const char *[]){
1554 "blsp2_qup6_spi_apps_clk_src",
1555 },
1556 .num_parents = 1,
1557 .flags = CLK_SET_RATE_PARENT,
1558 .ops = &clk_branch2_ops,
1559 },
1560 },
1561};
1562
1563static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1564 .halt_reg = 0x09c4,
1565 .clkr = {
1566 .enable_reg = 0x09c4,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "gcc_blsp2_uart1_apps_clk",
1570 .parent_names = (const char *[]){
1571 "blsp2_uart1_apps_clk_src",
1572 },
1573 .num_parents = 1,
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1576 },
1577 },
1578};
1579
1580static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1581 .halt_reg = 0x0a44,
1582 .clkr = {
1583 .enable_reg = 0x0a44,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "gcc_blsp2_uart2_apps_clk",
1587 .parent_names = (const char *[]){
1588 "blsp2_uart2_apps_clk_src",
1589 },
1590 .num_parents = 1,
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1593 },
1594 },
1595};
1596
1597static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1598 .halt_reg = 0x0ac4,
1599 .clkr = {
1600 .enable_reg = 0x0ac4,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "gcc_blsp2_uart3_apps_clk",
1604 .parent_names = (const char *[]){
1605 "blsp2_uart3_apps_clk_src",
1606 },
1607 .num_parents = 1,
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1610 },
1611 },
1612};
1613
1614static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1615 .halt_reg = 0x0b44,
1616 .clkr = {
1617 .enable_reg = 0x0b44,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_blsp2_uart4_apps_clk",
1621 .parent_names = (const char *[]){
1622 "blsp2_uart4_apps_clk_src",
1623 },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1632 .halt_reg = 0x0bc4,
1633 .clkr = {
1634 .enable_reg = 0x0bc4,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp2_uart5_apps_clk",
1638 .parent_names = (const char *[]){
1639 "blsp2_uart5_apps_clk_src",
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646};
1647
1648static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1649 .halt_reg = 0x0c44,
1650 .clkr = {
1651 .enable_reg = 0x0c44,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "gcc_blsp2_uart6_apps_clk",
1655 .parent_names = (const char *[]){
1656 "blsp2_uart6_apps_clk_src",
1657 },
1658 .num_parents = 1,
1659 .flags = CLK_SET_RATE_PARENT,
1660 .ops = &clk_branch2_ops,
1661 },
1662 },
1663};
1664
1665static struct clk_branch gcc_boot_rom_ahb_clk = {
1666 .halt_reg = 0x0e04,
1667 .halt_check = BRANCH_HALT_VOTED,
1668 .clkr = {
1669 .enable_reg = 0x1484,
1670 .enable_mask = BIT(10),
1671 .hw.init = &(struct clk_init_data){
1672 .name = "gcc_boot_rom_ahb_clk",
1673 .parent_names = (const char *[]){
1674 "config_noc_clk_src",
1675 },
1676 .num_parents = 1,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680};
1681
1682static struct clk_branch gcc_ce1_ahb_clk = {
1683 .halt_reg = 0x104c,
1684 .halt_check = BRANCH_HALT_VOTED,
1685 .clkr = {
1686 .enable_reg = 0x1484,
1687 .enable_mask = BIT(3),
1688 .hw.init = &(struct clk_init_data){
1689 .name = "gcc_ce1_ahb_clk",
1690 .parent_names = (const char *[]){
1691 "config_noc_clk_src",
1692 },
1693 .num_parents = 1,
1694 .ops = &clk_branch2_ops,
1695 },
1696 },
1697};
1698
1699static struct clk_branch gcc_ce1_axi_clk = {
1700 .halt_reg = 0x1048,
1701 .halt_check = BRANCH_HALT_VOTED,
1702 .clkr = {
1703 .enable_reg = 0x1484,
1704 .enable_mask = BIT(4),
1705 .hw.init = &(struct clk_init_data){
1706 .name = "gcc_ce1_axi_clk",
1707 .parent_names = (const char *[]){
1708 "system_noc_clk_src",
1709 },
1710 .num_parents = 1,
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch gcc_ce1_clk = {
1717 .halt_reg = 0x1050,
1718 .halt_check = BRANCH_HALT_VOTED,
1719 .clkr = {
1720 .enable_reg = 0x1484,
1721 .enable_mask = BIT(5),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_ce1_clk",
1724 .parent_names = (const char *[]){
1725 "ce1_clk_src",
1726 },
1727 .num_parents = 1,
1728 .ops = &clk_branch2_ops,
1729 },
1730 },
1731};
1732
1733static struct clk_branch gcc_ce2_ahb_clk = {
1734 .halt_reg = 0x108c,
1735 .halt_check = BRANCH_HALT_VOTED,
1736 .clkr = {
1737 .enable_reg = 0x1484,
1738 .enable_mask = BIT(0),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "gcc_ce2_ahb_clk",
1741 .parent_names = (const char *[]){
1742 "config_noc_clk_src",
1743 },
1744 .num_parents = 1,
1745 .ops = &clk_branch2_ops,
1746 },
1747 },
1748};
1749
1750static struct clk_branch gcc_ce2_axi_clk = {
1751 .halt_reg = 0x1088,
1752 .halt_check = BRANCH_HALT_VOTED,
1753 .clkr = {
1754 .enable_reg = 0x1484,
1755 .enable_mask = BIT(1),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_ce2_axi_clk",
1758 .parent_names = (const char *[]){
1759 "system_noc_clk_src",
1760 },
1761 .num_parents = 1,
1762 .ops = &clk_branch2_ops,
1763 },
1764 },
1765};
1766
1767static struct clk_branch gcc_ce2_clk = {
1768 .halt_reg = 0x1090,
1769 .halt_check = BRANCH_HALT_VOTED,
1770 .clkr = {
1771 .enable_reg = 0x1484,
1772 .enable_mask = BIT(2),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_ce2_clk",
1775 .parent_names = (const char *[]){
1776 "ce2_clk_src",
1777 },
1778 .num_parents = 1,
1779 .flags = CLK_SET_RATE_PARENT,
1780 .ops = &clk_branch2_ops,
1781 },
1782 },
1783};
1784
1785static struct clk_branch gcc_gp1_clk = {
1786 .halt_reg = 0x1900,
1787 .clkr = {
1788 .enable_reg = 0x1900,
1789 .enable_mask = BIT(0),
1790 .hw.init = &(struct clk_init_data){
1791 .name = "gcc_gp1_clk",
1792 .parent_names = (const char *[]){
1793 "gp1_clk_src",
1794 },
1795 .num_parents = 1,
1796 .flags = CLK_SET_RATE_PARENT,
1797 .ops = &clk_branch2_ops,
1798 },
1799 },
1800};
1801
1802static struct clk_branch gcc_gp2_clk = {
1803 .halt_reg = 0x1940,
1804 .clkr = {
1805 .enable_reg = 0x1940,
1806 .enable_mask = BIT(0),
1807 .hw.init = &(struct clk_init_data){
1808 .name = "gcc_gp2_clk",
1809 .parent_names = (const char *[]){
1810 "gp2_clk_src",
1811 },
1812 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT,
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817};
1818
1819static struct clk_branch gcc_gp3_clk = {
1820 .halt_reg = 0x1980,
1821 .clkr = {
1822 .enable_reg = 0x1980,
1823 .enable_mask = BIT(0),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "gcc_gp3_clk",
1826 .parent_names = (const char *[]){
1827 "gp3_clk_src",
1828 },
1829 .num_parents = 1,
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1832 },
1833 },
1834};
1835
1836static struct clk_branch gcc_lpass_q6_axi_clk = {
1837 .halt_reg = 0x11c0,
1838 .clkr = {
1839 .enable_reg = 0x11c0,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_lpass_q6_axi_clk",
1843 .parent_names = (const char *[]){
1844 "system_noc_clk_src",
1845 },
1846 .num_parents = 1,
1847 .ops = &clk_branch2_ops,
1848 },
1849 },
1850};
1851
1852static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1853 .halt_reg = 0x024c,
1854 .clkr = {
1855 .enable_reg = 0x024c,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_mmss_noc_cfg_ahb_clk",
1859 .parent_names = (const char *[]){
1860 "config_noc_clk_src",
1861 },
1862 .num_parents = 1,
1863 .ops = &clk_branch2_ops,
1864 .flags = CLK_IGNORE_UNUSED,
1865 },
1866 },
1867};
1868
1869static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
1870 .halt_reg = 0x0248,
1871 .clkr = {
1872 .enable_reg = 0x0248,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_ocmem_noc_cfg_ahb_clk",
1876 .parent_names = (const char *[]){
1877 "config_noc_clk_src",
1878 },
1879 .num_parents = 1,
1880 .ops = &clk_branch2_ops,
1881 },
1882 },
1883};
1884
1885static struct clk_branch gcc_mss_cfg_ahb_clk = {
1886 .halt_reg = 0x0280,
1887 .clkr = {
1888 .enable_reg = 0x0280,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_mss_cfg_ahb_clk",
1892 .parent_names = (const char *[]){
1893 "config_noc_clk_src",
1894 },
1895 .num_parents = 1,
1896 .ops = &clk_branch2_ops,
1897 },
1898 },
1899};
1900
1901static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1902 .halt_reg = 0x0284,
1903 .clkr = {
1904 .enable_reg = 0x0284,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_mss_q6_bimc_axi_clk",
1908 .flags = CLK_IS_ROOT,
1909 .ops = &clk_branch2_ops,
1910 },
1911 },
1912};
1913
1914static struct clk_branch gcc_pdm2_clk = {
1915 .halt_reg = 0x0ccc,
1916 .clkr = {
1917 .enable_reg = 0x0ccc,
1918 .enable_mask = BIT(0),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "gcc_pdm2_clk",
1921 .parent_names = (const char *[]){
1922 "pdm2_clk_src",
1923 },
1924 .num_parents = 1,
1925 .flags = CLK_SET_RATE_PARENT,
1926 .ops = &clk_branch2_ops,
1927 },
1928 },
1929};
1930
1931static struct clk_branch gcc_pdm_ahb_clk = {
1932 .halt_reg = 0x0cc4,
1933 .clkr = {
1934 .enable_reg = 0x0cc4,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_pdm_ahb_clk",
1938 .parent_names = (const char *[]){
1939 "periph_noc_clk_src",
1940 },
1941 .num_parents = 1,
1942 .ops = &clk_branch2_ops,
1943 },
1944 },
1945};
1946
1947static struct clk_branch gcc_prng_ahb_clk = {
1948 .halt_reg = 0x0d04,
1949 .halt_check = BRANCH_HALT_VOTED,
1950 .clkr = {
1951 .enable_reg = 0x1484,
1952 .enable_mask = BIT(13),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_prng_ahb_clk",
1955 .parent_names = (const char *[]){
1956 "periph_noc_clk_src",
1957 },
1958 .num_parents = 1,
1959 .ops = &clk_branch2_ops,
1960 },
1961 },
1962};
1963
1964static struct clk_branch gcc_sdcc1_ahb_clk = {
1965 .halt_reg = 0x04c8,
1966 .clkr = {
1967 .enable_reg = 0x04c8,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "gcc_sdcc1_ahb_clk",
1971 .parent_names = (const char *[]){
1972 "periph_noc_clk_src",
1973 },
1974 .num_parents = 1,
1975 .ops = &clk_branch2_ops,
1976 },
1977 },
1978};
1979
1980static struct clk_branch gcc_sdcc1_apps_clk = {
1981 .halt_reg = 0x04c4,
1982 .clkr = {
1983 .enable_reg = 0x04c4,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "gcc_sdcc1_apps_clk",
1987 .parent_names = (const char *[]){
1988 "sdcc1_apps_clk_src",
1989 },
1990 .num_parents = 1,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch gcc_sdcc2_ahb_clk = {
1998 .halt_reg = 0x0508,
1999 .clkr = {
2000 .enable_reg = 0x0508,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "gcc_sdcc2_ahb_clk",
2004 .parent_names = (const char *[]){
2005 "periph_noc_clk_src",
2006 },
2007 .num_parents = 1,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011};
2012
2013static struct clk_branch gcc_sdcc2_apps_clk = {
2014 .halt_reg = 0x0504,
2015 .clkr = {
2016 .enable_reg = 0x0504,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "gcc_sdcc2_apps_clk",
2020 .parent_names = (const char *[]){
2021 "sdcc2_apps_clk_src",
2022 },
2023 .num_parents = 1,
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2026 },
2027 },
2028};
2029
2030static struct clk_branch gcc_sdcc3_ahb_clk = {
2031 .halt_reg = 0x0548,
2032 .clkr = {
2033 .enable_reg = 0x0548,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gcc_sdcc3_ahb_clk",
2037 .parent_names = (const char *[]){
2038 "periph_noc_clk_src",
2039 },
2040 .num_parents = 1,
2041 .ops = &clk_branch2_ops,
2042 },
2043 },
2044};
2045
2046static struct clk_branch gcc_sdcc3_apps_clk = {
2047 .halt_reg = 0x0544,
2048 .clkr = {
2049 .enable_reg = 0x0544,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gcc_sdcc3_apps_clk",
2053 .parent_names = (const char *[]){
2054 "sdcc3_apps_clk_src",
2055 },
2056 .num_parents = 1,
2057 .flags = CLK_SET_RATE_PARENT,
2058 .ops = &clk_branch2_ops,
2059 },
2060 },
2061};
2062
2063static struct clk_branch gcc_sdcc4_ahb_clk = {
2064 .halt_reg = 0x0588,
2065 .clkr = {
2066 .enable_reg = 0x0588,
2067 .enable_mask = BIT(0),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "gcc_sdcc4_ahb_clk",
2070 .parent_names = (const char *[]){
2071 "periph_noc_clk_src",
2072 },
2073 .num_parents = 1,
2074 .ops = &clk_branch2_ops,
2075 },
2076 },
2077};
2078
2079static struct clk_branch gcc_sdcc4_apps_clk = {
2080 .halt_reg = 0x0584,
2081 .clkr = {
2082 .enable_reg = 0x0584,
2083 .enable_mask = BIT(0),
2084 .hw.init = &(struct clk_init_data){
2085 .name = "gcc_sdcc4_apps_clk",
2086 .parent_names = (const char *[]){
2087 "sdcc4_apps_clk_src",
2088 },
2089 .num_parents = 1,
2090 .flags = CLK_SET_RATE_PARENT,
2091 .ops = &clk_branch2_ops,
2092 },
2093 },
2094};
2095
2096static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2097 .halt_reg = 0x0108,
2098 .clkr = {
2099 .enable_reg = 0x0108,
2100 .enable_mask = BIT(0),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "gcc_sys_noc_usb3_axi_clk",
2103 .parent_names = (const char *[]){
2104 "usb30_master_clk_src",
2105 },
2106 .num_parents = 1,
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2109 },
2110 },
2111};
2112
2113static struct clk_branch gcc_tsif_ahb_clk = {
2114 .halt_reg = 0x0d84,
2115 .clkr = {
2116 .enable_reg = 0x0d84,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "gcc_tsif_ahb_clk",
2120 .parent_names = (const char *[]){
2121 "periph_noc_clk_src",
2122 },
2123 .num_parents = 1,
2124 .ops = &clk_branch2_ops,
2125 },
2126 },
2127};
2128
2129static struct clk_branch gcc_tsif_ref_clk = {
2130 .halt_reg = 0x0d88,
2131 .clkr = {
2132 .enable_reg = 0x0d88,
2133 .enable_mask = BIT(0),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_tsif_ref_clk",
2136 .parent_names = (const char *[]){
2137 "tsif_ref_clk_src",
2138 },
2139 .num_parents = 1,
2140 .flags = CLK_SET_RATE_PARENT,
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144};
2145
2146static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2147 .halt_reg = 0x04ac,
2148 .clkr = {
2149 .enable_reg = 0x04ac,
2150 .enable_mask = BIT(0),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_usb2a_phy_sleep_clk",
2153 .parent_names = (const char *[]){
2154 "sleep_clk_src",
2155 },
2156 .num_parents = 1,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160};
2161
2162static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2163 .halt_reg = 0x04b4,
2164 .clkr = {
2165 .enable_reg = 0x04b4,
2166 .enable_mask = BIT(0),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "gcc_usb2b_phy_sleep_clk",
2169 .parent_names = (const char *[]){
2170 "sleep_clk_src",
2171 },
2172 .num_parents = 1,
2173 .ops = &clk_branch2_ops,
2174 },
2175 },
2176};
2177
2178static struct clk_branch gcc_usb30_master_clk = {
2179 .halt_reg = 0x03c8,
2180 .clkr = {
2181 .enable_reg = 0x03c8,
2182 .enable_mask = BIT(0),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "gcc_usb30_master_clk",
2185 .parent_names = (const char *[]){
2186 "usb30_master_clk_src",
2187 },
2188 .num_parents = 1,
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2191 },
2192 },
2193};
2194
2195static struct clk_branch gcc_usb30_mock_utmi_clk = {
2196 .halt_reg = 0x03d0,
2197 .clkr = {
2198 .enable_reg = 0x03d0,
2199 .enable_mask = BIT(0),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "gcc_usb30_mock_utmi_clk",
2202 .parent_names = (const char *[]){
2203 "usb30_mock_utmi_clk_src",
2204 },
2205 .num_parents = 1,
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2208 },
2209 },
2210};
2211
2212static struct clk_branch gcc_usb30_sleep_clk = {
2213 .halt_reg = 0x03cc,
2214 .clkr = {
2215 .enable_reg = 0x03cc,
2216 .enable_mask = BIT(0),
2217 .hw.init = &(struct clk_init_data){
2218 .name = "gcc_usb30_sleep_clk",
2219 .parent_names = (const char *[]){
2220 "sleep_clk_src",
2221 },
2222 .num_parents = 1,
2223 .ops = &clk_branch2_ops,
2224 },
2225 },
2226};
2227
2228static struct clk_branch gcc_usb_hs_ahb_clk = {
2229 .halt_reg = 0x0488,
2230 .clkr = {
2231 .enable_reg = 0x0488,
2232 .enable_mask = BIT(0),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "gcc_usb_hs_ahb_clk",
2235 .parent_names = (const char *[]){
2236 "periph_noc_clk_src",
2237 },
2238 .num_parents = 1,
2239 .ops = &clk_branch2_ops,
2240 },
2241 },
2242};
2243
2244static struct clk_branch gcc_usb_hs_system_clk = {
2245 .halt_reg = 0x0484,
2246 .clkr = {
2247 .enable_reg = 0x0484,
2248 .enable_mask = BIT(0),
2249 .hw.init = &(struct clk_init_data){
2250 .name = "gcc_usb_hs_system_clk",
2251 .parent_names = (const char *[]){
2252 "usb_hs_system_clk_src",
2253 },
2254 .num_parents = 1,
2255 .flags = CLK_SET_RATE_PARENT,
2256 .ops = &clk_branch2_ops,
2257 },
2258 },
2259};
2260
2261static struct clk_branch gcc_usb_hsic_ahb_clk = {
2262 .halt_reg = 0x0408,
2263 .clkr = {
2264 .enable_reg = 0x0408,
2265 .enable_mask = BIT(0),
2266 .hw.init = &(struct clk_init_data){
2267 .name = "gcc_usb_hsic_ahb_clk",
2268 .parent_names = (const char *[]){
2269 "periph_noc_clk_src",
2270 },
2271 .num_parents = 1,
2272 .ops = &clk_branch2_ops,
2273 },
2274 },
2275};
2276
2277static struct clk_branch gcc_usb_hsic_clk = {
2278 .halt_reg = 0x0410,
2279 .clkr = {
2280 .enable_reg = 0x0410,
2281 .enable_mask = BIT(0),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gcc_usb_hsic_clk",
2284 .parent_names = (const char *[]){
2285 "usb_hsic_clk_src",
2286 },
2287 .num_parents = 1,
2288 .flags = CLK_SET_RATE_PARENT,
2289 .ops = &clk_branch2_ops,
2290 },
2291 },
2292};
2293
2294static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2295 .halt_reg = 0x0414,
2296 .clkr = {
2297 .enable_reg = 0x0414,
2298 .enable_mask = BIT(0),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_usb_hsic_io_cal_clk",
2301 .parent_names = (const char *[]){
2302 "usb_hsic_io_cal_clk_src",
2303 },
2304 .num_parents = 1,
2305 .flags = CLK_SET_RATE_PARENT,
2306 .ops = &clk_branch2_ops,
2307 },
2308 },
2309};
2310
2311static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2312 .halt_reg = 0x0418,
2313 .clkr = {
2314 .enable_reg = 0x0418,
2315 .enable_mask = BIT(0),
2316 .hw.init = &(struct clk_init_data){
2317 .name = "gcc_usb_hsic_io_cal_sleep_clk",
2318 .parent_names = (const char *[]){
2319 "sleep_clk_src",
2320 },
2321 .num_parents = 1,
2322 .ops = &clk_branch2_ops,
2323 },
2324 },
2325};
2326
2327static struct clk_branch gcc_usb_hsic_system_clk = {
2328 .halt_reg = 0x040c,
2329 .clkr = {
2330 .enable_reg = 0x040c,
2331 .enable_mask = BIT(0),
2332 .hw.init = &(struct clk_init_data){
2333 .name = "gcc_usb_hsic_system_clk",
2334 .parent_names = (const char *[]){
2335 "usb_hsic_system_clk_src",
2336 },
2337 .num_parents = 1,
2338 .flags = CLK_SET_RATE_PARENT,
2339 .ops = &clk_branch2_ops,
2340 },
2341 },
2342};
2343
2344static struct clk_regmap *gcc_msm8974_clocks[] = {
2345 [GPLL0] = &gpll0.clkr,
2346 [GPLL0_VOTE] = &gpll0_vote,
2347 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2348 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2349 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2350 [GPLL1] = &gpll1.clkr,
2351 [GPLL1_VOTE] = &gpll1_vote,
2352 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2353 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2354 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2355 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2356 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2357 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2358 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2359 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2360 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2361 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2362 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2363 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2364 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2365 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2366 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2367 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2368 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2369 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2370 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2371 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2372 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2373 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2374 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2375 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2376 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2377 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2378 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2379 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2380 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2381 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2382 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2383 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2384 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2385 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2386 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2387 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2388 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2389 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2390 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2391 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2392 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2393 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2394 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2395 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2396 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2397 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2398 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2399 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2400 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2401 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2402 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2403 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2404 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2405 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2406 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2407 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2408 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2409 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2410 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2411 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2412 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2413 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2414 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2415 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2416 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2417 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2418 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2419 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2420 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2421 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2422 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2423 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2424 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2425 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2426 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2427 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2428 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2429 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2430 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2431 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2432 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2433 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2434 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2435 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2436 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2437 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2438 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2439 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2440 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2441 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2442 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2443 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2444 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2445 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2446 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2447 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2448 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2449 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2450 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2451 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2452 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2453 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2454 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2455 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2456 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2457 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2458 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2459 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2460 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2461 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2462 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2463 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2464 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2465 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2466 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2467 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2468 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2469 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2470 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2471 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2472 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2473 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2474 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2475 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2476 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2477 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2478 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2479 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2480 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2481 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2482 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2483 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2484 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2485 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
2486};
2487
2488static const struct qcom_reset_map gcc_msm8974_resets[] = {
2489 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2490 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2491 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2492 [GCC_IMEM_BCR] = { 0x0200 },
2493 [GCC_MMSS_BCR] = { 0x0240 },
2494 [GCC_QDSS_BCR] = { 0x0300 },
2495 [GCC_USB_30_BCR] = { 0x03c0 },
2496 [GCC_USB3_PHY_BCR] = { 0x03fc },
2497 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2498 [GCC_USB_HS_BCR] = { 0x0480 },
2499 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2500 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2501 [GCC_SDCC1_BCR] = { 0x04c0 },
2502 [GCC_SDCC2_BCR] = { 0x0500 },
2503 [GCC_SDCC3_BCR] = { 0x0540 },
2504 [GCC_SDCC4_BCR] = { 0x0580 },
2505 [GCC_BLSP1_BCR] = { 0x05c0 },
2506 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2507 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2508 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2509 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2510 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2511 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2512 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2513 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2514 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2515 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2516 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2517 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2518 [GCC_BLSP2_BCR] = { 0x0940 },
2519 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2520 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2521 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2522 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2523 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2524 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2525 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2526 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2527 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2528 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2529 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2530 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2531 [GCC_PDM_BCR] = { 0x0cc0 },
2532 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2533 [GCC_TSIF_BCR] = { 0x0d80 },
2534 [GCC_TCSR_BCR] = { 0x0dc0 },
2535 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2536 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2537 [GCC_TLMM_BCR] = { 0x0e80 },
2538 [GCC_MPM_BCR] = { 0x0ec0 },
2539 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2540 [GCC_SPMI_BCR] = { 0x0fc0 },
2541 [GCC_SPDM_BCR] = { 0x1000 },
2542 [GCC_CE1_BCR] = { 0x1040 },
2543 [GCC_CE2_BCR] = { 0x1080 },
2544 [GCC_BIMC_BCR] = { 0x1100 },
2545 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2546 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2547 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2548 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2549 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2550 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2551 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2552 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2553 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2554 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2555 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2556 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2557 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2558 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2559 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2560 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2561 [GCC_DEHR_BCR] = { 0x1300 },
2562 [GCC_RBCPR_BCR] = { 0x1380 },
2563 [GCC_MSS_RESTART] = { 0x1680 },
2564 [GCC_LPASS_RESTART] = { 0x16c0 },
2565 [GCC_WCSS_RESTART] = { 0x1700 },
2566 [GCC_VENUS_RESTART] = { 0x1740 },
2567};
2568
2569static const struct regmap_config gcc_msm8974_regmap_config = {
2570 .reg_bits = 32,
2571 .reg_stride = 4,
2572 .val_bits = 32,
2573 .max_register = 0x1fc0,
2574 .fast_io = true,
2575};
2576
2577static const struct of_device_id gcc_msm8974_match_table[] = {
2578 { .compatible = "qcom,gcc-msm8974" },
2579 { }
2580};
2581MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2582
2583struct qcom_cc {
2584 struct qcom_reset_controller reset;
2585 struct clk_onecell_data data;
2586 struct clk *clks[];
2587};
2588
2589static int gcc_msm8974_probe(struct platform_device *pdev)
2590{
2591 void __iomem *base;
2592 struct resource *res;
2593 int i, ret;
2594 struct device *dev = &pdev->dev;
2595 struct clk *clk;
2596 struct clk_onecell_data *data;
2597 struct clk **clks;
2598 struct regmap *regmap;
2599 size_t num_clks;
2600 struct qcom_reset_controller *reset;
2601 struct qcom_cc *cc;
2602
2603 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2604 base = devm_ioremap_resource(dev, res);
2605 if (IS_ERR(base))
2606 return PTR_ERR(base);
2607
2608 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8974_regmap_config);
2609 if (IS_ERR(regmap))
2610 return PTR_ERR(regmap);
2611
2612 num_clks = ARRAY_SIZE(gcc_msm8974_clocks);
2613 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2614 GFP_KERNEL);
2615 if (!cc)
2616 return -ENOMEM;
2617
2618 clks = cc->clks;
2619 data = &cc->data;
2620 data->clks = clks;
2621 data->clk_num = num_clks;
2622
2623 /* Temporary until RPM clocks supported */
2624 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2625 if (IS_ERR(clk))
2626 return PTR_ERR(clk);
2627
2628 /* Should move to DT node? */
2629 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2630 CLK_IS_ROOT, 32768);
2631 if (IS_ERR(clk))
2632 return PTR_ERR(clk);
2633
2634 for (i = 0; i < num_clks; i++) {
2635 if (!gcc_msm8974_clocks[i])
2636 continue;
2637 clk = devm_clk_register_regmap(dev, gcc_msm8974_clocks[i]);
2638 if (IS_ERR(clk))
2639 return PTR_ERR(clk);
2640 clks[i] = clk;
2641 }
2642
2643 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2644 if (ret)
2645 return ret;
2646
2647 reset = &cc->reset;
2648 reset->rcdev.of_node = dev->of_node;
2649 reset->rcdev.ops = &qcom_reset_ops,
2650 reset->rcdev.owner = THIS_MODULE,
2651 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8974_resets),
2652 reset->regmap = regmap;
2653 reset->reset_map = gcc_msm8974_resets,
2654 platform_set_drvdata(pdev, &reset->rcdev);
2655
2656 ret = reset_controller_register(&reset->rcdev);
2657 if (ret)
2658 of_clk_del_provider(dev->of_node);
2659
2660 return ret;
2661}
2662
2663static int gcc_msm8974_remove(struct platform_device *pdev)
2664{
2665 of_clk_del_provider(pdev->dev.of_node);
2666 reset_controller_unregister(platform_get_drvdata(pdev));
2667 return 0;
2668}
2669
2670static struct platform_driver gcc_msm8974_driver = {
2671 .probe = gcc_msm8974_probe,
2672 .remove = gcc_msm8974_remove,
2673 .driver = {
2674 .name = "gcc-msm8974",
2675 .owner = THIS_MODULE,
2676 .of_match_table = gcc_msm8974_match_table,
2677 },
2678};
2679
2680static int __init gcc_msm8974_init(void)
2681{
2682 return platform_driver_register(&gcc_msm8974_driver);
2683}
2684core_initcall(gcc_msm8974_init);
2685
2686static void __exit gcc_msm8974_exit(void)
2687{
2688 platform_driver_unregister(&gcc_msm8974_driver);
2689}
2690module_exit(gcc_msm8974_exit);
2691
2692MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2693MODULE_LICENSE("GPL v2");
2694MODULE_ALIAS("platform:gcc-msm8974");
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
new file mode 100644
index 000000000000..f9b59c7e48e9
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -0,0 +1,2321 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/clk-provider.h>
23#include <linux/regmap.h>
24#include <linux/reset-controller.h>
25
26#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27#include <dt-bindings/reset/qcom,mmcc-msm8960.h>
28
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35#define P_PXO 0
36#define P_PLL8 1
37#define P_PLL2 2
38#define P_PLL3 3
39
40static u8 mmcc_pxo_pll8_pll2_map[] = {
41 [P_PXO] = 0,
42 [P_PLL8] = 2,
43 [P_PLL2] = 1,
44};
45
46static const char *mmcc_pxo_pll8_pll2[] = {
47 "pxo",
48 "pll8_vote",
49 "pll2",
50};
51
52static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
53 [P_PXO] = 0,
54 [P_PLL8] = 2,
55 [P_PLL2] = 1,
56 [P_PLL3] = 3,
57};
58
59static const char *mmcc_pxo_pll8_pll2_pll3[] = {
60 "pxo",
61 "pll2",
62 "pll8_vote",
63 "pll3",
64};
65
66static struct clk_pll pll2 = {
67 .l_reg = 0x320,
68 .m_reg = 0x324,
69 .n_reg = 0x328,
70 .config_reg = 0x32c,
71 .mode_reg = 0x31c,
72 .status_reg = 0x334,
73 .status_bit = 16,
74 .clkr.hw.init = &(struct clk_init_data){
75 .name = "pll2",
76 .parent_names = (const char *[]){ "pxo" },
77 .num_parents = 1,
78 .ops = &clk_pll_ops,
79 },
80};
81
82static struct freq_tbl clk_tbl_cam[] = {
83 { 6000000, P_PLL8, 4, 1, 16 },
84 { 8000000, P_PLL8, 4, 1, 12 },
85 { 12000000, P_PLL8, 4, 1, 8 },
86 { 16000000, P_PLL8, 4, 1, 6 },
87 { 19200000, P_PLL8, 4, 1, 5 },
88 { 24000000, P_PLL8, 4, 1, 4 },
89 { 32000000, P_PLL8, 4, 1, 3 },
90 { 48000000, P_PLL8, 4, 1, 2 },
91 { 64000000, P_PLL8, 3, 1, 2 },
92 { 96000000, P_PLL8, 4, 0, 0 },
93 { 128000000, P_PLL8, 3, 0, 0 },
94 { }
95};
96
97static struct clk_rcg camclk0_src = {
98 .ns_reg = 0x0148,
99 .md_reg = 0x0144,
100 .mn = {
101 .mnctr_en_bit = 5,
102 .mnctr_reset_bit = 8,
103 .reset_in_cc = true,
104 .mnctr_mode_shift = 6,
105 .n_val_shift = 24,
106 .m_val_shift = 8,
107 .width = 8,
108 },
109 .p = {
110 .pre_div_shift = 14,
111 .pre_div_width = 2,
112 },
113 .s = {
114 .src_sel_shift = 0,
115 .parent_map = mmcc_pxo_pll8_pll2_map,
116 },
117 .freq_tbl = clk_tbl_cam,
118 .clkr = {
119 .enable_reg = 0x0140,
120 .enable_mask = BIT(2),
121 .hw.init = &(struct clk_init_data){
122 .name = "camclk0_src",
123 .parent_names = mmcc_pxo_pll8_pll2,
124 .num_parents = 3,
125 .ops = &clk_rcg_ops,
126 },
127 },
128};
129
130static struct clk_branch camclk0_clk = {
131 .halt_reg = 0x01e8,
132 .halt_bit = 15,
133 .clkr = {
134 .enable_reg = 0x0140,
135 .enable_mask = BIT(0),
136 .hw.init = &(struct clk_init_data){
137 .name = "camclk0_clk",
138 .parent_names = (const char *[]){ "camclk0_src" },
139 .num_parents = 1,
140 .ops = &clk_branch_ops,
141 },
142 },
143
144};
145
146static struct clk_rcg camclk1_src = {
147 .ns_reg = 0x015c,
148 .md_reg = 0x0158,
149 .mn = {
150 .mnctr_en_bit = 5,
151 .mnctr_reset_bit = 8,
152 .reset_in_cc = true,
153 .mnctr_mode_shift = 6,
154 .n_val_shift = 24,
155 .m_val_shift = 8,
156 .width = 8,
157 },
158 .p = {
159 .pre_div_shift = 14,
160 .pre_div_width = 2,
161 },
162 .s = {
163 .src_sel_shift = 0,
164 .parent_map = mmcc_pxo_pll8_pll2_map,
165 },
166 .freq_tbl = clk_tbl_cam,
167 .clkr = {
168 .enable_reg = 0x0154,
169 .enable_mask = BIT(2),
170 .hw.init = &(struct clk_init_data){
171 .name = "camclk1_src",
172 .parent_names = mmcc_pxo_pll8_pll2,
173 .num_parents = 3,
174 .ops = &clk_rcg_ops,
175 },
176 },
177};
178
179static struct clk_branch camclk1_clk = {
180 .halt_reg = 0x01e8,
181 .halt_bit = 16,
182 .clkr = {
183 .enable_reg = 0x0154,
184 .enable_mask = BIT(0),
185 .hw.init = &(struct clk_init_data){
186 .name = "camclk1_clk",
187 .parent_names = (const char *[]){ "camclk1_src" },
188 .num_parents = 1,
189 .ops = &clk_branch_ops,
190 },
191 },
192
193};
194
195static struct clk_rcg camclk2_src = {
196 .ns_reg = 0x0228,
197 .md_reg = 0x0224,
198 .mn = {
199 .mnctr_en_bit = 5,
200 .mnctr_reset_bit = 8,
201 .reset_in_cc = true,
202 .mnctr_mode_shift = 6,
203 .n_val_shift = 24,
204 .m_val_shift = 8,
205 .width = 8,
206 },
207 .p = {
208 .pre_div_shift = 14,
209 .pre_div_width = 2,
210 },
211 .s = {
212 .src_sel_shift = 0,
213 .parent_map = mmcc_pxo_pll8_pll2_map,
214 },
215 .freq_tbl = clk_tbl_cam,
216 .clkr = {
217 .enable_reg = 0x0220,
218 .enable_mask = BIT(2),
219 .hw.init = &(struct clk_init_data){
220 .name = "camclk2_src",
221 .parent_names = mmcc_pxo_pll8_pll2,
222 .num_parents = 3,
223 .ops = &clk_rcg_ops,
224 },
225 },
226};
227
228static struct clk_branch camclk2_clk = {
229 .halt_reg = 0x01e8,
230 .halt_bit = 16,
231 .clkr = {
232 .enable_reg = 0x0220,
233 .enable_mask = BIT(0),
234 .hw.init = &(struct clk_init_data){
235 .name = "camclk2_clk",
236 .parent_names = (const char *[]){ "camclk2_src" },
237 .num_parents = 1,
238 .ops = &clk_branch_ops,
239 },
240 },
241
242};
243
244static struct freq_tbl clk_tbl_csi[] = {
245 { 27000000, P_PXO, 1, 0, 0 },
246 { 85330000, P_PLL8, 1, 2, 9 },
247 { 177780000, P_PLL2, 1, 2, 9 },
248 { }
249};
250
251static struct clk_rcg csi0_src = {
252 .ns_reg = 0x0048,
253 .md_reg = 0x0044,
254 .mn = {
255 .mnctr_en_bit = 5,
256 .mnctr_reset_bit = 7,
257 .mnctr_mode_shift = 6,
258 .n_val_shift = 24,
259 .m_val_shift = 8,
260 .width = 8,
261 },
262 .p = {
263 .pre_div_shift = 14,
264 .pre_div_width = 2,
265 },
266 .s = {
267 .src_sel_shift = 0,
268 .parent_map = mmcc_pxo_pll8_pll2_map,
269 },
270 .freq_tbl = clk_tbl_csi,
271 .clkr = {
272 .enable_reg = 0x0040,
273 .enable_mask = BIT(2),
274 .hw.init = &(struct clk_init_data){
275 .name = "csi0_src",
276 .parent_names = mmcc_pxo_pll8_pll2,
277 .num_parents = 3,
278 .ops = &clk_rcg_ops,
279 },
280 },
281};
282
283static struct clk_branch csi0_clk = {
284 .halt_reg = 0x01cc,
285 .halt_bit = 13,
286 .clkr = {
287 .enable_reg = 0x0040,
288 .enable_mask = BIT(0),
289 .hw.init = &(struct clk_init_data){
290 .parent_names = (const char *[]){ "csi0_src" },
291 .num_parents = 1,
292 .name = "csi0_clk",
293 .ops = &clk_branch_ops,
294 .flags = CLK_SET_RATE_PARENT,
295 },
296 },
297};
298
299static struct clk_branch csi0_phy_clk = {
300 .halt_reg = 0x01e8,
301 .halt_bit = 9,
302 .clkr = {
303 .enable_reg = 0x0040,
304 .enable_mask = BIT(8),
305 .hw.init = &(struct clk_init_data){
306 .parent_names = (const char *[]){ "csi0_src" },
307 .num_parents = 1,
308 .name = "csi0_phy_clk",
309 .ops = &clk_branch_ops,
310 .flags = CLK_SET_RATE_PARENT,
311 },
312 },
313};
314
315static struct clk_rcg csi1_src = {
316 .ns_reg = 0x0010,
317 .md_reg = 0x0028,
318 .mn = {
319 .mnctr_en_bit = 5,
320 .mnctr_reset_bit = 7,
321 .mnctr_mode_shift = 6,
322 .n_val_shift = 24,
323 .m_val_shift = 8,
324 .width = 8,
325 },
326 .p = {
327 .pre_div_shift = 14,
328 .pre_div_width = 2,
329 },
330 .s = {
331 .src_sel_shift = 0,
332 .parent_map = mmcc_pxo_pll8_pll2_map,
333 },
334 .freq_tbl = clk_tbl_csi,
335 .clkr = {
336 .enable_reg = 0x0024,
337 .enable_mask = BIT(2),
338 .hw.init = &(struct clk_init_data){
339 .name = "csi1_src",
340 .parent_names = mmcc_pxo_pll8_pll2,
341 .num_parents = 3,
342 .ops = &clk_rcg_ops,
343 },
344 },
345};
346
347static struct clk_branch csi1_clk = {
348 .halt_reg = 0x01cc,
349 .halt_bit = 14,
350 .clkr = {
351 .enable_reg = 0x0024,
352 .enable_mask = BIT(0),
353 .hw.init = &(struct clk_init_data){
354 .parent_names = (const char *[]){ "csi1_src" },
355 .num_parents = 1,
356 .name = "csi1_clk",
357 .ops = &clk_branch_ops,
358 .flags = CLK_SET_RATE_PARENT,
359 },
360 },
361};
362
363static struct clk_branch csi1_phy_clk = {
364 .halt_reg = 0x01e8,
365 .halt_bit = 10,
366 .clkr = {
367 .enable_reg = 0x0024,
368 .enable_mask = BIT(8),
369 .hw.init = &(struct clk_init_data){
370 .parent_names = (const char *[]){ "csi1_src" },
371 .num_parents = 1,
372 .name = "csi1_phy_clk",
373 .ops = &clk_branch_ops,
374 .flags = CLK_SET_RATE_PARENT,
375 },
376 },
377};
378
379static struct clk_rcg csi2_src = {
380 .ns_reg = 0x0234,
381 .md_reg = 0x022c,
382 .mn = {
383 .mnctr_en_bit = 5,
384 .mnctr_reset_bit = 7,
385 .mnctr_mode_shift = 6,
386 .n_val_shift = 24,
387 .m_val_shift = 8,
388 .width = 8,
389 },
390 .p = {
391 .pre_div_shift = 14,
392 .pre_div_width = 2,
393 },
394 .s = {
395 .src_sel_shift = 0,
396 .parent_map = mmcc_pxo_pll8_pll2_map,
397 },
398 .freq_tbl = clk_tbl_csi,
399 .clkr = {
400 .enable_reg = 0x022c,
401 .enable_mask = BIT(2),
402 .hw.init = &(struct clk_init_data){
403 .name = "csi2_src",
404 .parent_names = mmcc_pxo_pll8_pll2,
405 .num_parents = 3,
406 .ops = &clk_rcg_ops,
407 },
408 },
409};
410
411static struct clk_branch csi2_clk = {
412 .halt_reg = 0x01cc,
413 .halt_bit = 29,
414 .clkr = {
415 .enable_reg = 0x022c,
416 .enable_mask = BIT(0),
417 .hw.init = &(struct clk_init_data){
418 .parent_names = (const char *[]){ "csi2_src" },
419 .num_parents = 1,
420 .name = "csi2_clk",
421 .ops = &clk_branch_ops,
422 .flags = CLK_SET_RATE_PARENT,
423 },
424 },
425};
426
427static struct clk_branch csi2_phy_clk = {
428 .halt_reg = 0x01e8,
429 .halt_bit = 29,
430 .clkr = {
431 .enable_reg = 0x022c,
432 .enable_mask = BIT(8),
433 .hw.init = &(struct clk_init_data){
434 .parent_names = (const char *[]){ "csi2_src" },
435 .num_parents = 1,
436 .name = "csi2_phy_clk",
437 .ops = &clk_branch_ops,
438 .flags = CLK_SET_RATE_PARENT,
439 },
440 },
441};
442
443struct clk_pix_rdi {
444 u32 s_reg;
445 u32 s_mask;
446 u32 s2_reg;
447 u32 s2_mask;
448 struct clk_regmap clkr;
449};
450
451#define to_clk_pix_rdi(_hw) \
452 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
453
454static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
455{
456 int i;
457 int ret = 0;
458 u32 val;
459 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
460 struct clk *clk = hw->clk;
461 int num_parents = __clk_get_num_parents(hw->clk);
462
463 /*
464 * These clocks select three inputs via two muxes. One mux selects
465 * between csi0 and csi1 and the second mux selects between that mux's
466 * output and csi2. The source and destination selections for each
467 * mux must be clocking for the switch to succeed so just turn on
468 * all three sources because it's easier than figuring out what source
469 * needs to be on at what time.
470 */
471 for (i = 0; i < num_parents; i++) {
472 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
473 if (ret)
474 goto err;
475 }
476
477 if (index == 2)
478 val = rdi->s2_mask;
479 else
480 val = 0;
481 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
482 /*
483 * Wait at least 6 cycles of slowest clock
484 * for the glitch-free MUX to fully switch sources.
485 */
486 udelay(1);
487
488 if (index == 1)
489 val = rdi->s_mask;
490 else
491 val = 0;
492 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
493 /*
494 * Wait at least 6 cycles of slowest clock
495 * for the glitch-free MUX to fully switch sources.
496 */
497 udelay(1);
498
499err:
500 for (i--; i >= 0; i--)
501 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
502
503 return ret;
504}
505
506static u8 pix_rdi_get_parent(struct clk_hw *hw)
507{
508 u32 val;
509 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
510
511
512 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
513 if (val & rdi->s2_mask)
514 return 2;
515
516 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
517 if (val & rdi->s_mask)
518 return 1;
519
520 return 0;
521}
522
523static const struct clk_ops clk_ops_pix_rdi = {
524 .enable = clk_enable_regmap,
525 .disable = clk_disable_regmap,
526 .set_parent = pix_rdi_set_parent,
527 .get_parent = pix_rdi_get_parent,
528 .determine_rate = __clk_mux_determine_rate,
529};
530
531static const char *pix_rdi_parents[] = {
532 "csi0_clk",
533 "csi1_clk",
534 "csi2_clk",
535};
536
537static struct clk_pix_rdi csi_pix_clk = {
538 .s_reg = 0x0058,
539 .s_mask = BIT(25),
540 .s2_reg = 0x0238,
541 .s2_mask = BIT(13),
542 .clkr = {
543 .enable_reg = 0x0058,
544 .enable_mask = BIT(26),
545 .hw.init = &(struct clk_init_data){
546 .name = "csi_pix_clk",
547 .parent_names = pix_rdi_parents,
548 .num_parents = 3,
549 .ops = &clk_ops_pix_rdi,
550 },
551 },
552};
553
554static struct clk_pix_rdi csi_pix1_clk = {
555 .s_reg = 0x0238,
556 .s_mask = BIT(8),
557 .s2_reg = 0x0238,
558 .s2_mask = BIT(9),
559 .clkr = {
560 .enable_reg = 0x0238,
561 .enable_mask = BIT(10),
562 .hw.init = &(struct clk_init_data){
563 .name = "csi_pix1_clk",
564 .parent_names = pix_rdi_parents,
565 .num_parents = 3,
566 .ops = &clk_ops_pix_rdi,
567 },
568 },
569};
570
571static struct clk_pix_rdi csi_rdi_clk = {
572 .s_reg = 0x0058,
573 .s_mask = BIT(12),
574 .s2_reg = 0x0238,
575 .s2_mask = BIT(12),
576 .clkr = {
577 .enable_reg = 0x0058,
578 .enable_mask = BIT(13),
579 .hw.init = &(struct clk_init_data){
580 .name = "csi_rdi_clk",
581 .parent_names = pix_rdi_parents,
582 .num_parents = 3,
583 .ops = &clk_ops_pix_rdi,
584 },
585 },
586};
587
588static struct clk_pix_rdi csi_rdi1_clk = {
589 .s_reg = 0x0238,
590 .s_mask = BIT(0),
591 .s2_reg = 0x0238,
592 .s2_mask = BIT(1),
593 .clkr = {
594 .enable_reg = 0x0238,
595 .enable_mask = BIT(2),
596 .hw.init = &(struct clk_init_data){
597 .name = "csi_rdi1_clk",
598 .parent_names = pix_rdi_parents,
599 .num_parents = 3,
600 .ops = &clk_ops_pix_rdi,
601 },
602 },
603};
604
605static struct clk_pix_rdi csi_rdi2_clk = {
606 .s_reg = 0x0238,
607 .s_mask = BIT(4),
608 .s2_reg = 0x0238,
609 .s2_mask = BIT(5),
610 .clkr = {
611 .enable_reg = 0x0238,
612 .enable_mask = BIT(6),
613 .hw.init = &(struct clk_init_data){
614 .name = "csi_rdi2_clk",
615 .parent_names = pix_rdi_parents,
616 .num_parents = 3,
617 .ops = &clk_ops_pix_rdi,
618 },
619 },
620};
621
622static struct freq_tbl clk_tbl_csiphytimer[] = {
623 { 85330000, P_PLL8, 1, 2, 9 },
624 { 177780000, P_PLL2, 1, 2, 9 },
625 { }
626};
627
628static struct clk_rcg csiphytimer_src = {
629 .ns_reg = 0x0168,
630 .md_reg = 0x0164,
631 .mn = {
632 .mnctr_en_bit = 5,
633 .mnctr_reset_bit = 8,
634 .reset_in_cc = true,
635 .mnctr_mode_shift = 6,
636 .n_val_shift = 24,
637 .m_val_shift = 8,
638 .width = 8,
639 },
640 .p = {
641 .pre_div_shift = 14,
642 .pre_div_width = 2,
643 },
644 .s = {
645 .src_sel_shift = 0,
646 .parent_map = mmcc_pxo_pll8_pll2_map,
647 },
648 .freq_tbl = clk_tbl_csiphytimer,
649 .clkr = {
650 .enable_reg = 0x0160,
651 .enable_mask = BIT(2),
652 .hw.init = &(struct clk_init_data){
653 .name = "csiphytimer_src",
654 .parent_names = mmcc_pxo_pll8_pll2,
655 .num_parents = 3,
656 .ops = &clk_rcg_ops,
657 },
658 },
659};
660
661static const char *csixphy_timer_src[] = { "csiphytimer_src" };
662
663static struct clk_branch csiphy0_timer_clk = {
664 .halt_reg = 0x01e8,
665 .halt_bit = 17,
666 .clkr = {
667 .enable_reg = 0x0160,
668 .enable_mask = BIT(0),
669 .hw.init = &(struct clk_init_data){
670 .parent_names = csixphy_timer_src,
671 .num_parents = 1,
672 .name = "csiphy0_timer_clk",
673 .ops = &clk_branch_ops,
674 .flags = CLK_SET_RATE_PARENT,
675 },
676 },
677};
678
679static struct clk_branch csiphy1_timer_clk = {
680 .halt_reg = 0x01e8,
681 .halt_bit = 18,
682 .clkr = {
683 .enable_reg = 0x0160,
684 .enable_mask = BIT(9),
685 .hw.init = &(struct clk_init_data){
686 .parent_names = csixphy_timer_src,
687 .num_parents = 1,
688 .name = "csiphy1_timer_clk",
689 .ops = &clk_branch_ops,
690 .flags = CLK_SET_RATE_PARENT,
691 },
692 },
693};
694
695static struct clk_branch csiphy2_timer_clk = {
696 .halt_reg = 0x01e8,
697 .halt_bit = 30,
698 .clkr = {
699 .enable_reg = 0x0160,
700 .enable_mask = BIT(11),
701 .hw.init = &(struct clk_init_data){
702 .parent_names = csixphy_timer_src,
703 .num_parents = 1,
704 .name = "csiphy2_timer_clk",
705 .ops = &clk_branch_ops,
706 .flags = CLK_SET_RATE_PARENT,
707 },
708 },
709};
710
711static struct freq_tbl clk_tbl_gfx2d[] = {
712 { 27000000, P_PXO, 1, 0 },
713 { 48000000, P_PLL8, 1, 8 },
714 { 54857000, P_PLL8, 1, 7 },
715 { 64000000, P_PLL8, 1, 6 },
716 { 76800000, P_PLL8, 1, 5 },
717 { 96000000, P_PLL8, 1, 4 },
718 { 128000000, P_PLL8, 1, 3 },
719 { 145455000, P_PLL2, 2, 11 },
720 { 160000000, P_PLL2, 1, 5 },
721 { 177778000, P_PLL2, 2, 9 },
722 { 200000000, P_PLL2, 1, 4 },
723 { 228571000, P_PLL2, 2, 7 },
724 { }
725};
726
727static struct clk_dyn_rcg gfx2d0_src = {
728 .ns_reg = 0x0070,
729 .md_reg[0] = 0x0064,
730 .md_reg[1] = 0x0068,
731 .mn[0] = {
732 .mnctr_en_bit = 8,
733 .mnctr_reset_bit = 25,
734 .mnctr_mode_shift = 9,
735 .n_val_shift = 20,
736 .m_val_shift = 4,
737 .width = 4,
738 },
739 .mn[1] = {
740 .mnctr_en_bit = 5,
741 .mnctr_reset_bit = 24,
742 .mnctr_mode_shift = 6,
743 .n_val_shift = 16,
744 .m_val_shift = 4,
745 .width = 4,
746 },
747 .s[0] = {
748 .src_sel_shift = 3,
749 .parent_map = mmcc_pxo_pll8_pll2_map,
750 },
751 .s[1] = {
752 .src_sel_shift = 0,
753 .parent_map = mmcc_pxo_pll8_pll2_map,
754 },
755 .mux_sel_bit = 11,
756 .freq_tbl = clk_tbl_gfx2d,
757 .clkr = {
758 .enable_reg = 0x0060,
759 .enable_mask = BIT(2),
760 .hw.init = &(struct clk_init_data){
761 .name = "gfx2d0_src",
762 .parent_names = mmcc_pxo_pll8_pll2,
763 .num_parents = 3,
764 .ops = &clk_dyn_rcg_ops,
765 },
766 },
767};
768
769static struct clk_branch gfx2d0_clk = {
770 .halt_reg = 0x01c8,
771 .halt_bit = 9,
772 .clkr = {
773 .enable_reg = 0x0060,
774 .enable_mask = BIT(0),
775 .hw.init = &(struct clk_init_data){
776 .name = "gfx2d0_clk",
777 .parent_names = (const char *[]){ "gfx2d0_src" },
778 .num_parents = 1,
779 .ops = &clk_branch_ops,
780 .flags = CLK_SET_RATE_PARENT,
781 },
782 },
783};
784
785static struct clk_dyn_rcg gfx2d1_src = {
786 .ns_reg = 0x007c,
787 .md_reg[0] = 0x0078,
788 .md_reg[1] = 0x006c,
789 .mn[0] = {
790 .mnctr_en_bit = 8,
791 .mnctr_reset_bit = 25,
792 .mnctr_mode_shift = 9,
793 .n_val_shift = 20,
794 .m_val_shift = 4,
795 .width = 4,
796 },
797 .mn[1] = {
798 .mnctr_en_bit = 5,
799 .mnctr_reset_bit = 24,
800 .mnctr_mode_shift = 6,
801 .n_val_shift = 16,
802 .m_val_shift = 4,
803 .width = 4,
804 },
805 .s[0] = {
806 .src_sel_shift = 3,
807 .parent_map = mmcc_pxo_pll8_pll2_map,
808 },
809 .s[1] = {
810 .src_sel_shift = 0,
811 .parent_map = mmcc_pxo_pll8_pll2_map,
812 },
813 .mux_sel_bit = 11,
814 .freq_tbl = clk_tbl_gfx2d,
815 .clkr = {
816 .enable_reg = 0x0074,
817 .enable_mask = BIT(2),
818 .hw.init = &(struct clk_init_data){
819 .name = "gfx2d1_src",
820 .parent_names = mmcc_pxo_pll8_pll2,
821 .num_parents = 3,
822 .ops = &clk_dyn_rcg_ops,
823 },
824 },
825};
826
827static struct clk_branch gfx2d1_clk = {
828 .halt_reg = 0x01c8,
829 .halt_bit = 14,
830 .clkr = {
831 .enable_reg = 0x0074,
832 .enable_mask = BIT(0),
833 .hw.init = &(struct clk_init_data){
834 .name = "gfx2d1_clk",
835 .parent_names = (const char *[]){ "gfx2d1_src" },
836 .num_parents = 1,
837 .ops = &clk_branch_ops,
838 .flags = CLK_SET_RATE_PARENT,
839 },
840 },
841};
842
843static struct freq_tbl clk_tbl_gfx3d[] = {
844 { 27000000, P_PXO, 1, 0 },
845 { 48000000, P_PLL8, 1, 8 },
846 { 54857000, P_PLL8, 1, 7 },
847 { 64000000, P_PLL8, 1, 6 },
848 { 76800000, P_PLL8, 1, 5 },
849 { 96000000, P_PLL8, 1, 4 },
850 { 128000000, P_PLL8, 1, 3 },
851 { 145455000, P_PLL2, 2, 11 },
852 { 160000000, P_PLL2, 1, 5 },
853 { 177778000, P_PLL2, 2, 9 },
854 { 200000000, P_PLL2, 1, 4 },
855 { 228571000, P_PLL2, 2, 7 },
856 { 266667000, P_PLL2, 1, 3 },
857 { 300000000, P_PLL3, 1, 4 },
858 { 320000000, P_PLL2, 2, 5 },
859 { 400000000, P_PLL2, 1, 2 },
860 { }
861};
862
863static struct clk_dyn_rcg gfx3d_src = {
864 .ns_reg = 0x008c,
865 .md_reg[0] = 0x0084,
866 .md_reg[1] = 0x0088,
867 .mn[0] = {
868 .mnctr_en_bit = 8,
869 .mnctr_reset_bit = 25,
870 .mnctr_mode_shift = 9,
871 .n_val_shift = 18,
872 .m_val_shift = 4,
873 .width = 4,
874 },
875 .mn[1] = {
876 .mnctr_en_bit = 5,
877 .mnctr_reset_bit = 24,
878 .mnctr_mode_shift = 6,
879 .n_val_shift = 14,
880 .m_val_shift = 4,
881 .width = 4,
882 },
883 .s[0] = {
884 .src_sel_shift = 3,
885 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
886 },
887 .s[1] = {
888 .src_sel_shift = 0,
889 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
890 },
891 .mux_sel_bit = 11,
892 .freq_tbl = clk_tbl_gfx3d,
893 .clkr = {
894 .enable_reg = 0x0080,
895 .enable_mask = BIT(2),
896 .hw.init = &(struct clk_init_data){
897 .name = "gfx3d_src",
898 .parent_names = mmcc_pxo_pll8_pll2_pll3,
899 .num_parents = 3,
900 .ops = &clk_dyn_rcg_ops,
901 },
902 },
903};
904
905static struct clk_branch gfx3d_clk = {
906 .halt_reg = 0x01c8,
907 .halt_bit = 4,
908 .clkr = {
909 .enable_reg = 0x0080,
910 .enable_mask = BIT(0),
911 .hw.init = &(struct clk_init_data){
912 .name = "gfx3d_clk",
913 .parent_names = (const char *[]){ "gfx3d_src" },
914 .num_parents = 1,
915 .ops = &clk_branch_ops,
916 .flags = CLK_SET_RATE_PARENT,
917 },
918 },
919};
920
921static struct freq_tbl clk_tbl_ijpeg[] = {
922 { 27000000, P_PXO, 1, 0, 0 },
923 { 36570000, P_PLL8, 1, 2, 21 },
924 { 54860000, P_PLL8, 7, 0, 0 },
925 { 96000000, P_PLL8, 4, 0, 0 },
926 { 109710000, P_PLL8, 1, 2, 7 },
927 { 128000000, P_PLL8, 3, 0, 0 },
928 { 153600000, P_PLL8, 1, 2, 5 },
929 { 200000000, P_PLL2, 4, 0, 0 },
930 { 228571000, P_PLL2, 1, 2, 7 },
931 { 266667000, P_PLL2, 1, 1, 3 },
932 { 320000000, P_PLL2, 1, 2, 5 },
933 { }
934};
935
936static struct clk_rcg ijpeg_src = {
937 .ns_reg = 0x00a0,
938 .md_reg = 0x009c,
939 .mn = {
940 .mnctr_en_bit = 5,
941 .mnctr_reset_bit = 7,
942 .mnctr_mode_shift = 6,
943 .n_val_shift = 16,
944 .m_val_shift = 8,
945 .width = 8,
946 },
947 .p = {
948 .pre_div_shift = 12,
949 .pre_div_width = 2,
950 },
951 .s = {
952 .src_sel_shift = 0,
953 .parent_map = mmcc_pxo_pll8_pll2_map,
954 },
955 .freq_tbl = clk_tbl_ijpeg,
956 .clkr = {
957 .enable_reg = 0x0098,
958 .enable_mask = BIT(2),
959 .hw.init = &(struct clk_init_data){
960 .name = "ijpeg_src",
961 .parent_names = mmcc_pxo_pll8_pll2,
962 .num_parents = 3,
963 .ops = &clk_rcg_ops,
964 },
965 },
966};
967
968static struct clk_branch ijpeg_clk = {
969 .halt_reg = 0x01c8,
970 .halt_bit = 24,
971 .clkr = {
972 .enable_reg = 0x0098,
973 .enable_mask = BIT(0),
974 .hw.init = &(struct clk_init_data){
975 .name = "ijpeg_clk",
976 .parent_names = (const char *[]){ "ijpeg_src" },
977 .num_parents = 1,
978 .ops = &clk_branch_ops,
979 .flags = CLK_SET_RATE_PARENT,
980 },
981 },
982};
983
984static struct freq_tbl clk_tbl_jpegd[] = {
985 { 64000000, P_PLL8, 6 },
986 { 76800000, P_PLL8, 5 },
987 { 96000000, P_PLL8, 4 },
988 { 160000000, P_PLL2, 5 },
989 { 200000000, P_PLL2, 4 },
990 { }
991};
992
993static struct clk_rcg jpegd_src = {
994 .ns_reg = 0x00ac,
995 .p = {
996 .pre_div_shift = 12,
997 .pre_div_width = 2,
998 },
999 .s = {
1000 .src_sel_shift = 0,
1001 .parent_map = mmcc_pxo_pll8_pll2_map,
1002 },
1003 .freq_tbl = clk_tbl_jpegd,
1004 .clkr = {
1005 .enable_reg = 0x00a4,
1006 .enable_mask = BIT(2),
1007 .hw.init = &(struct clk_init_data){
1008 .name = "jpegd_src",
1009 .parent_names = mmcc_pxo_pll8_pll2,
1010 .num_parents = 3,
1011 .ops = &clk_rcg_ops,
1012 },
1013 },
1014};
1015
1016static struct clk_branch jpegd_clk = {
1017 .halt_reg = 0x01c8,
1018 .halt_bit = 19,
1019 .clkr = {
1020 .enable_reg = 0x00a4,
1021 .enable_mask = BIT(0),
1022 .hw.init = &(struct clk_init_data){
1023 .name = "jpegd_clk",
1024 .parent_names = (const char *[]){ "jpegd_src" },
1025 .num_parents = 1,
1026 .ops = &clk_branch_ops,
1027 .flags = CLK_SET_RATE_PARENT,
1028 },
1029 },
1030};
1031
1032static struct freq_tbl clk_tbl_mdp[] = {
1033 { 9600000, P_PLL8, 1, 1, 40 },
1034 { 13710000, P_PLL8, 1, 1, 28 },
1035 { 27000000, P_PXO, 1, 0, 0 },
1036 { 29540000, P_PLL8, 1, 1, 13 },
1037 { 34910000, P_PLL8, 1, 1, 11 },
1038 { 38400000, P_PLL8, 1, 1, 10 },
1039 { 59080000, P_PLL8, 1, 2, 13 },
1040 { 76800000, P_PLL8, 1, 1, 5 },
1041 { 85330000, P_PLL8, 1, 2, 9 },
1042 { 96000000, P_PLL8, 1, 1, 4 },
1043 { 128000000, P_PLL8, 1, 1, 3 },
1044 { 160000000, P_PLL2, 1, 1, 5 },
1045 { 177780000, P_PLL2, 1, 2, 9 },
1046 { 200000000, P_PLL2, 1, 1, 4 },
1047 { 228571000, P_PLL2, 1, 2, 7 },
1048 { 266667000, P_PLL2, 1, 1, 3 },
1049 { }
1050};
1051
1052static struct clk_dyn_rcg mdp_src = {
1053 .ns_reg = 0x00d0,
1054 .md_reg[0] = 0x00c4,
1055 .md_reg[1] = 0x00c8,
1056 .mn[0] = {
1057 .mnctr_en_bit = 8,
1058 .mnctr_reset_bit = 31,
1059 .mnctr_mode_shift = 9,
1060 .n_val_shift = 22,
1061 .m_val_shift = 8,
1062 .width = 8,
1063 },
1064 .mn[1] = {
1065 .mnctr_en_bit = 5,
1066 .mnctr_reset_bit = 30,
1067 .mnctr_mode_shift = 6,
1068 .n_val_shift = 14,
1069 .m_val_shift = 8,
1070 .width = 8,
1071 },
1072 .s[0] = {
1073 .src_sel_shift = 3,
1074 .parent_map = mmcc_pxo_pll8_pll2_map,
1075 },
1076 .s[1] = {
1077 .src_sel_shift = 0,
1078 .parent_map = mmcc_pxo_pll8_pll2_map,
1079 },
1080 .mux_sel_bit = 11,
1081 .freq_tbl = clk_tbl_mdp,
1082 .clkr = {
1083 .enable_reg = 0x00c0,
1084 .enable_mask = BIT(2),
1085 .hw.init = &(struct clk_init_data){
1086 .name = "mdp_src",
1087 .parent_names = mmcc_pxo_pll8_pll2,
1088 .num_parents = 3,
1089 .ops = &clk_dyn_rcg_ops,
1090 },
1091 },
1092};
1093
1094static struct clk_branch mdp_clk = {
1095 .halt_reg = 0x01d0,
1096 .halt_bit = 10,
1097 .clkr = {
1098 .enable_reg = 0x00c0,
1099 .enable_mask = BIT(0),
1100 .hw.init = &(struct clk_init_data){
1101 .name = "mdp_clk",
1102 .parent_names = (const char *[]){ "mdp_src" },
1103 .num_parents = 1,
1104 .ops = &clk_branch_ops,
1105 .flags = CLK_SET_RATE_PARENT,
1106 },
1107 },
1108};
1109
1110static struct clk_branch mdp_lut_clk = {
1111 .halt_reg = 0x01e8,
1112 .halt_bit = 13,
1113 .clkr = {
1114 .enable_reg = 0x016c,
1115 .enable_mask = BIT(0),
1116 .hw.init = &(struct clk_init_data){
1117 .parent_names = (const char *[]){ "mdp_clk" },
1118 .num_parents = 1,
1119 .name = "mdp_lut_clk",
1120 .ops = &clk_branch_ops,
1121 .flags = CLK_SET_RATE_PARENT,
1122 },
1123 },
1124};
1125
1126static struct clk_branch mdp_vsync_clk = {
1127 .halt_reg = 0x01cc,
1128 .halt_bit = 22,
1129 .clkr = {
1130 .enable_reg = 0x0058,
1131 .enable_mask = BIT(6),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "mdp_vsync_clk",
1134 .parent_names = (const char *[]){ "pxo" },
1135 .num_parents = 1,
1136 .ops = &clk_branch_ops
1137 },
1138 },
1139};
1140
1141static struct freq_tbl clk_tbl_rot[] = {
1142 { 27000000, P_PXO, 1 },
1143 { 29540000, P_PLL8, 13 },
1144 { 32000000, P_PLL8, 12 },
1145 { 38400000, P_PLL8, 10 },
1146 { 48000000, P_PLL8, 8 },
1147 { 54860000, P_PLL8, 7 },
1148 { 64000000, P_PLL8, 6 },
1149 { 76800000, P_PLL8, 5 },
1150 { 96000000, P_PLL8, 4 },
1151 { 100000000, P_PLL2, 8 },
1152 { 114290000, P_PLL2, 7 },
1153 { 133330000, P_PLL2, 6 },
1154 { 160000000, P_PLL2, 5 },
1155 { 200000000, P_PLL2, 4 },
1156 { }
1157};
1158
1159static struct clk_dyn_rcg rot_src = {
1160 .ns_reg = 0x00e8,
1161 .p[0] = {
1162 .pre_div_shift = 22,
1163 .pre_div_width = 4,
1164 },
1165 .p[1] = {
1166 .pre_div_shift = 26,
1167 .pre_div_width = 4,
1168 },
1169 .s[0] = {
1170 .src_sel_shift = 16,
1171 .parent_map = mmcc_pxo_pll8_pll2_map,
1172 },
1173 .s[1] = {
1174 .src_sel_shift = 19,
1175 .parent_map = mmcc_pxo_pll8_pll2_map,
1176 },
1177 .mux_sel_bit = 30,
1178 .freq_tbl = clk_tbl_rot,
1179 .clkr = {
1180 .enable_reg = 0x00e0,
1181 .enable_mask = BIT(2),
1182 .hw.init = &(struct clk_init_data){
1183 .name = "rot_src",
1184 .parent_names = mmcc_pxo_pll8_pll2,
1185 .num_parents = 3,
1186 .ops = &clk_dyn_rcg_ops,
1187 },
1188 },
1189};
1190
1191static struct clk_branch rot_clk = {
1192 .halt_reg = 0x01d0,
1193 .halt_bit = 15,
1194 .clkr = {
1195 .enable_reg = 0x00e0,
1196 .enable_mask = BIT(0),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "rot_clk",
1199 .parent_names = (const char *[]){ "rot_src" },
1200 .num_parents = 1,
1201 .ops = &clk_branch_ops,
1202 .flags = CLK_SET_RATE_PARENT,
1203 },
1204 },
1205};
1206
1207#define P_HDMI_PLL 1
1208
1209static u8 mmcc_pxo_hdmi_map[] = {
1210 [P_PXO] = 0,
1211 [P_HDMI_PLL] = 2,
1212};
1213
1214static const char *mmcc_pxo_hdmi[] = {
1215 "pxo",
1216 "hdmi_pll",
1217};
1218
1219static struct freq_tbl clk_tbl_tv[] = {
1220 { 25200000, P_HDMI_PLL, 1, 0, 0 },
1221 { 27000000, P_HDMI_PLL, 1, 0, 0 },
1222 { 27030000, P_HDMI_PLL, 1, 0, 0 },
1223 { 74250000, P_HDMI_PLL, 1, 0, 0 },
1224 { 108000000, P_HDMI_PLL, 1, 0, 0 },
1225 { 148500000, P_HDMI_PLL, 1, 0, 0 },
1226 { }
1227};
1228
1229static struct clk_rcg tv_src = {
1230 .ns_reg = 0x00f4,
1231 .md_reg = 0x00f0,
1232 .mn = {
1233 .mnctr_en_bit = 5,
1234 .mnctr_reset_bit = 7,
1235 .mnctr_mode_shift = 6,
1236 .n_val_shift = 16,
1237 .m_val_shift = 8,
1238 .width = 8,
1239 },
1240 .p = {
1241 .pre_div_shift = 14,
1242 .pre_div_width = 2,
1243 },
1244 .s = {
1245 .src_sel_shift = 0,
1246 .parent_map = mmcc_pxo_hdmi_map,
1247 },
1248 .freq_tbl = clk_tbl_tv,
1249 .clkr = {
1250 .enable_reg = 0x00ec,
1251 .enable_mask = BIT(2),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "tv_src",
1254 .parent_names = mmcc_pxo_hdmi,
1255 .num_parents = 2,
1256 .ops = &clk_rcg_ops,
1257 .flags = CLK_SET_RATE_PARENT,
1258 },
1259 },
1260};
1261
1262static const char *tv_src_name[] = { "tv_src" };
1263
1264static struct clk_branch tv_enc_clk = {
1265 .halt_reg = 0x01d4,
1266 .halt_bit = 9,
1267 .clkr = {
1268 .enable_reg = 0x00ec,
1269 .enable_mask = BIT(8),
1270 .hw.init = &(struct clk_init_data){
1271 .parent_names = tv_src_name,
1272 .num_parents = 1,
1273 .name = "tv_enc_clk",
1274 .ops = &clk_branch_ops,
1275 .flags = CLK_SET_RATE_PARENT,
1276 },
1277 },
1278};
1279
1280static struct clk_branch tv_dac_clk = {
1281 .halt_reg = 0x01d4,
1282 .halt_bit = 10,
1283 .clkr = {
1284 .enable_reg = 0x00ec,
1285 .enable_mask = BIT(10),
1286 .hw.init = &(struct clk_init_data){
1287 .parent_names = tv_src_name,
1288 .num_parents = 1,
1289 .name = "tv_dac_clk",
1290 .ops = &clk_branch_ops,
1291 .flags = CLK_SET_RATE_PARENT,
1292 },
1293 },
1294};
1295
1296static struct clk_branch mdp_tv_clk = {
1297 .halt_reg = 0x01d4,
1298 .halt_bit = 12,
1299 .clkr = {
1300 .enable_reg = 0x00ec,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .parent_names = tv_src_name,
1304 .num_parents = 1,
1305 .name = "mdp_tv_clk",
1306 .ops = &clk_branch_ops,
1307 .flags = CLK_SET_RATE_PARENT,
1308 },
1309 },
1310};
1311
1312static struct clk_branch hdmi_tv_clk = {
1313 .halt_reg = 0x01d4,
1314 .halt_bit = 11,
1315 .clkr = {
1316 .enable_reg = 0x00ec,
1317 .enable_mask = BIT(12),
1318 .hw.init = &(struct clk_init_data){
1319 .parent_names = tv_src_name,
1320 .num_parents = 1,
1321 .name = "hdmi_tv_clk",
1322 .ops = &clk_branch_ops,
1323 .flags = CLK_SET_RATE_PARENT,
1324 },
1325 },
1326};
1327
1328static struct clk_branch hdmi_app_clk = {
1329 .halt_reg = 0x01cc,
1330 .halt_bit = 25,
1331 .clkr = {
1332 .enable_reg = 0x005c,
1333 .enable_mask = BIT(11),
1334 .hw.init = &(struct clk_init_data){
1335 .parent_names = (const char *[]){ "pxo" },
1336 .num_parents = 1,
1337 .name = "hdmi_app_clk",
1338 .ops = &clk_branch_ops,
1339 },
1340 },
1341};
1342
1343static struct freq_tbl clk_tbl_vcodec[] = {
1344 { 27000000, P_PXO, 1, 0 },
1345 { 32000000, P_PLL8, 1, 12 },
1346 { 48000000, P_PLL8, 1, 8 },
1347 { 54860000, P_PLL8, 1, 7 },
1348 { 96000000, P_PLL8, 1, 4 },
1349 { 133330000, P_PLL2, 1, 6 },
1350 { 200000000, P_PLL2, 1, 4 },
1351 { 228570000, P_PLL2, 2, 7 },
1352 { 266670000, P_PLL2, 1, 3 },
1353 { }
1354};
1355
1356static struct clk_dyn_rcg vcodec_src = {
1357 .ns_reg = 0x0100,
1358 .md_reg[0] = 0x00fc,
1359 .md_reg[1] = 0x0128,
1360 .mn[0] = {
1361 .mnctr_en_bit = 5,
1362 .mnctr_reset_bit = 31,
1363 .mnctr_mode_shift = 6,
1364 .n_val_shift = 11,
1365 .m_val_shift = 8,
1366 .width = 8,
1367 },
1368 .mn[1] = {
1369 .mnctr_en_bit = 10,
1370 .mnctr_reset_bit = 30,
1371 .mnctr_mode_shift = 11,
1372 .n_val_shift = 19,
1373 .m_val_shift = 8,
1374 .width = 8,
1375 },
1376 .s[0] = {
1377 .src_sel_shift = 27,
1378 .parent_map = mmcc_pxo_pll8_pll2_map,
1379 },
1380 .s[1] = {
1381 .src_sel_shift = 0,
1382 .parent_map = mmcc_pxo_pll8_pll2_map,
1383 },
1384 .mux_sel_bit = 13,
1385 .freq_tbl = clk_tbl_vcodec,
1386 .clkr = {
1387 .enable_reg = 0x00f8,
1388 .enable_mask = BIT(2),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "vcodec_src",
1391 .parent_names = mmcc_pxo_pll8_pll2,
1392 .num_parents = 3,
1393 .ops = &clk_dyn_rcg_ops,
1394 },
1395 },
1396};
1397
1398static struct clk_branch vcodec_clk = {
1399 .halt_reg = 0x01d0,
1400 .halt_bit = 29,
1401 .clkr = {
1402 .enable_reg = 0x00f8,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "vcodec_clk",
1406 .parent_names = (const char *[]){ "vcodec_src" },
1407 .num_parents = 1,
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_SET_RATE_PARENT,
1410 },
1411 },
1412};
1413
1414static struct freq_tbl clk_tbl_vpe[] = {
1415 { 27000000, P_PXO, 1 },
1416 { 34909000, P_PLL8, 11 },
1417 { 38400000, P_PLL8, 10 },
1418 { 64000000, P_PLL8, 6 },
1419 { 76800000, P_PLL8, 5 },
1420 { 96000000, P_PLL8, 4 },
1421 { 100000000, P_PLL2, 8 },
1422 { 160000000, P_PLL2, 5 },
1423 { }
1424};
1425
1426static struct clk_rcg vpe_src = {
1427 .ns_reg = 0x0118,
1428 .p = {
1429 .pre_div_shift = 12,
1430 .pre_div_width = 4,
1431 },
1432 .s = {
1433 .src_sel_shift = 0,
1434 .parent_map = mmcc_pxo_pll8_pll2_map,
1435 },
1436 .freq_tbl = clk_tbl_vpe,
1437 .clkr = {
1438 .enable_reg = 0x0110,
1439 .enable_mask = BIT(2),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "vpe_src",
1442 .parent_names = mmcc_pxo_pll8_pll2,
1443 .num_parents = 3,
1444 .ops = &clk_rcg_ops,
1445 },
1446 },
1447};
1448
1449static struct clk_branch vpe_clk = {
1450 .halt_reg = 0x01c8,
1451 .halt_bit = 28,
1452 .clkr = {
1453 .enable_reg = 0x0110,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "vpe_clk",
1457 .parent_names = (const char *[]){ "vpe_src" },
1458 .num_parents = 1,
1459 .ops = &clk_branch_ops,
1460 .flags = CLK_SET_RATE_PARENT,
1461 },
1462 },
1463};
1464
1465static struct freq_tbl clk_tbl_vfe[] = {
1466 { 13960000, P_PLL8, 1, 2, 55 },
1467 { 27000000, P_PXO, 1, 0, 0 },
1468 { 36570000, P_PLL8, 1, 2, 21 },
1469 { 38400000, P_PLL8, 2, 1, 5 },
1470 { 45180000, P_PLL8, 1, 2, 17 },
1471 { 48000000, P_PLL8, 2, 1, 4 },
1472 { 54860000, P_PLL8, 1, 1, 7 },
1473 { 64000000, P_PLL8, 2, 1, 3 },
1474 { 76800000, P_PLL8, 1, 1, 5 },
1475 { 96000000, P_PLL8, 2, 1, 2 },
1476 { 109710000, P_PLL8, 1, 2, 7 },
1477 { 128000000, P_PLL8, 1, 1, 3 },
1478 { 153600000, P_PLL8, 1, 2, 5 },
1479 { 200000000, P_PLL2, 2, 1, 2 },
1480 { 228570000, P_PLL2, 1, 2, 7 },
1481 { 266667000, P_PLL2, 1, 1, 3 },
1482 { 320000000, P_PLL2, 1, 2, 5 },
1483 { }
1484};
1485
1486static struct clk_rcg vfe_src = {
1487 .ns_reg = 0x0108,
1488 .mn = {
1489 .mnctr_en_bit = 5,
1490 .mnctr_reset_bit = 7,
1491 .mnctr_mode_shift = 6,
1492 .n_val_shift = 16,
1493 .m_val_shift = 8,
1494 .width = 8,
1495 },
1496 .p = {
1497 .pre_div_shift = 10,
1498 .pre_div_width = 1,
1499 },
1500 .s = {
1501 .src_sel_shift = 0,
1502 .parent_map = mmcc_pxo_pll8_pll2_map,
1503 },
1504 .freq_tbl = clk_tbl_vfe,
1505 .clkr = {
1506 .enable_reg = 0x0104,
1507 .enable_mask = BIT(2),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "vfe_src",
1510 .parent_names = mmcc_pxo_pll8_pll2,
1511 .num_parents = 3,
1512 .ops = &clk_rcg_ops,
1513 },
1514 },
1515};
1516
1517static struct clk_branch vfe_clk = {
1518 .halt_reg = 0x01cc,
1519 .halt_bit = 6,
1520 .clkr = {
1521 .enable_reg = 0x0104,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "vfe_clk",
1525 .parent_names = (const char *[]){ "vfe_src" },
1526 .num_parents = 1,
1527 .ops = &clk_branch_ops,
1528 .flags = CLK_SET_RATE_PARENT,
1529 },
1530 },
1531};
1532
1533static struct clk_branch vfe_csi_clk = {
1534 .halt_reg = 0x01cc,
1535 .halt_bit = 8,
1536 .clkr = {
1537 .enable_reg = 0x0104,
1538 .enable_mask = BIT(12),
1539 .hw.init = &(struct clk_init_data){
1540 .parent_names = (const char *[]){ "vfe_src" },
1541 .num_parents = 1,
1542 .name = "vfe_csi_clk",
1543 .ops = &clk_branch_ops,
1544 .flags = CLK_SET_RATE_PARENT,
1545 },
1546 },
1547};
1548
1549static struct clk_branch gmem_axi_clk = {
1550 .halt_reg = 0x01d8,
1551 .halt_bit = 6,
1552 .clkr = {
1553 .enable_reg = 0x0018,
1554 .enable_mask = BIT(24),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "gmem_axi_clk",
1557 .ops = &clk_branch_ops,
1558 .flags = CLK_IS_ROOT,
1559 },
1560 },
1561};
1562
1563static struct clk_branch ijpeg_axi_clk = {
1564 .hwcg_reg = 0x0018,
1565 .hwcg_bit = 11,
1566 .halt_reg = 0x01d8,
1567 .halt_bit = 4,
1568 .clkr = {
1569 .enable_reg = 0x0018,
1570 .enable_mask = BIT(21),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "ijpeg_axi_clk",
1573 .ops = &clk_branch_ops,
1574 .flags = CLK_IS_ROOT,
1575 },
1576 },
1577};
1578
1579static struct clk_branch mmss_imem_axi_clk = {
1580 .hwcg_reg = 0x0018,
1581 .hwcg_bit = 15,
1582 .halt_reg = 0x01d8,
1583 .halt_bit = 7,
1584 .clkr = {
1585 .enable_reg = 0x0018,
1586 .enable_mask = BIT(22),
1587 .hw.init = &(struct clk_init_data){
1588 .name = "mmss_imem_axi_clk",
1589 .ops = &clk_branch_ops,
1590 .flags = CLK_IS_ROOT,
1591 },
1592 },
1593};
1594
1595static struct clk_branch jpegd_axi_clk = {
1596 .halt_reg = 0x01d8,
1597 .halt_bit = 5,
1598 .clkr = {
1599 .enable_reg = 0x0018,
1600 .enable_mask = BIT(25),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "jpegd_axi_clk",
1603 .ops = &clk_branch_ops,
1604 .flags = CLK_IS_ROOT,
1605 },
1606 },
1607};
1608
1609static struct clk_branch vcodec_axi_b_clk = {
1610 .hwcg_reg = 0x0114,
1611 .hwcg_bit = 22,
1612 .halt_reg = 0x01e8,
1613 .halt_bit = 25,
1614 .clkr = {
1615 .enable_reg = 0x0114,
1616 .enable_mask = BIT(23),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "vcodec_axi_b_clk",
1619 .ops = &clk_branch_ops,
1620 .flags = CLK_IS_ROOT,
1621 },
1622 },
1623};
1624
1625static struct clk_branch vcodec_axi_a_clk = {
1626 .hwcg_reg = 0x0114,
1627 .hwcg_bit = 24,
1628 .halt_reg = 0x01e8,
1629 .halt_bit = 26,
1630 .clkr = {
1631 .enable_reg = 0x0114,
1632 .enable_mask = BIT(25),
1633 .hw.init = &(struct clk_init_data){
1634 .name = "vcodec_axi_a_clk",
1635 .ops = &clk_branch_ops,
1636 .flags = CLK_IS_ROOT,
1637 },
1638 },
1639};
1640
1641static struct clk_branch vcodec_axi_clk = {
1642 .hwcg_reg = 0x0018,
1643 .hwcg_bit = 13,
1644 .halt_reg = 0x01d8,
1645 .halt_bit = 3,
1646 .clkr = {
1647 .enable_reg = 0x0018,
1648 .enable_mask = BIT(19),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "vcodec_axi_clk",
1651 .ops = &clk_branch_ops,
1652 .flags = CLK_IS_ROOT,
1653 },
1654 },
1655};
1656
1657static struct clk_branch vfe_axi_clk = {
1658 .halt_reg = 0x01d8,
1659 .halt_bit = 0,
1660 .clkr = {
1661 .enable_reg = 0x0018,
1662 .enable_mask = BIT(18),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "vfe_axi_clk",
1665 .ops = &clk_branch_ops,
1666 .flags = CLK_IS_ROOT,
1667 },
1668 },
1669};
1670
1671static struct clk_branch mdp_axi_clk = {
1672 .hwcg_reg = 0x0018,
1673 .hwcg_bit = 16,
1674 .halt_reg = 0x01d8,
1675 .halt_bit = 8,
1676 .clkr = {
1677 .enable_reg = 0x0018,
1678 .enable_mask = BIT(23),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "mdp_axi_clk",
1681 .ops = &clk_branch_ops,
1682 .flags = CLK_IS_ROOT,
1683 },
1684 },
1685};
1686
1687static struct clk_branch rot_axi_clk = {
1688 .hwcg_reg = 0x0020,
1689 .hwcg_bit = 25,
1690 .halt_reg = 0x01d8,
1691 .halt_bit = 2,
1692 .clkr = {
1693 .enable_reg = 0x0020,
1694 .enable_mask = BIT(24),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "rot_axi_clk",
1697 .ops = &clk_branch_ops,
1698 .flags = CLK_IS_ROOT,
1699 },
1700 },
1701};
1702
1703static struct clk_branch vpe_axi_clk = {
1704 .hwcg_reg = 0x0020,
1705 .hwcg_bit = 27,
1706 .halt_reg = 0x01d8,
1707 .halt_bit = 1,
1708 .clkr = {
1709 .enable_reg = 0x0020,
1710 .enable_mask = BIT(26),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "vpe_axi_clk",
1713 .ops = &clk_branch_ops,
1714 .flags = CLK_IS_ROOT,
1715 },
1716 },
1717};
1718
1719static struct clk_branch gfx3d_axi_clk = {
1720 .hwcg_reg = 0x0244,
1721 .hwcg_bit = 24,
1722 .halt_reg = 0x0240,
1723 .halt_bit = 30,
1724 .clkr = {
1725 .enable_reg = 0x0244,
1726 .enable_mask = BIT(25),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gfx3d_axi_clk",
1729 .ops = &clk_branch_ops,
1730 .flags = CLK_IS_ROOT,
1731 },
1732 },
1733};
1734
1735static struct clk_branch amp_ahb_clk = {
1736 .halt_reg = 0x01dc,
1737 .halt_bit = 18,
1738 .clkr = {
1739 .enable_reg = 0x0008,
1740 .enable_mask = BIT(24),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "amp_ahb_clk",
1743 .ops = &clk_branch_ops,
1744 .flags = CLK_IS_ROOT,
1745 },
1746 },
1747};
1748
1749static struct clk_branch csi_ahb_clk = {
1750 .halt_reg = 0x01dc,
1751 .halt_bit = 16,
1752 .clkr = {
1753 .enable_reg = 0x0008,
1754 .enable_mask = BIT(7),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "csi_ahb_clk",
1757 .ops = &clk_branch_ops,
1758 .flags = CLK_IS_ROOT
1759 },
1760 },
1761};
1762
1763static struct clk_branch dsi_m_ahb_clk = {
1764 .halt_reg = 0x01dc,
1765 .halt_bit = 19,
1766 .clkr = {
1767 .enable_reg = 0x0008,
1768 .enable_mask = BIT(9),
1769 .hw.init = &(struct clk_init_data){
1770 .name = "dsi_m_ahb_clk",
1771 .ops = &clk_branch_ops,
1772 .flags = CLK_IS_ROOT,
1773 },
1774 },
1775};
1776
1777static struct clk_branch dsi_s_ahb_clk = {
1778 .hwcg_reg = 0x0038,
1779 .hwcg_bit = 20,
1780 .halt_reg = 0x01dc,
1781 .halt_bit = 21,
1782 .clkr = {
1783 .enable_reg = 0x0008,
1784 .enable_mask = BIT(18),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "dsi_s_ahb_clk",
1787 .ops = &clk_branch_ops,
1788 .flags = CLK_IS_ROOT,
1789 },
1790 },
1791};
1792
1793static struct clk_branch dsi2_m_ahb_clk = {
1794 .halt_reg = 0x01d8,
1795 .halt_bit = 18,
1796 .clkr = {
1797 .enable_reg = 0x0008,
1798 .enable_mask = BIT(17),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "dsi2_m_ahb_clk",
1801 .ops = &clk_branch_ops,
1802 .flags = CLK_IS_ROOT
1803 },
1804 },
1805};
1806
1807static struct clk_branch dsi2_s_ahb_clk = {
1808 .hwcg_reg = 0x0038,
1809 .hwcg_bit = 15,
1810 .halt_reg = 0x01dc,
1811 .halt_bit = 20,
1812 .clkr = {
1813 .enable_reg = 0x0008,
1814 .enable_mask = BIT(22),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "dsi2_s_ahb_clk",
1817 .ops = &clk_branch_ops,
1818 .flags = CLK_IS_ROOT,
1819 },
1820 },
1821};
1822
1823static struct clk_branch gfx2d0_ahb_clk = {
1824 .hwcg_reg = 0x0038,
1825 .hwcg_bit = 28,
1826 .halt_reg = 0x01dc,
1827 .halt_bit = 2,
1828 .clkr = {
1829 .enable_reg = 0x0008,
1830 .enable_mask = BIT(19),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "gfx2d0_ahb_clk",
1833 .ops = &clk_branch_ops,
1834 .flags = CLK_IS_ROOT,
1835 },
1836 },
1837};
1838
1839static struct clk_branch gfx2d1_ahb_clk = {
1840 .hwcg_reg = 0x0038,
1841 .hwcg_bit = 29,
1842 .halt_reg = 0x01dc,
1843 .halt_bit = 3,
1844 .clkr = {
1845 .enable_reg = 0x0008,
1846 .enable_mask = BIT(2),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "gfx2d1_ahb_clk",
1849 .ops = &clk_branch_ops,
1850 .flags = CLK_IS_ROOT,
1851 },
1852 },
1853};
1854
1855static struct clk_branch gfx3d_ahb_clk = {
1856 .hwcg_reg = 0x0038,
1857 .hwcg_bit = 27,
1858 .halt_reg = 0x01dc,
1859 .halt_bit = 4,
1860 .clkr = {
1861 .enable_reg = 0x0008,
1862 .enable_mask = BIT(3),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "gfx3d_ahb_clk",
1865 .ops = &clk_branch_ops,
1866 .flags = CLK_IS_ROOT,
1867 },
1868 },
1869};
1870
1871static struct clk_branch hdmi_m_ahb_clk = {
1872 .hwcg_reg = 0x0038,
1873 .hwcg_bit = 21,
1874 .halt_reg = 0x01dc,
1875 .halt_bit = 5,
1876 .clkr = {
1877 .enable_reg = 0x0008,
1878 .enable_mask = BIT(14),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "hdmi_m_ahb_clk",
1881 .ops = &clk_branch_ops,
1882 .flags = CLK_IS_ROOT,
1883 },
1884 },
1885};
1886
1887static struct clk_branch hdmi_s_ahb_clk = {
1888 .hwcg_reg = 0x0038,
1889 .hwcg_bit = 22,
1890 .halt_reg = 0x01dc,
1891 .halt_bit = 6,
1892 .clkr = {
1893 .enable_reg = 0x0008,
1894 .enable_mask = BIT(4),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "hdmi_s_ahb_clk",
1897 .ops = &clk_branch_ops,
1898 .flags = CLK_IS_ROOT,
1899 },
1900 },
1901};
1902
1903static struct clk_branch ijpeg_ahb_clk = {
1904 .halt_reg = 0x01dc,
1905 .halt_bit = 9,
1906 .clkr = {
1907 .enable_reg = 0x0008,
1908 .enable_mask = BIT(5),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "ijpeg_ahb_clk",
1911 .ops = &clk_branch_ops,
1912 .flags = CLK_IS_ROOT
1913 },
1914 },
1915};
1916
1917static struct clk_branch mmss_imem_ahb_clk = {
1918 .hwcg_reg = 0x0038,
1919 .hwcg_bit = 12,
1920 .halt_reg = 0x01dc,
1921 .halt_bit = 10,
1922 .clkr = {
1923 .enable_reg = 0x0008,
1924 .enable_mask = BIT(6),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "mmss_imem_ahb_clk",
1927 .ops = &clk_branch_ops,
1928 .flags = CLK_IS_ROOT
1929 },
1930 },
1931};
1932
1933static struct clk_branch jpegd_ahb_clk = {
1934 .halt_reg = 0x01dc,
1935 .halt_bit = 7,
1936 .clkr = {
1937 .enable_reg = 0x0008,
1938 .enable_mask = BIT(21),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "jpegd_ahb_clk",
1941 .ops = &clk_branch_ops,
1942 .flags = CLK_IS_ROOT,
1943 },
1944 },
1945};
1946
1947static struct clk_branch mdp_ahb_clk = {
1948 .halt_reg = 0x01dc,
1949 .halt_bit = 11,
1950 .clkr = {
1951 .enable_reg = 0x0008,
1952 .enable_mask = BIT(10),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "mdp_ahb_clk",
1955 .ops = &clk_branch_ops,
1956 .flags = CLK_IS_ROOT,
1957 },
1958 },
1959};
1960
1961static struct clk_branch rot_ahb_clk = {
1962 .halt_reg = 0x01dc,
1963 .halt_bit = 13,
1964 .clkr = {
1965 .enable_reg = 0x0008,
1966 .enable_mask = BIT(12),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "rot_ahb_clk",
1969 .ops = &clk_branch_ops,
1970 .flags = CLK_IS_ROOT
1971 },
1972 },
1973};
1974
1975static struct clk_branch smmu_ahb_clk = {
1976 .hwcg_reg = 0x0008,
1977 .hwcg_bit = 26,
1978 .halt_reg = 0x01dc,
1979 .halt_bit = 22,
1980 .clkr = {
1981 .enable_reg = 0x0008,
1982 .enable_mask = BIT(15),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "smmu_ahb_clk",
1985 .ops = &clk_branch_ops,
1986 .flags = CLK_IS_ROOT,
1987 },
1988 },
1989};
1990
1991static struct clk_branch tv_enc_ahb_clk = {
1992 .halt_reg = 0x01dc,
1993 .halt_bit = 23,
1994 .clkr = {
1995 .enable_reg = 0x0008,
1996 .enable_mask = BIT(25),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "tv_enc_ahb_clk",
1999 .ops = &clk_branch_ops,
2000 .flags = CLK_IS_ROOT,
2001 },
2002 },
2003};
2004
2005static struct clk_branch vcodec_ahb_clk = {
2006 .hwcg_reg = 0x0038,
2007 .hwcg_bit = 26,
2008 .halt_reg = 0x01dc,
2009 .halt_bit = 12,
2010 .clkr = {
2011 .enable_reg = 0x0008,
2012 .enable_mask = BIT(11),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "vcodec_ahb_clk",
2015 .ops = &clk_branch_ops,
2016 .flags = CLK_IS_ROOT,
2017 },
2018 },
2019};
2020
2021static struct clk_branch vfe_ahb_clk = {
2022 .halt_reg = 0x01dc,
2023 .halt_bit = 14,
2024 .clkr = {
2025 .enable_reg = 0x0008,
2026 .enable_mask = BIT(13),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "vfe_ahb_clk",
2029 .ops = &clk_branch_ops,
2030 .flags = CLK_IS_ROOT,
2031 },
2032 },
2033};
2034
2035static struct clk_branch vpe_ahb_clk = {
2036 .halt_reg = 0x01dc,
2037 .halt_bit = 15,
2038 .clkr = {
2039 .enable_reg = 0x0008,
2040 .enable_mask = BIT(16),
2041 .hw.init = &(struct clk_init_data){
2042 .name = "vpe_ahb_clk",
2043 .ops = &clk_branch_ops,
2044 .flags = CLK_IS_ROOT,
2045 },
2046 },
2047};
2048
2049static struct clk_regmap *mmcc_msm8960_clks[] = {
2050 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2051 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2052 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2053 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2054 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2055 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2056 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2057 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2058 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2059 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2060 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2061 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2062 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2063 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2064 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2065 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2066 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2067 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2068 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2069 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2070 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2071 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2072 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2073 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2074 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2075 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2076 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2077 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2078 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2079 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2080 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2081 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2082 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2083 [CSI0_SRC] = &csi0_src.clkr,
2084 [CSI0_CLK] = &csi0_clk.clkr,
2085 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2086 [CSI1_SRC] = &csi1_src.clkr,
2087 [CSI1_CLK] = &csi1_clk.clkr,
2088 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2089 [CSI2_SRC] = &csi2_src.clkr,
2090 [CSI2_CLK] = &csi2_clk.clkr,
2091 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2092 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2093 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2094 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2095 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2096 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2097 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2098 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2099 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2100 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2101 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2102 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2103 [GFX3D_SRC] = &gfx3d_src.clkr,
2104 [GFX3D_CLK] = &gfx3d_clk.clkr,
2105 [IJPEG_SRC] = &ijpeg_src.clkr,
2106 [IJPEG_CLK] = &ijpeg_clk.clkr,
2107 [JPEGD_SRC] = &jpegd_src.clkr,
2108 [JPEGD_CLK] = &jpegd_clk.clkr,
2109 [MDP_SRC] = &mdp_src.clkr,
2110 [MDP_CLK] = &mdp_clk.clkr,
2111 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2112 [ROT_SRC] = &rot_src.clkr,
2113 [ROT_CLK] = &rot_clk.clkr,
2114 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2115 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2116 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2117 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2118 [TV_SRC] = &tv_src.clkr,
2119 [VCODEC_SRC] = &vcodec_src.clkr,
2120 [VCODEC_CLK] = &vcodec_clk.clkr,
2121 [VFE_SRC] = &vfe_src.clkr,
2122 [VFE_CLK] = &vfe_clk.clkr,
2123 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2124 [VPE_SRC] = &vpe_src.clkr,
2125 [VPE_CLK] = &vpe_clk.clkr,
2126 [CAMCLK0_SRC] = &camclk0_src.clkr,
2127 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2128 [CAMCLK1_SRC] = &camclk1_src.clkr,
2129 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2130 [CAMCLK2_SRC] = &camclk2_src.clkr,
2131 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2132 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2133 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2134 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2135 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2136 [PLL2] = &pll2.clkr,
2137};
2138
2139static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2140 [VPE_AXI_RESET] = { 0x0208, 15 },
2141 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2142 [MPD_AXI_RESET] = { 0x0208, 13 },
2143 [VFE_AXI_RESET] = { 0x0208, 9 },
2144 [SP_AXI_RESET] = { 0x0208, 8 },
2145 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2146 [ROT_AXI_RESET] = { 0x0208, 6 },
2147 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2148 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2149 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2150 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2151 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2152 [FAB_S0_AXI_RESET] = { 0x0208 },
2153 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2154 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2155 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2156 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2157 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2158 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2159 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2160 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2161 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2162 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2163 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2164 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2165 [APU_AHB_RESET] = { 0x020c, 18 },
2166 [CSI_AHB_RESET] = { 0x020c, 17 },
2167 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2168 [VPE_AHB_RESET] = { 0x020c, 14 },
2169 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2170 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2171 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2172 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2173 [HDMI_AHB_RESET] = { 0x020c, 9 },
2174 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2175 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2176 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2177 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2178 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2179 [MDP_AHB_RESET] = { 0x020c, 3 },
2180 [ROT_AHB_RESET] = { 0x020c, 2 },
2181 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2182 [VFE_AHB_RESET] = { 0x020c, 0 },
2183 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2184 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2185 [CSIPHY2_RESET] = { 0x0210, 29 },
2186 [CSI_PIX1_RESET] = { 0x0210, 28 },
2187 [CSIPHY0_RESET] = { 0x0210, 27 },
2188 [CSIPHY1_RESET] = { 0x0210, 26 },
2189 [DSI2_RESET] = { 0x0210, 25 },
2190 [VFE_CSI_RESET] = { 0x0210, 24 },
2191 [MDP_RESET] = { 0x0210, 21 },
2192 [AMP_RESET] = { 0x0210, 20 },
2193 [JPEGD_RESET] = { 0x0210, 19 },
2194 [CSI1_RESET] = { 0x0210, 18 },
2195 [VPE_RESET] = { 0x0210, 17 },
2196 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2197 [VFE_RESET] = { 0x0210, 15 },
2198 [GFX2D0_RESET] = { 0x0210, 14 },
2199 [GFX2D1_RESET] = { 0x0210, 13 },
2200 [GFX3D_RESET] = { 0x0210, 12 },
2201 [HDMI_RESET] = { 0x0210, 11 },
2202 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2203 [IJPEG_RESET] = { 0x0210, 9 },
2204 [CSI0_RESET] = { 0x0210, 8 },
2205 [DSI_RESET] = { 0x0210, 7 },
2206 [VCODEC_RESET] = { 0x0210, 6 },
2207 [MDP_TV_RESET] = { 0x0210, 4 },
2208 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2209 [ROT_RESET] = { 0x0210, 2 },
2210 [TV_HDMI_RESET] = { 0x0210, 1 },
2211 [TV_ENC_RESET] = { 0x0210 },
2212 [CSI2_RESET] = { 0x0214, 2 },
2213 [CSI_RDI1_RESET] = { 0x0214, 1 },
2214 [CSI_RDI2_RESET] = { 0x0214 },
2215};
2216
2217static const struct regmap_config mmcc_msm8960_regmap_config = {
2218 .reg_bits = 32,
2219 .reg_stride = 4,
2220 .val_bits = 32,
2221 .max_register = 0x334,
2222 .fast_io = true,
2223};
2224
2225static const struct of_device_id mmcc_msm8960_match_table[] = {
2226 { .compatible = "qcom,mmcc-msm8960" },
2227 { }
2228};
2229MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2230
2231struct qcom_cc {
2232 struct qcom_reset_controller reset;
2233 struct clk_onecell_data data;
2234 struct clk *clks[];
2235};
2236
2237static int mmcc_msm8960_probe(struct platform_device *pdev)
2238{
2239 void __iomem *base;
2240 struct resource *res;
2241 int i, ret;
2242 struct device *dev = &pdev->dev;
2243 struct clk *clk;
2244 struct clk_onecell_data *data;
2245 struct clk **clks;
2246 struct regmap *regmap;
2247 size_t num_clks;
2248 struct qcom_reset_controller *reset;
2249 struct qcom_cc *cc;
2250
2251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252 base = devm_ioremap_resource(dev, res);
2253 if (IS_ERR(base))
2254 return PTR_ERR(base);
2255
2256 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8960_regmap_config);
2257 if (IS_ERR(regmap))
2258 return PTR_ERR(regmap);
2259
2260 num_clks = ARRAY_SIZE(mmcc_msm8960_clks);
2261 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2262 GFP_KERNEL);
2263 if (!cc)
2264 return -ENOMEM;
2265
2266 clks = cc->clks;
2267 data = &cc->data;
2268 data->clks = clks;
2269 data->clk_num = num_clks;
2270
2271 for (i = 0; i < num_clks; i++) {
2272 if (!mmcc_msm8960_clks[i])
2273 continue;
2274 clk = devm_clk_register_regmap(dev, mmcc_msm8960_clks[i]);
2275 if (IS_ERR(clk))
2276 return PTR_ERR(clk);
2277 clks[i] = clk;
2278 }
2279
2280 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2281 if (ret)
2282 return ret;
2283
2284 reset = &cc->reset;
2285 reset->rcdev.of_node = dev->of_node;
2286 reset->rcdev.ops = &qcom_reset_ops,
2287 reset->rcdev.owner = THIS_MODULE,
2288 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2289 reset->regmap = regmap;
2290 reset->reset_map = mmcc_msm8960_resets,
2291 platform_set_drvdata(pdev, &reset->rcdev);
2292
2293 ret = reset_controller_register(&reset->rcdev);
2294 if (ret)
2295 of_clk_del_provider(dev->of_node);
2296
2297 return ret;
2298}
2299
2300static int mmcc_msm8960_remove(struct platform_device *pdev)
2301{
2302 of_clk_del_provider(pdev->dev.of_node);
2303 reset_controller_unregister(platform_get_drvdata(pdev));
2304 return 0;
2305}
2306
2307static struct platform_driver mmcc_msm8960_driver = {
2308 .probe = mmcc_msm8960_probe,
2309 .remove = mmcc_msm8960_remove,
2310 .driver = {
2311 .name = "mmcc-msm8960",
2312 .owner = THIS_MODULE,
2313 .of_match_table = mmcc_msm8960_match_table,
2314 },
2315};
2316
2317module_platform_driver(mmcc_msm8960_driver);
2318
2319MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2320MODULE_LICENSE("GPL v2");
2321MODULE_ALIAS("platform:mmcc-msm8960");
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
new file mode 100644
index 000000000000..c95774514b81
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -0,0 +1,2625 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
26#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define P_XO 0
35#define P_MMPLL0 1
36#define P_EDPLINK 1
37#define P_MMPLL1 2
38#define P_HDMIPLL 2
39#define P_GPLL0 3
40#define P_EDPVCO 3
41#define P_GPLL1 4
42#define P_DSI0PLL 4
43#define P_MMPLL2 4
44#define P_MMPLL3 4
45#define P_DSI1PLL 5
46
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
48 [P_XO] = 0,
49 [P_MMPLL0] = 1,
50 [P_MMPLL1] = 2,
51 [P_GPLL0] = 5,
52};
53
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
55 "xo",
56 "mmpll0_vote",
57 "mmpll1_vote",
58 "mmss_gpll0_vote",
59};
60
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0,
63 [P_MMPLL0] = 1,
64 [P_HDMIPLL] = 4,
65 [P_GPLL0] = 5,
66 [P_DSI0PLL] = 2,
67 [P_DSI1PLL] = 3,
68};
69
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
71 "xo",
72 "mmpll0_vote",
73 "hdmipll",
74 "mmss_gpll0_vote",
75 "dsi0pll",
76 "dsi1pll",
77};
78
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0,
81 [P_MMPLL0] = 1,
82 [P_MMPLL1] = 2,
83 [P_GPLL0] = 5,
84 [P_MMPLL2] = 3,
85};
86
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
88 "xo",
89 "mmpll0_vote",
90 "mmpll1_vote",
91 "mmss_gpll0_vote",
92 "mmpll2",
93};
94
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0,
97 [P_MMPLL0] = 1,
98 [P_MMPLL1] = 2,
99 [P_GPLL0] = 5,
100 [P_MMPLL3] = 3,
101};
102
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
104 "xo",
105 "mmpll0_vote",
106 "mmpll1_vote",
107 "mmss_gpll0_vote",
108 "mmpll3",
109};
110
111static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
112 [P_XO] = 0,
113 [P_MMPLL0] = 1,
114 [P_MMPLL1] = 2,
115 [P_GPLL0] = 5,
116 [P_GPLL1] = 4,
117};
118
119static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
120 "xo",
121 "mmpll0_vote",
122 "mmpll1_vote",
123 "mmss_gpll0_vote",
124 "gpll1_vote",
125};
126
127static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
128 [P_XO] = 0,
129 [P_EDPLINK] = 4,
130 [P_HDMIPLL] = 3,
131 [P_EDPVCO] = 5,
132 [P_DSI0PLL] = 1,
133 [P_DSI1PLL] = 2,
134};
135
136static const char *mmcc_xo_dsi_hdmi_edp[] = {
137 "xo",
138 "edp_link_clk",
139 "hdmipll",
140 "edp_vco_div",
141 "dsi0pll",
142 "dsi1pll",
143};
144
145static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
146 [P_XO] = 0,
147 [P_EDPLINK] = 4,
148 [P_HDMIPLL] = 3,
149 [P_GPLL0] = 5,
150 [P_DSI0PLL] = 1,
151 [P_DSI1PLL] = 2,
152};
153
154static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
155 "xo",
156 "edp_link_clk",
157 "hdmipll",
158 "gpll0_vote",
159 "dsi0pll",
160 "dsi1pll",
161};
162
163#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
164
165static struct clk_pll mmpll0 = {
166 .l_reg = 0x0004,
167 .m_reg = 0x0008,
168 .n_reg = 0x000c,
169 .config_reg = 0x0014,
170 .mode_reg = 0x0000,
171 .status_reg = 0x001c,
172 .clkr.hw.init = &(struct clk_init_data){
173 .name = "mmpll0",
174 .parent_names = (const char *[]){ "xo" },
175 .num_parents = 1,
176 .ops = &clk_pll_ops,
177 },
178};
179
180static struct clk_regmap mmpll0_vote = {
181 .enable_reg = 0x0100,
182 .enable_mask = BIT(0),
183 .hw.init = &(struct clk_init_data){
184 .name = "mmpll0_vote",
185 .parent_names = (const char *[]){ "mmpll0" },
186 .num_parents = 1,
187 .ops = &clk_pll_vote_ops,
188 },
189};
190
191static struct clk_pll mmpll1 = {
192 .l_reg = 0x0044,
193 .m_reg = 0x0048,
194 .n_reg = 0x004c,
195 .config_reg = 0x0054,
196 .mode_reg = 0x0040,
197 .status_reg = 0x005c,
198 .clkr.hw.init = &(struct clk_init_data){
199 .name = "mmpll1",
200 .parent_names = (const char *[]){ "xo" },
201 .num_parents = 1,
202 .ops = &clk_pll_ops,
203 },
204};
205
206static struct clk_regmap mmpll1_vote = {
207 .enable_reg = 0x0100,
208 .enable_mask = BIT(1),
209 .hw.init = &(struct clk_init_data){
210 .name = "mmpll1_vote",
211 .parent_names = (const char *[]){ "mmpll1" },
212 .num_parents = 1,
213 .ops = &clk_pll_vote_ops,
214 },
215};
216
217static struct clk_pll mmpll2 = {
218 .l_reg = 0x4104,
219 .m_reg = 0x4108,
220 .n_reg = 0x410c,
221 .config_reg = 0x4114,
222 .mode_reg = 0x4100,
223 .status_reg = 0x411c,
224 .clkr.hw.init = &(struct clk_init_data){
225 .name = "mmpll2",
226 .parent_names = (const char *[]){ "xo" },
227 .num_parents = 1,
228 .ops = &clk_pll_ops,
229 },
230};
231
232static struct clk_pll mmpll3 = {
233 .l_reg = 0x0084,
234 .m_reg = 0x0088,
235 .n_reg = 0x008c,
236 .config_reg = 0x0094,
237 .mode_reg = 0x0080,
238 .status_reg = 0x009c,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "mmpll3",
241 .parent_names = (const char *[]){ "xo" },
242 .num_parents = 1,
243 .ops = &clk_pll_ops,
244 },
245};
246
247static struct clk_rcg2 mmss_ahb_clk_src = {
248 .cmd_rcgr = 0x5000,
249 .hid_width = 5,
250 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "mmss_ahb_clk_src",
253 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
254 .num_parents = 4,
255 .ops = &clk_rcg2_ops,
256 },
257};
258
259static struct freq_tbl ftbl_mmss_axi_clk[] = {
260 F( 19200000, P_XO, 1, 0, 0),
261 F( 37500000, P_GPLL0, 16, 0, 0),
262 F( 50000000, P_GPLL0, 12, 0, 0),
263 F( 75000000, P_GPLL0, 8, 0, 0),
264 F(100000000, P_GPLL0, 6, 0, 0),
265 F(150000000, P_GPLL0, 4, 0, 0),
266 F(291750000, P_MMPLL1, 4, 0, 0),
267 F(400000000, P_MMPLL0, 2, 0, 0),
268 F(466800000, P_MMPLL1, 2.5, 0, 0),
269};
270
271static struct clk_rcg2 mmss_axi_clk_src = {
272 .cmd_rcgr = 0x5040,
273 .hid_width = 5,
274 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
275 .freq_tbl = ftbl_mmss_axi_clk,
276 .clkr.hw.init = &(struct clk_init_data){
277 .name = "mmss_axi_clk_src",
278 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
279 .num_parents = 4,
280 .ops = &clk_rcg2_ops,
281 },
282};
283
284static struct freq_tbl ftbl_ocmemnoc_clk[] = {
285 F( 19200000, P_XO, 1, 0, 0),
286 F( 37500000, P_GPLL0, 16, 0, 0),
287 F( 50000000, P_GPLL0, 12, 0, 0),
288 F( 75000000, P_GPLL0, 8, 0, 0),
289 F(100000000, P_GPLL0, 6, 0, 0),
290 F(150000000, P_GPLL0, 4, 0, 0),
291 F(291750000, P_MMPLL1, 4, 0, 0),
292 F(400000000, P_MMPLL0, 2, 0, 0),
293};
294
295static struct clk_rcg2 ocmemnoc_clk_src = {
296 .cmd_rcgr = 0x5090,
297 .hid_width = 5,
298 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
299 .freq_tbl = ftbl_ocmemnoc_clk,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "ocmemnoc_clk_src",
302 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
303 .num_parents = 4,
304 .ops = &clk_rcg2_ops,
305 },
306};
307
308static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
309 F(100000000, P_GPLL0, 6, 0, 0),
310 F(200000000, P_MMPLL0, 4, 0, 0),
311 { }
312};
313
314static struct clk_rcg2 csi0_clk_src = {
315 .cmd_rcgr = 0x3090,
316 .hid_width = 5,
317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
318 .freq_tbl = ftbl_camss_csi0_3_clk,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "csi0_clk_src",
321 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
322 .num_parents = 4,
323 .ops = &clk_rcg2_ops,
324 },
325};
326
327static struct clk_rcg2 csi1_clk_src = {
328 .cmd_rcgr = 0x3100,
329 .hid_width = 5,
330 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
331 .freq_tbl = ftbl_camss_csi0_3_clk,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "csi1_clk_src",
334 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
335 .num_parents = 4,
336 .ops = &clk_rcg2_ops,
337 },
338};
339
340static struct clk_rcg2 csi2_clk_src = {
341 .cmd_rcgr = 0x3160,
342 .hid_width = 5,
343 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
344 .freq_tbl = ftbl_camss_csi0_3_clk,
345 .clkr.hw.init = &(struct clk_init_data){
346 .name = "csi2_clk_src",
347 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
348 .num_parents = 4,
349 .ops = &clk_rcg2_ops,
350 },
351};
352
353static struct clk_rcg2 csi3_clk_src = {
354 .cmd_rcgr = 0x31c0,
355 .hid_width = 5,
356 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
357 .freq_tbl = ftbl_camss_csi0_3_clk,
358 .clkr.hw.init = &(struct clk_init_data){
359 .name = "csi3_clk_src",
360 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
361 .num_parents = 4,
362 .ops = &clk_rcg2_ops,
363 },
364};
365
366static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
367 F(37500000, P_GPLL0, 16, 0, 0),
368 F(50000000, P_GPLL0, 12, 0, 0),
369 F(60000000, P_GPLL0, 10, 0, 0),
370 F(80000000, P_GPLL0, 7.5, 0, 0),
371 F(100000000, P_GPLL0, 6, 0, 0),
372 F(109090000, P_GPLL0, 5.5, 0, 0),
373 F(133330000, P_GPLL0, 4.5, 0, 0),
374 F(200000000, P_GPLL0, 3, 0, 0),
375 F(228570000, P_MMPLL0, 3.5, 0, 0),
376 F(266670000, P_MMPLL0, 3, 0, 0),
377 F(320000000, P_MMPLL0, 2.5, 0, 0),
378 F(400000000, P_MMPLL0, 2, 0, 0),
379 F(465000000, P_MMPLL3, 2, 0, 0),
380 { }
381};
382
383static struct clk_rcg2 vfe0_clk_src = {
384 .cmd_rcgr = 0x3600,
385 .hid_width = 5,
386 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
387 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
388 .clkr.hw.init = &(struct clk_init_data){
389 .name = "vfe0_clk_src",
390 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
391 .num_parents = 4,
392 .ops = &clk_rcg2_ops,
393 },
394};
395
396static struct clk_rcg2 vfe1_clk_src = {
397 .cmd_rcgr = 0x3620,
398 .hid_width = 5,
399 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
400 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
401 .clkr.hw.init = &(struct clk_init_data){
402 .name = "vfe1_clk_src",
403 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
404 .num_parents = 4,
405 .ops = &clk_rcg2_ops,
406 },
407};
408
409static struct freq_tbl ftbl_mdss_mdp_clk[] = {
410 F(37500000, P_GPLL0, 16, 0, 0),
411 F(60000000, P_GPLL0, 10, 0, 0),
412 F(75000000, P_GPLL0, 8, 0, 0),
413 F(85710000, P_GPLL0, 7, 0, 0),
414 F(100000000, P_GPLL0, 6, 0, 0),
415 F(133330000, P_MMPLL0, 6, 0, 0),
416 F(160000000, P_MMPLL0, 5, 0, 0),
417 F(200000000, P_MMPLL0, 4, 0, 0),
418 F(228570000, P_MMPLL0, 3.5, 0, 0),
419 F(240000000, P_GPLL0, 2.5, 0, 0),
420 F(266670000, P_MMPLL0, 3, 0, 0),
421 F(320000000, P_MMPLL0, 2.5, 0, 0),
422 { }
423};
424
425static struct clk_rcg2 mdp_clk_src = {
426 .cmd_rcgr = 0x2040,
427 .hid_width = 5,
428 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
429 .freq_tbl = ftbl_mdss_mdp_clk,
430 .clkr.hw.init = &(struct clk_init_data){
431 .name = "mdp_clk_src",
432 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
433 .num_parents = 6,
434 .ops = &clk_rcg2_ops,
435 },
436};
437
438static struct clk_rcg2 gfx3d_clk_src = {
439 .cmd_rcgr = 0x4000,
440 .hid_width = 5,
441 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
442 .clkr.hw.init = &(struct clk_init_data){
443 .name = "gfx3d_clk_src",
444 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
445 .num_parents = 5,
446 .ops = &clk_rcg2_ops,
447 },
448};
449
450static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
451 F(75000000, P_GPLL0, 8, 0, 0),
452 F(133330000, P_GPLL0, 4.5, 0, 0),
453 F(200000000, P_GPLL0, 3, 0, 0),
454 F(228570000, P_MMPLL0, 3.5, 0, 0),
455 F(266670000, P_MMPLL0, 3, 0, 0),
456 F(320000000, P_MMPLL0, 2.5, 0, 0),
457 { }
458};
459
460static struct clk_rcg2 jpeg0_clk_src = {
461 .cmd_rcgr = 0x3500,
462 .hid_width = 5,
463 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
464 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
465 .clkr.hw.init = &(struct clk_init_data){
466 .name = "jpeg0_clk_src",
467 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
468 .num_parents = 4,
469 .ops = &clk_rcg2_ops,
470 },
471};
472
473static struct clk_rcg2 jpeg1_clk_src = {
474 .cmd_rcgr = 0x3520,
475 .hid_width = 5,
476 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
477 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "jpeg1_clk_src",
480 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
481 .num_parents = 4,
482 .ops = &clk_rcg2_ops,
483 },
484};
485
486static struct clk_rcg2 jpeg2_clk_src = {
487 .cmd_rcgr = 0x3540,
488 .hid_width = 5,
489 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
490 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "jpeg2_clk_src",
493 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
494 .num_parents = 4,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
500 F(125000000, P_DSI0PLL, 2, 0, 0),
501 F(250000000, P_DSI0PLL, 1, 0, 0),
502 { }
503};
504
505static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
506 F(125000000, P_DSI1PLL, 2, 0, 0),
507 F(250000000, P_DSI1PLL, 1, 0, 0),
508 { }
509};
510
511static struct clk_rcg2 pclk0_clk_src = {
512 .cmd_rcgr = 0x2000,
513 .mnd_width = 8,
514 .hid_width = 5,
515 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
516 .freq_tbl = ftbl_mdss_pclk0_clk,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "pclk0_clk_src",
519 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
520 .num_parents = 6,
521 .ops = &clk_rcg2_ops,
522 },
523};
524
525static struct clk_rcg2 pclk1_clk_src = {
526 .cmd_rcgr = 0x2020,
527 .mnd_width = 8,
528 .hid_width = 5,
529 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
530 .freq_tbl = ftbl_mdss_pclk1_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "pclk1_clk_src",
533 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
534 .num_parents = 6,
535 .ops = &clk_rcg2_ops,
536 },
537};
538
539static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
540 F(50000000, P_GPLL0, 12, 0, 0),
541 F(100000000, P_GPLL0, 6, 0, 0),
542 F(133330000, P_MMPLL0, 6, 0, 0),
543 F(200000000, P_MMPLL0, 4, 0, 0),
544 F(266670000, P_MMPLL0, 3, 0, 0),
545 F(465000000, P_MMPLL3, 2, 0, 0),
546 { }
547};
548
549static struct clk_rcg2 vcodec0_clk_src = {
550 .cmd_rcgr = 0x1000,
551 .mnd_width = 8,
552 .hid_width = 5,
553 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
554 .freq_tbl = ftbl_venus0_vcodec0_clk,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "vcodec0_clk_src",
557 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
558 .num_parents = 5,
559 .ops = &clk_rcg2_ops,
560 },
561};
562
563static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
564 F(19200000, P_XO, 1, 0, 0),
565 { }
566};
567
568static struct clk_rcg2 cci_clk_src = {
569 .cmd_rcgr = 0x3300,
570 .hid_width = 5,
571 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
572 .freq_tbl = ftbl_camss_cci_cci_clk,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "cci_clk_src",
575 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
576 .num_parents = 4,
577 .ops = &clk_rcg2_ops,
578 },
579};
580
581static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
582 F(10000, P_XO, 16, 1, 120),
583 F(24000, P_XO, 16, 1, 50),
584 F(6000000, P_GPLL0, 10, 1, 10),
585 F(12000000, P_GPLL0, 10, 1, 5),
586 F(13000000, P_GPLL0, 4, 13, 150),
587 F(24000000, P_GPLL0, 5, 1, 5),
588 { }
589};
590
591static struct clk_rcg2 camss_gp0_clk_src = {
592 .cmd_rcgr = 0x3420,
593 .mnd_width = 8,
594 .hid_width = 5,
595 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
596 .freq_tbl = ftbl_camss_gp0_1_clk,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "camss_gp0_clk_src",
599 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
600 .num_parents = 5,
601 .ops = &clk_rcg2_ops,
602 },
603};
604
605static struct clk_rcg2 camss_gp1_clk_src = {
606 .cmd_rcgr = 0x3450,
607 .mnd_width = 8,
608 .hid_width = 5,
609 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
610 .freq_tbl = ftbl_camss_gp0_1_clk,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "camss_gp1_clk_src",
613 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
614 .num_parents = 5,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
620 F(4800000, P_XO, 4, 0, 0),
621 F(6000000, P_GPLL0, 10, 1, 10),
622 F(8000000, P_GPLL0, 15, 1, 5),
623 F(9600000, P_XO, 2, 0, 0),
624 F(16000000, P_GPLL0, 12.5, 1, 3),
625 F(19200000, P_XO, 1, 0, 0),
626 F(24000000, P_GPLL0, 5, 1, 5),
627 F(32000000, P_MMPLL0, 5, 1, 5),
628 F(48000000, P_GPLL0, 12.5, 0, 0),
629 F(64000000, P_MMPLL0, 12.5, 0, 0),
630 F(66670000, P_GPLL0, 9, 0, 0),
631 { }
632};
633
634static struct clk_rcg2 mclk0_clk_src = {
635 .cmd_rcgr = 0x3360,
636 .hid_width = 5,
637 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
638 .freq_tbl = ftbl_camss_mclk0_3_clk,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "mclk0_clk_src",
641 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
642 .num_parents = 4,
643 .ops = &clk_rcg2_ops,
644 },
645};
646
647static struct clk_rcg2 mclk1_clk_src = {
648 .cmd_rcgr = 0x3390,
649 .hid_width = 5,
650 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
651 .freq_tbl = ftbl_camss_mclk0_3_clk,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "mclk1_clk_src",
654 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
655 .num_parents = 4,
656 .ops = &clk_rcg2_ops,
657 },
658};
659
660static struct clk_rcg2 mclk2_clk_src = {
661 .cmd_rcgr = 0x33c0,
662 .hid_width = 5,
663 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
664 .freq_tbl = ftbl_camss_mclk0_3_clk,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "mclk2_clk_src",
667 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
668 .num_parents = 4,
669 .ops = &clk_rcg2_ops,
670 },
671};
672
673static struct clk_rcg2 mclk3_clk_src = {
674 .cmd_rcgr = 0x33f0,
675 .hid_width = 5,
676 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
677 .freq_tbl = ftbl_camss_mclk0_3_clk,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "mclk3_clk_src",
680 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
681 .num_parents = 4,
682 .ops = &clk_rcg2_ops,
683 },
684};
685
686static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
687 F(100000000, P_GPLL0, 6, 0, 0),
688 F(200000000, P_MMPLL0, 4, 0, 0),
689 { }
690};
691
692static struct clk_rcg2 csi0phytimer_clk_src = {
693 .cmd_rcgr = 0x3000,
694 .hid_width = 5,
695 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
696 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "csi0phytimer_clk_src",
699 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
700 .num_parents = 4,
701 .ops = &clk_rcg2_ops,
702 },
703};
704
705static struct clk_rcg2 csi1phytimer_clk_src = {
706 .cmd_rcgr = 0x3030,
707 .hid_width = 5,
708 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
709 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
710 .clkr.hw.init = &(struct clk_init_data){
711 .name = "csi1phytimer_clk_src",
712 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
713 .num_parents = 4,
714 .ops = &clk_rcg2_ops,
715 },
716};
717
718static struct clk_rcg2 csi2phytimer_clk_src = {
719 .cmd_rcgr = 0x3060,
720 .hid_width = 5,
721 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
722 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "csi2phytimer_clk_src",
725 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
726 .num_parents = 4,
727 .ops = &clk_rcg2_ops,
728 },
729};
730
731static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
732 F(133330000, P_GPLL0, 4.5, 0, 0),
733 F(266670000, P_MMPLL0, 3, 0, 0),
734 F(320000000, P_MMPLL0, 2.5, 0, 0),
735 F(400000000, P_MMPLL0, 2, 0, 0),
736 F(465000000, P_MMPLL3, 2, 0, 0),
737 { }
738};
739
740static struct clk_rcg2 cpp_clk_src = {
741 .cmd_rcgr = 0x3640,
742 .hid_width = 5,
743 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
744 .freq_tbl = ftbl_camss_vfe_cpp_clk,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "cpp_clk_src",
747 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
748 .num_parents = 4,
749 .ops = &clk_rcg2_ops,
750 },
751};
752
753static struct freq_tbl ftbl_mdss_byte0_clk[] = {
754 F(93750000, P_DSI0PLL, 8, 0, 0),
755 F(187500000, P_DSI0PLL, 4, 0, 0),
756 { }
757};
758
759static struct freq_tbl ftbl_mdss_byte1_clk[] = {
760 F(93750000, P_DSI1PLL, 8, 0, 0),
761 F(187500000, P_DSI1PLL, 4, 0, 0),
762 { }
763};
764
765static struct clk_rcg2 byte0_clk_src = {
766 .cmd_rcgr = 0x2120,
767 .hid_width = 5,
768 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
769 .freq_tbl = ftbl_mdss_byte0_clk,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "byte0_clk_src",
772 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
773 .num_parents = 6,
774 .ops = &clk_rcg2_ops,
775 },
776};
777
778static struct clk_rcg2 byte1_clk_src = {
779 .cmd_rcgr = 0x2140,
780 .hid_width = 5,
781 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
782 .freq_tbl = ftbl_mdss_byte1_clk,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "byte1_clk_src",
785 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
786 .num_parents = 6,
787 .ops = &clk_rcg2_ops,
788 },
789};
790
791static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
792 F(19200000, P_XO, 1, 0, 0),
793 { }
794};
795
796static struct clk_rcg2 edpaux_clk_src = {
797 .cmd_rcgr = 0x20e0,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
800 .freq_tbl = ftbl_mdss_edpaux_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "edpaux_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct freq_tbl ftbl_mdss_edplink_clk[] = {
810 F(135000000, P_EDPLINK, 2, 0, 0),
811 F(270000000, P_EDPLINK, 11, 0, 0),
812 { }
813};
814
815static struct clk_rcg2 edplink_clk_src = {
816 .cmd_rcgr = 0x20c0,
817 .hid_width = 5,
818 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
819 .freq_tbl = ftbl_mdss_edplink_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "edplink_clk_src",
822 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
823 .num_parents = 6,
824 .ops = &clk_rcg2_ops,
825 },
826};
827
828static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
829 F(175000000, P_EDPVCO, 2, 0, 0),
830 F(350000000, P_EDPVCO, 11, 0, 0),
831 { }
832};
833
834static struct clk_rcg2 edppixel_clk_src = {
835 .cmd_rcgr = 0x20a0,
836 .mnd_width = 8,
837 .hid_width = 5,
838 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
839 .freq_tbl = ftbl_mdss_edppixel_clk,
840 .clkr.hw.init = &(struct clk_init_data){
841 .name = "edppixel_clk_src",
842 .parent_names = mmcc_xo_dsi_hdmi_edp,
843 .num_parents = 6,
844 .ops = &clk_rcg2_ops,
845 },
846};
847
848static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
849 F(19200000, P_XO, 1, 0, 0),
850 { }
851};
852
853static struct clk_rcg2 esc0_clk_src = {
854 .cmd_rcgr = 0x2160,
855 .hid_width = 5,
856 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
857 .freq_tbl = ftbl_mdss_esc0_1_clk,
858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "esc0_clk_src",
860 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
861 .num_parents = 6,
862 .ops = &clk_rcg2_ops,
863 },
864};
865
866static struct clk_rcg2 esc1_clk_src = {
867 .cmd_rcgr = 0x2180,
868 .hid_width = 5,
869 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
870 .freq_tbl = ftbl_mdss_esc0_1_clk,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "esc1_clk_src",
873 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
874 .num_parents = 6,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
880 F(25200000, P_HDMIPLL, 1, 0, 0),
881 F(27000000, P_HDMIPLL, 1, 0, 0),
882 F(27030000, P_HDMIPLL, 1, 0, 0),
883 F(65000000, P_HDMIPLL, 1, 0, 0),
884 F(74250000, P_HDMIPLL, 1, 0, 0),
885 F(108000000, P_HDMIPLL, 1, 0, 0),
886 F(148500000, P_HDMIPLL, 1, 0, 0),
887 F(268500000, P_HDMIPLL, 1, 0, 0),
888 F(297000000, P_HDMIPLL, 1, 0, 0),
889 { }
890};
891
892static struct clk_rcg2 extpclk_clk_src = {
893 .cmd_rcgr = 0x2060,
894 .hid_width = 5,
895 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
896 .freq_tbl = ftbl_mdss_extpclk_clk,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "extpclk_clk_src",
899 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
900 .num_parents = 6,
901 .ops = &clk_rcg2_ops,
902 },
903};
904
905static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
906 F(19200000, P_XO, 1, 0, 0),
907 { }
908};
909
910static struct clk_rcg2 hdmi_clk_src = {
911 .cmd_rcgr = 0x2100,
912 .hid_width = 5,
913 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
914 .freq_tbl = ftbl_mdss_hdmi_clk,
915 .clkr.hw.init = &(struct clk_init_data){
916 .name = "hdmi_clk_src",
917 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
918 .num_parents = 4,
919 .ops = &clk_rcg2_ops,
920 },
921};
922
923static struct freq_tbl ftbl_mdss_vsync_clk[] = {
924 F(19200000, P_XO, 1, 0, 0),
925 { }
926};
927
928static struct clk_rcg2 vsync_clk_src = {
929 .cmd_rcgr = 0x2080,
930 .hid_width = 5,
931 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
932 .freq_tbl = ftbl_mdss_vsync_clk,
933 .clkr.hw.init = &(struct clk_init_data){
934 .name = "vsync_clk_src",
935 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
936 .num_parents = 4,
937 .ops = &clk_rcg2_ops,
938 },
939};
940
941static struct clk_branch camss_cci_cci_ahb_clk = {
942 .halt_reg = 0x3348,
943 .clkr = {
944 .enable_reg = 0x3348,
945 .enable_mask = BIT(0),
946 .hw.init = &(struct clk_init_data){
947 .name = "camss_cci_cci_ahb_clk",
948 .parent_names = (const char *[]){
949 "mmss_ahb_clk_src",
950 },
951 .num_parents = 1,
952 .ops = &clk_branch2_ops,
953 },
954 },
955};
956
957static struct clk_branch camss_cci_cci_clk = {
958 .halt_reg = 0x3344,
959 .clkr = {
960 .enable_reg = 0x3344,
961 .enable_mask = BIT(0),
962 .hw.init = &(struct clk_init_data){
963 .name = "camss_cci_cci_clk",
964 .parent_names = (const char *[]){
965 "cci_clk_src",
966 },
967 .num_parents = 1,
968 .flags = CLK_SET_RATE_PARENT,
969 .ops = &clk_branch2_ops,
970 },
971 },
972};
973
974static struct clk_branch camss_csi0_ahb_clk = {
975 .halt_reg = 0x30bc,
976 .clkr = {
977 .enable_reg = 0x30bc,
978 .enable_mask = BIT(0),
979 .hw.init = &(struct clk_init_data){
980 .name = "camss_csi0_ahb_clk",
981 .parent_names = (const char *[]){
982 "mmss_ahb_clk_src",
983 },
984 .num_parents = 1,
985 .ops = &clk_branch2_ops,
986 },
987 },
988};
989
990static struct clk_branch camss_csi0_clk = {
991 .halt_reg = 0x30b4,
992 .clkr = {
993 .enable_reg = 0x30b4,
994 .enable_mask = BIT(0),
995 .hw.init = &(struct clk_init_data){
996 .name = "camss_csi0_clk",
997 .parent_names = (const char *[]){
998 "csi0_clk_src",
999 },
1000 .num_parents = 1,
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_branch2_ops,
1003 },
1004 },
1005};
1006
1007static struct clk_branch camss_csi0phy_clk = {
1008 .halt_reg = 0x30c4,
1009 .clkr = {
1010 .enable_reg = 0x30c4,
1011 .enable_mask = BIT(0),
1012 .hw.init = &(struct clk_init_data){
1013 .name = "camss_csi0phy_clk",
1014 .parent_names = (const char *[]){
1015 "csi0_clk_src",
1016 },
1017 .num_parents = 1,
1018 .flags = CLK_SET_RATE_PARENT,
1019 .ops = &clk_branch2_ops,
1020 },
1021 },
1022};
1023
1024static struct clk_branch camss_csi0pix_clk = {
1025 .halt_reg = 0x30e4,
1026 .clkr = {
1027 .enable_reg = 0x30e4,
1028 .enable_mask = BIT(0),
1029 .hw.init = &(struct clk_init_data){
1030 .name = "camss_csi0pix_clk",
1031 .parent_names = (const char *[]){
1032 "csi0_clk_src",
1033 },
1034 .num_parents = 1,
1035 .flags = CLK_SET_RATE_PARENT,
1036 .ops = &clk_branch2_ops,
1037 },
1038 },
1039};
1040
1041static struct clk_branch camss_csi0rdi_clk = {
1042 .halt_reg = 0x30d4,
1043 .clkr = {
1044 .enable_reg = 0x30d4,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "camss_csi0rdi_clk",
1048 .parent_names = (const char *[]){
1049 "csi0_clk_src",
1050 },
1051 .num_parents = 1,
1052 .flags = CLK_SET_RATE_PARENT,
1053 .ops = &clk_branch2_ops,
1054 },
1055 },
1056};
1057
1058static struct clk_branch camss_csi1_ahb_clk = {
1059 .halt_reg = 0x3128,
1060 .clkr = {
1061 .enable_reg = 0x3128,
1062 .enable_mask = BIT(0),
1063 .hw.init = &(struct clk_init_data){
1064 .name = "camss_csi1_ahb_clk",
1065 .parent_names = (const char *[]){
1066 "mmss_ahb_clk_src",
1067 },
1068 .num_parents = 1,
1069 .ops = &clk_branch2_ops,
1070 },
1071 },
1072};
1073
1074static struct clk_branch camss_csi1_clk = {
1075 .halt_reg = 0x3124,
1076 .clkr = {
1077 .enable_reg = 0x3124,
1078 .enable_mask = BIT(0),
1079 .hw.init = &(struct clk_init_data){
1080 .name = "camss_csi1_clk",
1081 .parent_names = (const char *[]){
1082 "csi1_clk_src",
1083 },
1084 .num_parents = 1,
1085 .flags = CLK_SET_RATE_PARENT,
1086 .ops = &clk_branch2_ops,
1087 },
1088 },
1089};
1090
1091static struct clk_branch camss_csi1phy_clk = {
1092 .halt_reg = 0x3134,
1093 .clkr = {
1094 .enable_reg = 0x3134,
1095 .enable_mask = BIT(0),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "camss_csi1phy_clk",
1098 .parent_names = (const char *[]){
1099 "csi1_clk_src",
1100 },
1101 .num_parents = 1,
1102 .flags = CLK_SET_RATE_PARENT,
1103 .ops = &clk_branch2_ops,
1104 },
1105 },
1106};
1107
1108static struct clk_branch camss_csi1pix_clk = {
1109 .halt_reg = 0x3154,
1110 .clkr = {
1111 .enable_reg = 0x3154,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "camss_csi1pix_clk",
1115 .parent_names = (const char *[]){
1116 "csi1_clk_src",
1117 },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123};
1124
1125static struct clk_branch camss_csi1rdi_clk = {
1126 .halt_reg = 0x3144,
1127 .clkr = {
1128 .enable_reg = 0x3144,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "camss_csi1rdi_clk",
1132 .parent_names = (const char *[]){
1133 "csi1_clk_src",
1134 },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140};
1141
1142static struct clk_branch camss_csi2_ahb_clk = {
1143 .halt_reg = 0x3188,
1144 .clkr = {
1145 .enable_reg = 0x3188,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "camss_csi2_ahb_clk",
1149 .parent_names = (const char *[]){
1150 "mmss_ahb_clk_src",
1151 },
1152 .num_parents = 1,
1153 .ops = &clk_branch2_ops,
1154 },
1155 },
1156};
1157
1158static struct clk_branch camss_csi2_clk = {
1159 .halt_reg = 0x3184,
1160 .clkr = {
1161 .enable_reg = 0x3184,
1162 .enable_mask = BIT(0),
1163 .hw.init = &(struct clk_init_data){
1164 .name = "camss_csi2_clk",
1165 .parent_names = (const char *[]){
1166 "csi2_clk_src",
1167 },
1168 .num_parents = 1,
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1171 },
1172 },
1173};
1174
1175static struct clk_branch camss_csi2phy_clk = {
1176 .halt_reg = 0x3194,
1177 .clkr = {
1178 .enable_reg = 0x3194,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "camss_csi2phy_clk",
1182 .parent_names = (const char *[]){
1183 "csi2_clk_src",
1184 },
1185 .num_parents = 1,
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1188 },
1189 },
1190};
1191
1192static struct clk_branch camss_csi2pix_clk = {
1193 .halt_reg = 0x31b4,
1194 .clkr = {
1195 .enable_reg = 0x31b4,
1196 .enable_mask = BIT(0),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "camss_csi2pix_clk",
1199 .parent_names = (const char *[]){
1200 "csi2_clk_src",
1201 },
1202 .num_parents = 1,
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207};
1208
1209static struct clk_branch camss_csi2rdi_clk = {
1210 .halt_reg = 0x31a4,
1211 .clkr = {
1212 .enable_reg = 0x31a4,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_csi2rdi_clk",
1216 .parent_names = (const char *[]){
1217 "csi2_clk_src",
1218 },
1219 .num_parents = 1,
1220 .flags = CLK_SET_RATE_PARENT,
1221 .ops = &clk_branch2_ops,
1222 },
1223 },
1224};
1225
1226static struct clk_branch camss_csi3_ahb_clk = {
1227 .halt_reg = 0x31e8,
1228 .clkr = {
1229 .enable_reg = 0x31e8,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "camss_csi3_ahb_clk",
1233 .parent_names = (const char *[]){
1234 "mmss_ahb_clk_src",
1235 },
1236 .num_parents = 1,
1237 .ops = &clk_branch2_ops,
1238 },
1239 },
1240};
1241
1242static struct clk_branch camss_csi3_clk = {
1243 .halt_reg = 0x31e4,
1244 .clkr = {
1245 .enable_reg = 0x31e4,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "camss_csi3_clk",
1249 .parent_names = (const char *[]){
1250 "csi3_clk_src",
1251 },
1252 .num_parents = 1,
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_branch2_ops,
1255 },
1256 },
1257};
1258
1259static struct clk_branch camss_csi3phy_clk = {
1260 .halt_reg = 0x31f4,
1261 .clkr = {
1262 .enable_reg = 0x31f4,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "camss_csi3phy_clk",
1266 .parent_names = (const char *[]){
1267 "csi3_clk_src",
1268 },
1269 .num_parents = 1,
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1272 },
1273 },
1274};
1275
1276static struct clk_branch camss_csi3pix_clk = {
1277 .halt_reg = 0x3214,
1278 .clkr = {
1279 .enable_reg = 0x3214,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "camss_csi3pix_clk",
1283 .parent_names = (const char *[]){
1284 "csi3_clk_src",
1285 },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1289 },
1290 },
1291};
1292
1293static struct clk_branch camss_csi3rdi_clk = {
1294 .halt_reg = 0x3204,
1295 .clkr = {
1296 .enable_reg = 0x3204,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "camss_csi3rdi_clk",
1300 .parent_names = (const char *[]){
1301 "csi3_clk_src",
1302 },
1303 .num_parents = 1,
1304 .flags = CLK_SET_RATE_PARENT,
1305 .ops = &clk_branch2_ops,
1306 },
1307 },
1308};
1309
1310static struct clk_branch camss_csi_vfe0_clk = {
1311 .halt_reg = 0x3704,
1312 .clkr = {
1313 .enable_reg = 0x3704,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi_vfe0_clk",
1317 .parent_names = (const char *[]){
1318 "vfe0_clk_src",
1319 },
1320 .num_parents = 1,
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1323 },
1324 },
1325};
1326
1327static struct clk_branch camss_csi_vfe1_clk = {
1328 .halt_reg = 0x3714,
1329 .clkr = {
1330 .enable_reg = 0x3714,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "camss_csi_vfe1_clk",
1334 .parent_names = (const char *[]){
1335 "vfe1_clk_src",
1336 },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static struct clk_branch camss_gp0_clk = {
1345 .halt_reg = 0x3444,
1346 .clkr = {
1347 .enable_reg = 0x3444,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "camss_gp0_clk",
1351 .parent_names = (const char *[]){
1352 "camss_gp0_clk_src",
1353 },
1354 .num_parents = 1,
1355 .flags = CLK_SET_RATE_PARENT,
1356 .ops = &clk_branch2_ops,
1357 },
1358 },
1359};
1360
1361static struct clk_branch camss_gp1_clk = {
1362 .halt_reg = 0x3474,
1363 .clkr = {
1364 .enable_reg = 0x3474,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_gp1_clk",
1368 .parent_names = (const char *[]){
1369 "camss_gp1_clk_src",
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 .ops = &clk_branch2_ops,
1374 },
1375 },
1376};
1377
1378static struct clk_branch camss_ispif_ahb_clk = {
1379 .halt_reg = 0x3224,
1380 .clkr = {
1381 .enable_reg = 0x3224,
1382 .enable_mask = BIT(0),
1383 .hw.init = &(struct clk_init_data){
1384 .name = "camss_ispif_ahb_clk",
1385 .parent_names = (const char *[]){
1386 "mmss_ahb_clk_src",
1387 },
1388 .num_parents = 1,
1389 .ops = &clk_branch2_ops,
1390 },
1391 },
1392};
1393
1394static struct clk_branch camss_jpeg_jpeg0_clk = {
1395 .halt_reg = 0x35a8,
1396 .clkr = {
1397 .enable_reg = 0x35a8,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "camss_jpeg_jpeg0_clk",
1401 .parent_names = (const char *[]){
1402 "jpeg0_clk_src",
1403 },
1404 .num_parents = 1,
1405 .flags = CLK_SET_RATE_PARENT,
1406 .ops = &clk_branch2_ops,
1407 },
1408 },
1409};
1410
1411static struct clk_branch camss_jpeg_jpeg1_clk = {
1412 .halt_reg = 0x35ac,
1413 .clkr = {
1414 .enable_reg = 0x35ac,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "camss_jpeg_jpeg1_clk",
1418 .parent_names = (const char *[]){
1419 "jpeg1_clk_src",
1420 },
1421 .num_parents = 1,
1422 .flags = CLK_SET_RATE_PARENT,
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428static struct clk_branch camss_jpeg_jpeg2_clk = {
1429 .halt_reg = 0x35b0,
1430 .clkr = {
1431 .enable_reg = 0x35b0,
1432 .enable_mask = BIT(0),
1433 .hw.init = &(struct clk_init_data){
1434 .name = "camss_jpeg_jpeg2_clk",
1435 .parent_names = (const char *[]){
1436 "jpeg2_clk_src",
1437 },
1438 .num_parents = 1,
1439 .flags = CLK_SET_RATE_PARENT,
1440 .ops = &clk_branch2_ops,
1441 },
1442 },
1443};
1444
1445static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1446 .halt_reg = 0x35b4,
1447 .clkr = {
1448 .enable_reg = 0x35b4,
1449 .enable_mask = BIT(0),
1450 .hw.init = &(struct clk_init_data){
1451 .name = "camss_jpeg_jpeg_ahb_clk",
1452 .parent_names = (const char *[]){
1453 "mmss_ahb_clk_src",
1454 },
1455 .num_parents = 1,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1462 .halt_reg = 0x35b8,
1463 .clkr = {
1464 .enable_reg = 0x35b8,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "camss_jpeg_jpeg_axi_clk",
1468 .parent_names = (const char *[]){
1469 "mmss_axi_clk_src",
1470 },
1471 .num_parents = 1,
1472 .ops = &clk_branch2_ops,
1473 },
1474 },
1475};
1476
1477static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1478 .halt_reg = 0x35bc,
1479 .clkr = {
1480 .enable_reg = 0x35bc,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1484 .parent_names = (const char *[]){
1485 "ocmemnoc_clk_src",
1486 },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492};
1493
1494static struct clk_branch camss_mclk0_clk = {
1495 .halt_reg = 0x3384,
1496 .clkr = {
1497 .enable_reg = 0x3384,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "camss_mclk0_clk",
1501 .parent_names = (const char *[]){
1502 "mclk0_clk_src",
1503 },
1504 .num_parents = 1,
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509};
1510
1511static struct clk_branch camss_mclk1_clk = {
1512 .halt_reg = 0x33b4,
1513 .clkr = {
1514 .enable_reg = 0x33b4,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "camss_mclk1_clk",
1518 .parent_names = (const char *[]){
1519 "mclk1_clk_src",
1520 },
1521 .num_parents = 1,
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1524 },
1525 },
1526};
1527
1528static struct clk_branch camss_mclk2_clk = {
1529 .halt_reg = 0x33e4,
1530 .clkr = {
1531 .enable_reg = 0x33e4,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(struct clk_init_data){
1534 .name = "camss_mclk2_clk",
1535 .parent_names = (const char *[]){
1536 "mclk2_clk_src",
1537 },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT,
1540 .ops = &clk_branch2_ops,
1541 },
1542 },
1543};
1544
1545static struct clk_branch camss_mclk3_clk = {
1546 .halt_reg = 0x3414,
1547 .clkr = {
1548 .enable_reg = 0x3414,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camss_mclk3_clk",
1552 .parent_names = (const char *[]){
1553 "mclk3_clk_src",
1554 },
1555 .num_parents = 1,
1556 .flags = CLK_SET_RATE_PARENT,
1557 .ops = &clk_branch2_ops,
1558 },
1559 },
1560};
1561
1562static struct clk_branch camss_micro_ahb_clk = {
1563 .halt_reg = 0x3494,
1564 .clkr = {
1565 .enable_reg = 0x3494,
1566 .enable_mask = BIT(0),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "camss_micro_ahb_clk",
1569 .parent_names = (const char *[]){
1570 "mmss_ahb_clk_src",
1571 },
1572 .num_parents = 1,
1573 .ops = &clk_branch2_ops,
1574 },
1575 },
1576};
1577
1578static struct clk_branch camss_phy0_csi0phytimer_clk = {
1579 .halt_reg = 0x3024,
1580 .clkr = {
1581 .enable_reg = 0x3024,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "camss_phy0_csi0phytimer_clk",
1585 .parent_names = (const char *[]){
1586 "csi0phytimer_clk_src",
1587 },
1588 .num_parents = 1,
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1591 },
1592 },
1593};
1594
1595static struct clk_branch camss_phy1_csi1phytimer_clk = {
1596 .halt_reg = 0x3054,
1597 .clkr = {
1598 .enable_reg = 0x3054,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "camss_phy1_csi1phytimer_clk",
1602 .parent_names = (const char *[]){
1603 "csi1phytimer_clk_src",
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610};
1611
1612static struct clk_branch camss_phy2_csi2phytimer_clk = {
1613 .halt_reg = 0x3084,
1614 .clkr = {
1615 .enable_reg = 0x3084,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "camss_phy2_csi2phytimer_clk",
1619 .parent_names = (const char *[]){
1620 "csi2phytimer_clk_src",
1621 },
1622 .num_parents = 1,
1623 .flags = CLK_SET_RATE_PARENT,
1624 .ops = &clk_branch2_ops,
1625 },
1626 },
1627};
1628
1629static struct clk_branch camss_top_ahb_clk = {
1630 .halt_reg = 0x3484,
1631 .clkr = {
1632 .enable_reg = 0x3484,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "camss_top_ahb_clk",
1636 .parent_names = (const char *[]){
1637 "mmss_ahb_clk_src",
1638 },
1639 .num_parents = 1,
1640 .ops = &clk_branch2_ops,
1641 },
1642 },
1643};
1644
1645static struct clk_branch camss_vfe_cpp_ahb_clk = {
1646 .halt_reg = 0x36b4,
1647 .clkr = {
1648 .enable_reg = 0x36b4,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "camss_vfe_cpp_ahb_clk",
1652 .parent_names = (const char *[]){
1653 "mmss_ahb_clk_src",
1654 },
1655 .num_parents = 1,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch camss_vfe_cpp_clk = {
1662 .halt_reg = 0x36b0,
1663 .clkr = {
1664 .enable_reg = 0x36b0,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_vfe_cpp_clk",
1668 .parent_names = (const char *[]){
1669 "cpp_clk_src",
1670 },
1671 .num_parents = 1,
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1674 },
1675 },
1676};
1677
1678static struct clk_branch camss_vfe_vfe0_clk = {
1679 .halt_reg = 0x36a8,
1680 .clkr = {
1681 .enable_reg = 0x36a8,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "camss_vfe_vfe0_clk",
1685 .parent_names = (const char *[]){
1686 "vfe0_clk_src",
1687 },
1688 .num_parents = 1,
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1691 },
1692 },
1693};
1694
1695static struct clk_branch camss_vfe_vfe1_clk = {
1696 .halt_reg = 0x36ac,
1697 .clkr = {
1698 .enable_reg = 0x36ac,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "camss_vfe_vfe1_clk",
1702 .parent_names = (const char *[]){
1703 "vfe1_clk_src",
1704 },
1705 .num_parents = 1,
1706 .flags = CLK_SET_RATE_PARENT,
1707 .ops = &clk_branch2_ops,
1708 },
1709 },
1710};
1711
1712static struct clk_branch camss_vfe_vfe_ahb_clk = {
1713 .halt_reg = 0x36b8,
1714 .clkr = {
1715 .enable_reg = 0x36b8,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "camss_vfe_vfe_ahb_clk",
1719 .parent_names = (const char *[]){
1720 "mmss_ahb_clk_src",
1721 },
1722 .num_parents = 1,
1723 .ops = &clk_branch2_ops,
1724 },
1725 },
1726};
1727
1728static struct clk_branch camss_vfe_vfe_axi_clk = {
1729 .halt_reg = 0x36bc,
1730 .clkr = {
1731 .enable_reg = 0x36bc,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "camss_vfe_vfe_axi_clk",
1735 .parent_names = (const char *[]){
1736 "mmss_axi_clk_src",
1737 },
1738 .num_parents = 1,
1739 .ops = &clk_branch2_ops,
1740 },
1741 },
1742};
1743
1744static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1745 .halt_reg = 0x36c0,
1746 .clkr = {
1747 .enable_reg = 0x36c0,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_vfe_vfe_ocmemnoc_clk",
1751 .parent_names = (const char *[]){
1752 "ocmemnoc_clk_src",
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch mdss_ahb_clk = {
1762 .halt_reg = 0x2308,
1763 .clkr = {
1764 .enable_reg = 0x2308,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "mdss_ahb_clk",
1768 .parent_names = (const char *[]){
1769 "mmss_ahb_clk_src",
1770 },
1771 .num_parents = 1,
1772 .ops = &clk_branch2_ops,
1773 },
1774 },
1775};
1776
1777static struct clk_branch mdss_axi_clk = {
1778 .halt_reg = 0x2310,
1779 .clkr = {
1780 .enable_reg = 0x2310,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "mdss_axi_clk",
1784 .parent_names = (const char *[]){
1785 "mmss_axi_clk_src",
1786 },
1787 .num_parents = 1,
1788 .flags = CLK_SET_RATE_PARENT,
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch mdss_byte0_clk = {
1795 .halt_reg = 0x233c,
1796 .clkr = {
1797 .enable_reg = 0x233c,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "mdss_byte0_clk",
1801 .parent_names = (const char *[]){
1802 "byte0_clk_src",
1803 },
1804 .num_parents = 1,
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809};
1810
1811static struct clk_branch mdss_byte1_clk = {
1812 .halt_reg = 0x2340,
1813 .clkr = {
1814 .enable_reg = 0x2340,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "mdss_byte1_clk",
1818 .parent_names = (const char *[]){
1819 "byte1_clk_src",
1820 },
1821 .num_parents = 1,
1822 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops,
1824 },
1825 },
1826};
1827
1828static struct clk_branch mdss_edpaux_clk = {
1829 .halt_reg = 0x2334,
1830 .clkr = {
1831 .enable_reg = 0x2334,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "mdss_edpaux_clk",
1835 .parent_names = (const char *[]){
1836 "edpaux_clk_src",
1837 },
1838 .num_parents = 1,
1839 .flags = CLK_SET_RATE_PARENT,
1840 .ops = &clk_branch2_ops,
1841 },
1842 },
1843};
1844
1845static struct clk_branch mdss_edplink_clk = {
1846 .halt_reg = 0x2330,
1847 .clkr = {
1848 .enable_reg = 0x2330,
1849 .enable_mask = BIT(0),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "mdss_edplink_clk",
1852 .parent_names = (const char *[]){
1853 "edplink_clk_src",
1854 },
1855 .num_parents = 1,
1856 .flags = CLK_SET_RATE_PARENT,
1857 .ops = &clk_branch2_ops,
1858 },
1859 },
1860};
1861
1862static struct clk_branch mdss_edppixel_clk = {
1863 .halt_reg = 0x232c,
1864 .clkr = {
1865 .enable_reg = 0x232c,
1866 .enable_mask = BIT(0),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "mdss_edppixel_clk",
1869 .parent_names = (const char *[]){
1870 "edppixel_clk_src",
1871 },
1872 .num_parents = 1,
1873 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877};
1878
1879static struct clk_branch mdss_esc0_clk = {
1880 .halt_reg = 0x2344,
1881 .clkr = {
1882 .enable_reg = 0x2344,
1883 .enable_mask = BIT(0),
1884 .hw.init = &(struct clk_init_data){
1885 .name = "mdss_esc0_clk",
1886 .parent_names = (const char *[]){
1887 "esc0_clk_src",
1888 },
1889 .num_parents = 1,
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1892 },
1893 },
1894};
1895
1896static struct clk_branch mdss_esc1_clk = {
1897 .halt_reg = 0x2348,
1898 .clkr = {
1899 .enable_reg = 0x2348,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_esc1_clk",
1903 .parent_names = (const char *[]){
1904 "esc1_clk_src",
1905 },
1906 .num_parents = 1,
1907 .flags = CLK_SET_RATE_PARENT,
1908 .ops = &clk_branch2_ops,
1909 },
1910 },
1911};
1912
1913static struct clk_branch mdss_extpclk_clk = {
1914 .halt_reg = 0x2324,
1915 .clkr = {
1916 .enable_reg = 0x2324,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "mdss_extpclk_clk",
1920 .parent_names = (const char *[]){
1921 "extpclk_clk_src",
1922 },
1923 .num_parents = 1,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1926 },
1927 },
1928};
1929
1930static struct clk_branch mdss_hdmi_ahb_clk = {
1931 .halt_reg = 0x230c,
1932 .clkr = {
1933 .enable_reg = 0x230c,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "mdss_hdmi_ahb_clk",
1937 .parent_names = (const char *[]){
1938 "mmss_ahb_clk_src",
1939 },
1940 .num_parents = 1,
1941 .ops = &clk_branch2_ops,
1942 },
1943 },
1944};
1945
1946static struct clk_branch mdss_hdmi_clk = {
1947 .halt_reg = 0x2338,
1948 .clkr = {
1949 .enable_reg = 0x2338,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "mdss_hdmi_clk",
1953 .parent_names = (const char *[]){
1954 "hdmi_clk_src",
1955 },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch mdss_mdp_clk = {
1964 .halt_reg = 0x231c,
1965 .clkr = {
1966 .enable_reg = 0x231c,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "mdss_mdp_clk",
1970 .parent_names = (const char *[]){
1971 "mdp_clk_src",
1972 },
1973 .num_parents = 1,
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1976 },
1977 },
1978};
1979
1980static struct clk_branch mdss_mdp_lut_clk = {
1981 .halt_reg = 0x2320,
1982 .clkr = {
1983 .enable_reg = 0x2320,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "mdss_mdp_lut_clk",
1987 .parent_names = (const char *[]){
1988 "mdp_clk_src",
1989 },
1990 .num_parents = 1,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch mdss_pclk0_clk = {
1998 .halt_reg = 0x2314,
1999 .clkr = {
2000 .enable_reg = 0x2314,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "mdss_pclk0_clk",
2004 .parent_names = (const char *[]){
2005 "pclk0_clk_src",
2006 },
2007 .num_parents = 1,
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2010 },
2011 },
2012};
2013
2014static struct clk_branch mdss_pclk1_clk = {
2015 .halt_reg = 0x2318,
2016 .clkr = {
2017 .enable_reg = 0x2318,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "mdss_pclk1_clk",
2021 .parent_names = (const char *[]){
2022 "pclk1_clk_src",
2023 },
2024 .num_parents = 1,
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2027 },
2028 },
2029};
2030
2031static struct clk_branch mdss_vsync_clk = {
2032 .halt_reg = 0x2328,
2033 .clkr = {
2034 .enable_reg = 0x2328,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "mdss_vsync_clk",
2038 .parent_names = (const char *[]){
2039 "vsync_clk_src",
2040 },
2041 .num_parents = 1,
2042 .flags = CLK_SET_RATE_PARENT,
2043 .ops = &clk_branch2_ops,
2044 },
2045 },
2046};
2047
2048static struct clk_branch mmss_misc_ahb_clk = {
2049 .halt_reg = 0x502c,
2050 .clkr = {
2051 .enable_reg = 0x502c,
2052 .enable_mask = BIT(0),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "mmss_misc_ahb_clk",
2055 .parent_names = (const char *[]){
2056 "mmss_ahb_clk_src",
2057 },
2058 .num_parents = 1,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch mmss_mmssnoc_ahb_clk = {
2065 .halt_reg = 0x5024,
2066 .clkr = {
2067 .enable_reg = 0x5024,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mmss_mmssnoc_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "mmss_ahb_clk_src",
2073 },
2074 .num_parents = 1,
2075 .ops = &clk_branch2_ops,
2076 .flags = CLK_IGNORE_UNUSED,
2077 },
2078 },
2079};
2080
2081static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2082 .halt_reg = 0x5028,
2083 .clkr = {
2084 .enable_reg = 0x5028,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mmss_mmssnoc_bto_ahb_clk",
2088 .parent_names = (const char *[]){
2089 "mmss_ahb_clk_src",
2090 },
2091 .num_parents = 1,
2092 .ops = &clk_branch2_ops,
2093 .flags = CLK_IGNORE_UNUSED,
2094 },
2095 },
2096};
2097
2098static struct clk_branch mmss_mmssnoc_axi_clk = {
2099 .halt_reg = 0x506c,
2100 .clkr = {
2101 .enable_reg = 0x506c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mmss_mmssnoc_axi_clk",
2105 .parent_names = (const char *[]){
2106 "mmss_axi_clk_src",
2107 },
2108 .num_parents = 1,
2109 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2110 .ops = &clk_branch2_ops,
2111 },
2112 },
2113};
2114
2115static struct clk_branch mmss_s0_axi_clk = {
2116 .halt_reg = 0x5064,
2117 .clkr = {
2118 .enable_reg = 0x5064,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mmss_s0_axi_clk",
2122 .parent_names = (const char *[]){
2123 "mmss_axi_clk_src",
2124 },
2125 .num_parents = 1,
2126 .ops = &clk_branch2_ops,
2127 .flags = CLK_IGNORE_UNUSED,
2128 },
2129 },
2130};
2131
2132static struct clk_branch ocmemcx_ahb_clk = {
2133 .halt_reg = 0x405c,
2134 .clkr = {
2135 .enable_reg = 0x405c,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "ocmemcx_ahb_clk",
2139 .parent_names = (const char *[]){
2140 "mmss_ahb_clk_src",
2141 },
2142 .num_parents = 1,
2143 .ops = &clk_branch2_ops,
2144 },
2145 },
2146};
2147
2148static struct clk_branch ocmemcx_ocmemnoc_clk = {
2149 .halt_reg = 0x4058,
2150 .clkr = {
2151 .enable_reg = 0x4058,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "ocmemcx_ocmemnoc_clk",
2155 .parent_names = (const char *[]){
2156 "ocmemnoc_clk_src",
2157 },
2158 .num_parents = 1,
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2161 },
2162 },
2163};
2164
2165static struct clk_branch oxili_ocmemgx_clk = {
2166 .halt_reg = 0x402c,
2167 .clkr = {
2168 .enable_reg = 0x402c,
2169 .enable_mask = BIT(0),
2170 .hw.init = &(struct clk_init_data){
2171 .name = "oxili_ocmemgx_clk",
2172 .parent_names = (const char *[]){
2173 "gfx3d_clk_src",
2174 },
2175 .num_parents = 1,
2176 .flags = CLK_SET_RATE_PARENT,
2177 .ops = &clk_branch2_ops,
2178 },
2179 },
2180};
2181
2182static struct clk_branch ocmemnoc_clk = {
2183 .halt_reg = 0x50b4,
2184 .clkr = {
2185 .enable_reg = 0x50b4,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "ocmemnoc_clk",
2189 .parent_names = (const char *[]){
2190 "ocmemnoc_clk_src",
2191 },
2192 .num_parents = 1,
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2195 },
2196 },
2197};
2198
2199static struct clk_branch oxili_gfx3d_clk = {
2200 .halt_reg = 0x4028,
2201 .clkr = {
2202 .enable_reg = 0x4028,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "oxili_gfx3d_clk",
2206 .parent_names = (const char *[]){
2207 "gfx3d_clk_src",
2208 },
2209 .num_parents = 1,
2210 .flags = CLK_SET_RATE_PARENT,
2211 .ops = &clk_branch2_ops,
2212 },
2213 },
2214};
2215
2216static struct clk_branch oxilicx_ahb_clk = {
2217 .halt_reg = 0x403c,
2218 .clkr = {
2219 .enable_reg = 0x403c,
2220 .enable_mask = BIT(0),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "oxilicx_ahb_clk",
2223 .parent_names = (const char *[]){
2224 "mmss_ahb_clk_src",
2225 },
2226 .num_parents = 1,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230};
2231
2232static struct clk_branch oxilicx_axi_clk = {
2233 .halt_reg = 0x4038,
2234 .clkr = {
2235 .enable_reg = 0x4038,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "oxilicx_axi_clk",
2239 .parent_names = (const char *[]){
2240 "mmss_axi_clk_src",
2241 },
2242 .num_parents = 1,
2243 .ops = &clk_branch2_ops,
2244 },
2245 },
2246};
2247
2248static struct clk_branch venus0_ahb_clk = {
2249 .halt_reg = 0x1030,
2250 .clkr = {
2251 .enable_reg = 0x1030,
2252 .enable_mask = BIT(0),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "venus0_ahb_clk",
2255 .parent_names = (const char *[]){
2256 "mmss_ahb_clk_src",
2257 },
2258 .num_parents = 1,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch venus0_axi_clk = {
2265 .halt_reg = 0x1034,
2266 .clkr = {
2267 .enable_reg = 0x1034,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "venus0_axi_clk",
2271 .parent_names = (const char *[]){
2272 "mmss_axi_clk_src",
2273 },
2274 .num_parents = 1,
2275 .ops = &clk_branch2_ops,
2276 },
2277 },
2278};
2279
2280static struct clk_branch venus0_ocmemnoc_clk = {
2281 .halt_reg = 0x1038,
2282 .clkr = {
2283 .enable_reg = 0x1038,
2284 .enable_mask = BIT(0),
2285 .hw.init = &(struct clk_init_data){
2286 .name = "venus0_ocmemnoc_clk",
2287 .parent_names = (const char *[]){
2288 "ocmemnoc_clk_src",
2289 },
2290 .num_parents = 1,
2291 .flags = CLK_SET_RATE_PARENT,
2292 .ops = &clk_branch2_ops,
2293 },
2294 },
2295};
2296
2297static struct clk_branch venus0_vcodec0_clk = {
2298 .halt_reg = 0x1028,
2299 .clkr = {
2300 .enable_reg = 0x1028,
2301 .enable_mask = BIT(0),
2302 .hw.init = &(struct clk_init_data){
2303 .name = "venus0_vcodec0_clk",
2304 .parent_names = (const char *[]){
2305 "vcodec0_clk_src",
2306 },
2307 .num_parents = 1,
2308 .flags = CLK_SET_RATE_PARENT,
2309 .ops = &clk_branch2_ops,
2310 },
2311 },
2312};
2313
2314static const struct pll_config mmpll1_config = {
2315 .l = 60,
2316 .m = 25,
2317 .n = 32,
2318 .vco_val = 0x0,
2319 .vco_mask = 0x3 << 20,
2320 .pre_div_val = 0x0,
2321 .pre_div_mask = 0x3 << 12,
2322 .post_div_val = 0x0,
2323 .post_div_mask = 0x3 << 8,
2324 .mn_ena_mask = BIT(24),
2325 .main_output_mask = BIT(0),
2326};
2327
2328static struct pll_config mmpll3_config = {
2329 .l = 48,
2330 .m = 7,
2331 .n = 16,
2332 .vco_val = 0x0,
2333 .vco_mask = 0x3 << 20,
2334 .pre_div_val = 0x0,
2335 .pre_div_mask = 0x3 << 12,
2336 .post_div_val = 0x0,
2337 .post_div_mask = 0x3 << 8,
2338 .mn_ena_mask = BIT(24),
2339 .main_output_mask = BIT(0),
2340 .aux_output_mask = BIT(1),
2341};
2342
2343static struct clk_regmap *mmcc_msm8974_clocks[] = {
2344 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2345 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2346 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2347 [MMPLL0] = &mmpll0.clkr,
2348 [MMPLL0_VOTE] = &mmpll0_vote,
2349 [MMPLL1] = &mmpll1.clkr,
2350 [MMPLL1_VOTE] = &mmpll1_vote,
2351 [MMPLL2] = &mmpll2.clkr,
2352 [MMPLL3] = &mmpll3.clkr,
2353 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2354 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2355 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2356 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2357 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2358 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2359 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2360 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2361 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2362 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2363 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2364 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2365 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2366 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2367 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2368 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2369 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2370 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2371 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2372 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2373 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2374 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2375 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2376 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2377 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2378 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2379 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2380 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2381 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2382 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2383 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2384 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2385 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2386 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2387 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2388 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2389 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2390 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2391 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2392 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2393 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2394 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2395 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2396 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2397 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2398 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2399 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2400 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2401 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2402 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2403 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2404 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2405 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2406 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2407 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2408 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2409 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2410 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2411 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2412 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2413 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2414 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2415 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2416 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2417 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2418 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2419 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2420 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2421 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2422 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2423 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2424 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2425 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2426 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2427 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2428 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2429 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2430 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2431 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2432 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2433 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2434 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2435 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2436 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2437 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2438 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2439 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2440 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2441 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2442 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2443 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2444 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2445 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2446 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2447 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2448 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2449 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2450 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2451 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2452 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2453 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2454 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2455 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2456 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2457 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2458 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2459 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2460 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2461 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2462 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2463 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2464 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2465 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2466 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2467 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2468 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2469 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2470};
2471
2472static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2473 [SPDM_RESET] = { 0x0200 },
2474 [SPDM_RM_RESET] = { 0x0300 },
2475 [VENUS0_RESET] = { 0x1020 },
2476 [MDSS_RESET] = { 0x2300 },
2477 [CAMSS_PHY0_RESET] = { 0x3020 },
2478 [CAMSS_PHY1_RESET] = { 0x3050 },
2479 [CAMSS_PHY2_RESET] = { 0x3080 },
2480 [CAMSS_CSI0_RESET] = { 0x30b0 },
2481 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2482 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2483 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2484 [CAMSS_CSI1_RESET] = { 0x3120 },
2485 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2486 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2487 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2488 [CAMSS_CSI2_RESET] = { 0x3180 },
2489 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2490 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2491 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2492 [CAMSS_CSI3_RESET] = { 0x31e0 },
2493 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2494 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2495 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2496 [CAMSS_ISPIF_RESET] = { 0x3220 },
2497 [CAMSS_CCI_RESET] = { 0x3340 },
2498 [CAMSS_MCLK0_RESET] = { 0x3380 },
2499 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2500 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2501 [CAMSS_MCLK3_RESET] = { 0x3410 },
2502 [CAMSS_GP0_RESET] = { 0x3440 },
2503 [CAMSS_GP1_RESET] = { 0x3470 },
2504 [CAMSS_TOP_RESET] = { 0x3480 },
2505 [CAMSS_MICRO_RESET] = { 0x3490 },
2506 [CAMSS_JPEG_RESET] = { 0x35a0 },
2507 [CAMSS_VFE_RESET] = { 0x36a0 },
2508 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2509 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2510 [OXILI_RESET] = { 0x4020 },
2511 [OXILICX_RESET] = { 0x4030 },
2512 [OCMEMCX_RESET] = { 0x4050 },
2513 [MMSS_RBCRP_RESET] = { 0x4080 },
2514 [MMSSNOCAHB_RESET] = { 0x5020 },
2515 [MMSSNOCAXI_RESET] = { 0x5060 },
2516 [OCMEMNOC_RESET] = { 0x50b0 },
2517};
2518
2519static const struct regmap_config mmcc_msm8974_regmap_config = {
2520 .reg_bits = 32,
2521 .reg_stride = 4,
2522 .val_bits = 32,
2523 .max_register = 0x5104,
2524 .fast_io = true,
2525};
2526
2527static const struct of_device_id mmcc_msm8974_match_table[] = {
2528 { .compatible = "qcom,mmcc-msm8974" },
2529 { }
2530};
2531MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2532
2533struct qcom_cc {
2534 struct qcom_reset_controller reset;
2535 struct clk_onecell_data data;
2536 struct clk *clks[];
2537};
2538
2539static int mmcc_msm8974_probe(struct platform_device *pdev)
2540{
2541 void __iomem *base;
2542 struct resource *res;
2543 int i, ret;
2544 struct device *dev = &pdev->dev;
2545 struct clk *clk;
2546 struct clk_onecell_data *data;
2547 struct clk **clks;
2548 struct regmap *regmap;
2549 size_t num_clks;
2550 struct qcom_reset_controller *reset;
2551 struct qcom_cc *cc;
2552
2553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2554 base = devm_ioremap_resource(dev, res);
2555 if (IS_ERR(base))
2556 return PTR_ERR(base);
2557
2558 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8974_regmap_config);
2559 if (IS_ERR(regmap))
2560 return PTR_ERR(regmap);
2561
2562 num_clks = ARRAY_SIZE(mmcc_msm8974_clocks);
2563 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2564 GFP_KERNEL);
2565 if (!cc)
2566 return -ENOMEM;
2567
2568 clks = cc->clks;
2569 data = &cc->data;
2570 data->clks = clks;
2571 data->clk_num = num_clks;
2572
2573 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2574 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2575
2576 for (i = 0; i < num_clks; i++) {
2577 if (!mmcc_msm8974_clocks[i])
2578 continue;
2579 clk = devm_clk_register_regmap(dev, mmcc_msm8974_clocks[i]);
2580 if (IS_ERR(clk))
2581 return PTR_ERR(clk);
2582 clks[i] = clk;
2583 }
2584
2585 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2586 if (ret)
2587 return ret;
2588
2589 reset = &cc->reset;
2590 reset->rcdev.of_node = dev->of_node;
2591 reset->rcdev.ops = &qcom_reset_ops,
2592 reset->rcdev.owner = THIS_MODULE,
2593 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2594 reset->regmap = regmap;
2595 reset->reset_map = mmcc_msm8974_resets,
2596 platform_set_drvdata(pdev, &reset->rcdev);
2597
2598 ret = reset_controller_register(&reset->rcdev);
2599 if (ret)
2600 of_clk_del_provider(dev->of_node);
2601
2602 return ret;
2603}
2604
2605static int mmcc_msm8974_remove(struct platform_device *pdev)
2606{
2607 of_clk_del_provider(pdev->dev.of_node);
2608 reset_controller_unregister(platform_get_drvdata(pdev));
2609 return 0;
2610}
2611
2612static struct platform_driver mmcc_msm8974_driver = {
2613 .probe = mmcc_msm8974_probe,
2614 .remove = mmcc_msm8974_remove,
2615 .driver = {
2616 .name = "mmcc-msm8974",
2617 .owner = THIS_MODULE,
2618 .of_match_table = mmcc_msm8974_match_table,
2619 },
2620};
2621module_platform_driver(mmcc_msm8974_driver);
2622
2623MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2624MODULE_LICENSE("GPL v2");
2625MODULE_ALIAS("platform:mmcc-msm8974");
diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c
new file mode 100644
index 000000000000..6c977d3a8590
--- /dev/null
+++ b/drivers/clk/qcom/reset.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/export.h>
16#include <linux/regmap.h>
17#include <linux/reset-controller.h>
18#include <linux/delay.h>
19
20#include "reset.h"
21
22static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
23{
24 rcdev->ops->assert(rcdev, id);
25 udelay(1);
26 rcdev->ops->deassert(rcdev, id);
27 return 0;
28}
29
30static int
31qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
32{
33 struct qcom_reset_controller *rst;
34 const struct qcom_reset_map *map;
35 u32 mask;
36
37 rst = to_qcom_reset_controller(rcdev);
38 map = &rst->reset_map[id];
39 mask = BIT(map->bit);
40
41 return regmap_update_bits(rst->regmap, map->reg, mask, mask);
42}
43
44static int
45qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
46{
47 struct qcom_reset_controller *rst;
48 const struct qcom_reset_map *map;
49 u32 mask;
50
51 rst = to_qcom_reset_controller(rcdev);
52 map = &rst->reset_map[id];
53 mask = BIT(map->bit);
54
55 return regmap_update_bits(rst->regmap, map->reg, mask, 0);
56}
57
58struct reset_control_ops qcom_reset_ops = {
59 .reset = qcom_reset,
60 .assert = qcom_reset_assert,
61 .deassert = qcom_reset_deassert,
62};
63EXPORT_SYMBOL_GPL(qcom_reset_ops);
diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h
new file mode 100644
index 000000000000..0e11e2130f97
--- /dev/null
+++ b/drivers/clk/qcom/reset.h
@@ -0,0 +1,37 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_RESET_H__
15#define __QCOM_CLK_RESET_H__
16
17#include <linux/reset-controller.h>
18
19struct qcom_reset_map {
20 unsigned int reg;
21 u8 bit;
22};
23
24struct regmap;
25
26struct qcom_reset_controller {
27 const struct qcom_reset_map *reset_map;
28 struct regmap *regmap;
29 struct reset_controller_dev rcdev;
30};
31
32#define to_qcom_reset_controller(r) \
33 container_of(r, struct qcom_reset_controller, rcdev);
34
35extern struct reset_control_ops qcom_reset_ops;
36
37#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 19:33:27 -0500