1 files changed, 123 insertions, 31 deletions

diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 7162615bcdcd..d1e5863d3375 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -18,26 +18,56 @@
 #include "common.h"
 
 #define CORE_CLK_DIV_RATIO_MASK         0xff
-#define CORE_CLK_DIV_RATIO_RELOAD       BIT(8)
-#define CORE_CLK_DIV_ENABLE_OFFSET      24
-#define CORE_CLK_DIV_RATIO_OFFSET       0x8
 
+/*
+ * This structure describes the hardware details (bit offset and mask)
+ * to configure one particular core divider clock. Those hardware
+ * details may differ from one SoC to another. This structure is
+ * therefore typically instantiated statically to describe the
+ * hardware details.
+ */
 struct clk_corediv_desc {
         unsigned int mask;
         unsigned int offset;
         unsigned int fieldbit;
 };
 
+/*
+ * This structure describes the hardware details to configure the core
+ * divider clocks on a given SoC. Amongst others, it points to the
+ * array of core divider clock descriptors for this SoC, as well as
+ * the corresponding operations to manipulate them.
+ */
+struct clk_corediv_soc_desc {
+        const struct clk_corediv_desc *descs;
+        unsigned int ndescs;
+        const struct clk_ops ops;
+        u32 ratio_reload;
+        u32 enable_bit_offset;
+        u32 ratio_offset;
+};
+
+/*
+ * This structure represents one core divider clock for the clock
+ * framework, and is dynamically allocated for each core divider clock
+ * existing in the current SoC.
+ */
 struct clk_corediv {
         struct clk_hw hw;
         void __iomem *reg;
-        struct clk_corediv_desc desc;
+        const struct clk_corediv_desc *desc;
+        const struct clk_corediv_soc_desc *soc_desc;
         spinlock_t lock;
 };
 
 static struct clk_onecell_data clk_data;
 
-static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = {
+/*
+ * Description of the core divider clocks available. For now, we
+ * support only NAND, and it is available at the same register
+ * locations regardless of the SoC.
+ */
+static const struct clk_corediv_desc mvebu_corediv_desc[] = {
         { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
 };
 
@@ -46,8 +76,9 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = {
 static int clk_corediv_is_enabled(struct clk_hw *hwclk)
 {
         struct clk_corediv *corediv = to_corediv_clk(hwclk);
-        struct clk_corediv_desc *desc = &corediv->desc;
-        u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET;
+        const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
+        const struct clk_corediv_desc *desc = corediv->desc;
+        u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset;
 
         return !!(readl(corediv->reg) & enable_mask);
 }
@@ -55,14 +86,15 @@ static int clk_corediv_is_enabled(struct clk_hw *hwclk)
 static int clk_corediv_enable(struct clk_hw *hwclk)
 {
         struct clk_corediv *corediv = to_corediv_clk(hwclk);
-        struct clk_corediv_desc *desc = &corediv->desc;
+        const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
+        const struct clk_corediv_desc *desc = corediv->desc;
         unsigned long flags = 0;
         u32 reg;
 
         spin_lock_irqsave(&corediv->lock, flags);
 
         reg = readl(corediv->reg);
-        reg |= (BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET);
+        reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset);
         writel(reg, corediv->reg);
 
         spin_unlock_irqrestore(&corediv->lock, flags);
@@ -73,14 +105,15 @@ static int clk_corediv_enable(struct clk_hw *hwclk)
 static void clk_corediv_disable(struct clk_hw *hwclk)
 {
         struct clk_corediv *corediv = to_corediv_clk(hwclk);
-        struct clk_corediv_desc *desc = &corediv->desc;
+        const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
+        const struct clk_corediv_desc *desc = corediv->desc;
         unsigned long flags = 0;
         u32 reg;
 
         spin_lock_irqsave(&corediv->lock, flags);
 
         reg = readl(corediv->reg);
-        reg &= ~(BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET);
+        reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset);
         writel(reg, corediv->reg);
 
         spin_unlock_irqrestore(&corediv->lock, flags);
@@ -90,10 +123,11 @@ static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk,
                                          unsigned long parent_rate)
 {
         struct clk_corediv *corediv = to_corediv_clk(hwclk);
-        struct clk_corediv_desc *desc = &corediv->desc;
+        const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
+        const struct clk_corediv_desc *desc = corediv->desc;
         u32 reg, div;
 
-        reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
+        reg = readl(corediv->reg + soc_desc->ratio_offset);
         div = (reg >> desc->offset) & desc->mask;
         return parent_rate / div;
 }
@@ -117,7 +151,8 @@ static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
                             unsigned long parent_rate)
 {
         struct clk_corediv *corediv = to_corediv_clk(hwclk);
-        struct clk_corediv_desc *desc = &corediv->desc;
+        const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
+        const struct clk_corediv_desc *desc = corediv->desc;
         unsigned long flags = 0;
         u32 reg, div;
 
@@ -126,17 +161,17 @@ static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
         spin_lock_irqsave(&corediv->lock, flags);
 
         /* Write new divider to the divider ratio register */
-        reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
+        reg = readl(corediv->reg + soc_desc->ratio_offset);
         reg &= ~(desc->mask << desc->offset);
         reg |= (div & desc->mask) << desc->offset;
-        writel(reg, corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
+        writel(reg, corediv->reg + soc_desc->ratio_offset);
 
         /* Set reload-force for this clock */
         reg = readl(corediv->reg) | BIT(desc->fieldbit);
         writel(reg, corediv->reg);
 
         /* Now trigger the clock update */
-        reg = readl(corediv->reg) | CORE_CLK_DIV_RATIO_RELOAD;
+        reg = readl(corediv->reg) | soc_desc->ratio_reload;
         writel(reg, corediv->reg);
 
         /*
@@ -144,7 +179,7 @@ static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
          * ratios request and the reload request.
          */
         udelay(1000);
-        reg &= ~(CORE_CLK_DIV_RATIO_MASK | CORE_CLK_DIV_RATIO_RELOAD);
+        reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload);
         writel(reg, corediv->reg);
         udelay(1000);
 
@@ -153,16 +188,53 @@ static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
         return 0;
 }
 
-static const struct clk_ops corediv_ops = {
-        .enable = clk_corediv_enable,
-        .disable = clk_corediv_disable,
-        .is_enabled = clk_corediv_is_enabled,
-        .recalc_rate = clk_corediv_recalc_rate,
-        .round_rate = clk_corediv_round_rate,
-        .set_rate = clk_corediv_set_rate,
+static const struct clk_corediv_soc_desc armada370_corediv_soc = {
+        .descs = mvebu_corediv_desc,
+        .ndescs = ARRAY_SIZE(mvebu_corediv_desc),
+        .ops = {
+                .enable = clk_corediv_enable,
+                .disable = clk_corediv_disable,
+                .is_enabled = clk_corediv_is_enabled,
+                .recalc_rate = clk_corediv_recalc_rate,
+                .round_rate = clk_corediv_round_rate,
+                .set_rate = clk_corediv_set_rate,
+        },
+        .ratio_reload = BIT(8),
+        .enable_bit_offset = 24,
+        .ratio_offset = 0x8,
+};
+
+static const struct clk_corediv_soc_desc armada380_corediv_soc = {
+        .descs = mvebu_corediv_desc,
+        .ndescs = ARRAY_SIZE(mvebu_corediv_desc),
+        .ops = {
+                .enable = clk_corediv_enable,
+                .disable = clk_corediv_disable,
+                .is_enabled = clk_corediv_is_enabled,
+                .recalc_rate = clk_corediv_recalc_rate,
+                .round_rate = clk_corediv_round_rate,
+                .set_rate = clk_corediv_set_rate,
+        },
+        .ratio_reload = BIT(8),
+        .enable_bit_offset = 16,
+        .ratio_offset = 0x4,
 };
 
-static void __init mvebu_corediv_clk_init(struct device_node *node)
+static const struct clk_corediv_soc_desc armada375_corediv_soc = {
+        .descs = mvebu_corediv_desc,
+        .ndescs = ARRAY_SIZE(mvebu_corediv_desc),
+        .ops = {
+                .recalc_rate = clk_corediv_recalc_rate,
+                .round_rate = clk_corediv_round_rate,
+                .set_rate = clk_corediv_set_rate,
+        },
+        .ratio_reload = BIT(8),
+        .ratio_offset = 0x4,
+};
+
+static void __init
+mvebu_corediv_clk_init(struct device_node *node,
+                       const struct clk_corediv_soc_desc *soc_desc)
 {
         struct clk_init_data init;
         struct clk_corediv *corediv;
@@ -178,7 +250,7 @@ static void __init mvebu_corediv_clk_init(struct device_node *node)
 
         parent_name = of_clk_get_parent_name(node, 0);
 
-        clk_data.clk_num = ARRAY_SIZE(mvebu_corediv_desc);
+        clk_data.clk_num = soc_desc->ndescs;
 
         /* clks holds the clock array */
         clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
@@ -199,10 +271,11 @@ static void __init mvebu_corediv_clk_init(struct device_node *node)
                 init.num_parents = 1;
                 init.parent_names = &parent_name;
                 init.name = clk_name;
-                init.ops = &corediv_ops;
+                init.ops = &soc_desc->ops;
                 init.flags = 0;
 
-                corediv[i].desc = mvebu_corediv_desc[i];
+                corediv[i].soc_desc = soc_desc;
+                corediv[i].desc = soc_desc->descs + i;
                 corediv[i].reg = base;
                 corediv[i].hw.init = &init;
 
@@ -219,5 +292,24 @@ err_free_clks:
 err_unmap:
         iounmap(base);
 }
-CLK_OF_DECLARE(mvebu_corediv_clk, "marvell,armada-370-corediv-clock",
-               mvebu_corediv_clk_init);
+
+static void __init armada370_corediv_clk_init(struct device_node *node)
+{
+        return mvebu_corediv_clk_init(node, &armada370_corediv_soc);
+}
+CLK_OF_DECLARE(armada370_corediv_clk, "marvell,armada-370-corediv-clock",
+               armada370_corediv_clk_init);
+
+static void __init armada375_corediv_clk_init(struct device_node *node)
+{
+        return mvebu_corediv_clk_init(node, &armada375_corediv_soc);
+}
+CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock",
+               armada375_corediv_clk_init);
+
+static void __init armada380_corediv_clk_init(struct device_node *node)
+{
+        return mvebu_corediv_clk_init(node, &armada380_corediv_soc);
+}
+CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
+               armada380_corediv_clk_init);