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generated by cgit v1.2.2 (git 2.25.0) at 2025-09-15 22:27:08 -0400
kwb">unsigned char chan_allocation_order; #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ unsigned char chan_priority; }; /** * enum dw_dma_slave_width - DMA slave register access width. * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses */ enum dw_dma_slave_width { DW_DMA_SLAVE_WIDTH_8BIT, DW_DMA_SLAVE_WIDTH_16BIT, DW_DMA_SLAVE_WIDTH_32BIT, }; /* bursts size */ enum dw_dma_msize { DW_DMA_MSIZE_1, DW_DMA_MSIZE_4, DW_DMA_MSIZE_8, DW_DMA_MSIZE_16, DW_DMA_MSIZE_32, DW_DMA_MSIZE_64, DW_DMA_MSIZE_128, DW_DMA_MSIZE_256, }; /* flow controller */ enum dw_dma_fc { DW_DMA_FC_D_M2M, DW_DMA_FC_D_M2P, DW_DMA_FC_D_P2M, DW_DMA_FC_D_P2P, DW_DMA_FC_P_P2M, DW_DMA_FC_SP_P2P, DW_DMA_FC_P_M2P, DW_DMA_FC_DP_P2P, }; /** * struct dw_dma_slave - Controller-specific information about a slave * * @dma_dev: required DMA master device * @tx_reg: physical address of data register used for * memory-to-peripheral transfers * @rx_reg: physical address of data register used for * peripheral-to-memory transfers * @reg_width: peripheral register width * @cfg_hi: Platform-specific initializer for the CFG_HI register * @cfg_lo: Platform-specific initializer for the CFG_LO register * @src_master: src master for transfers on allocated channel. * @dst_master: dest master for transfers on allocated channel. * @src_msize: src burst size. * @dst_msize: dest burst size. * @fc: flow controller for DMA transfer */ struct dw_dma_slave { struct device *dma_dev; dma_addr_t tx_reg; dma_addr_t rx_reg; enum dw_dma_slave_width reg_width; u32 cfg_hi; u32 cfg_lo; u8 src_master; u8 dst_master; u8 src_msize; u8 dst_msize; u8 fc; }; /* Platform-configurable bits in CFG_HI */ #define DWC_CFGH_FCMODE (1 << 0) #define DWC_CFGH_FIFO_MODE (1 << 1) #define DWC_CFGH_PROTCTL(x) ((x) << 2) #define DWC_CFGH_SRC_PER(x) ((x) << 7) #define DWC_CFGH_DST_PER(x) ((x) << 11) /* Platform-configurable bits in CFG_LO */ #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) #define DWC_CFGL_LOCK_CH_XACT (2 << 12) #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ /* DMA API extensions */ struct dw_cyclic_desc {