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Diffstat (limited to 'drivers/char/watchdog/i6300esb.h')
-rw-r--r-- | drivers/char/watchdog/i6300esb.h | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/drivers/char/watchdog/i6300esb.h b/drivers/char/watchdog/i6300esb.h deleted file mode 100644 index 20c923bbb1c9..000000000000 --- a/drivers/char/watchdog/i6300esb.h +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | /* | ||
2 | * i6300esb: Watchdog timer driver for Intel 6300ESB chipset | ||
3 | * | ||
4 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights Reserved. | ||
5 | * http://www.kernelconcepts.de | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License | ||
9 | * as published by the Free Software Foundation; either version | ||
10 | * 2 of the License, or (at your option) any later version. | ||
11 | * | ||
12 | * Neither kernel concepts nor Nils Faerber admit liability nor provide | ||
13 | * warranty for any of this software. This material is provided | ||
14 | * "AS-IS" and at no charge. | ||
15 | * | ||
16 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de> | ||
17 | * developed for | ||
18 | * Jentro AG, Haar/Munich (Germany) | ||
19 | * | ||
20 | * TCO timer driver for i8xx chipsets | ||
21 | * based on softdog.c by Alan Cox <alan@redhat.com> | ||
22 | * | ||
23 | * For history and the complete list of supported I/O Controller Hub's | ||
24 | * see i8xx_tco.c | ||
25 | */ | ||
26 | |||
27 | |||
28 | /* | ||
29 | * Some address definitions for the TCO | ||
30 | */ | ||
31 | |||
32 | /* PCI configuration registers */ | ||
33 | #define ESB_CONFIG_REG 0x60 /* Config register */ | ||
34 | #define ESB_LOCK_REG 0x68 /* WDT lock register */ | ||
35 | |||
36 | /* Memory mapped registers */ | ||
37 | #define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */ | ||
38 | #define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */ | ||
39 | #define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */ | ||
40 | #define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */ | ||
41 | |||
42 | |||
43 | /* | ||
44 | * Some register bits | ||
45 | */ | ||
46 | |||
47 | /* Lock register bits */ | ||
48 | #define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */ | ||
49 | #define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */ | ||
50 | #define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */ | ||
51 | |||
52 | /* Config register bits */ | ||
53 | #define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */ | ||
54 | #define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */ | ||
55 | #define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */ | ||
56 | |||
57 | /* Reload register bits */ | ||
58 | #define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */ | ||
59 | |||
60 | /* | ||
61 | * Some magic constants | ||
62 | */ | ||
63 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ | ||
64 | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ | ||