diff options
Diffstat (limited to 'drivers/char/agp/intel-agp.h')
-rw-r--r-- | drivers/char/agp/intel-agp.h | 40 |
1 files changed, 35 insertions, 5 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 57226424690c..6ec0fff79bc2 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h | |||
@@ -64,6 +64,7 @@ | |||
64 | #define I830_PTE_SYSTEM_CACHED 0x00000006 | 64 | #define I830_PTE_SYSTEM_CACHED 0x00000006 |
65 | /* GT PTE cache control fields */ | 65 | /* GT PTE cache control fields */ |
66 | #define GEN6_PTE_UNCACHED 0x00000002 | 66 | #define GEN6_PTE_UNCACHED 0x00000002 |
67 | #define HSW_PTE_UNCACHED 0x00000000 | ||
67 | #define GEN6_PTE_LLC 0x00000004 | 68 | #define GEN6_PTE_LLC 0x00000004 |
68 | #define GEN6_PTE_LLC_MLC 0x00000006 | 69 | #define GEN6_PTE_LLC_MLC 0x00000006 |
69 | #define GEN6_PTE_GFDT 0x00000008 | 70 | #define GEN6_PTE_GFDT 0x00000008 |
@@ -239,16 +240,45 @@ | |||
239 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A | 240 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A |
240 | #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */ | 241 | #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */ |
241 | #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30 | 242 | #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30 |
242 | #define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */ | 243 | #define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */ |
243 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402 | 244 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402 |
244 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412 | 245 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412 |
245 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */ | 246 | #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422 |
247 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */ | ||
246 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406 | 248 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406 |
247 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416 | 249 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416 |
248 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */ | 250 | #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426 |
251 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */ | ||
249 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a | 252 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a |
250 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a | 253 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a |
251 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */ | 254 | #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a |
252 | #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04 | 255 | #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04 |
256 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02 | ||
257 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12 | ||
258 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22 | ||
259 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06 | ||
260 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16 | ||
261 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26 | ||
262 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A | ||
263 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A | ||
264 | #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A | ||
265 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02 | ||
266 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12 | ||
267 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22 | ||
268 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06 | ||
269 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16 | ||
270 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26 | ||
271 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A | ||
272 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A | ||
273 | #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A | ||
274 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12 | ||
275 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22 | ||
276 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32 | ||
277 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16 | ||
278 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26 | ||
279 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36 | ||
280 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A | ||
281 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A | ||
282 | #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A | ||
253 | 283 | ||
254 | #endif | 284 | #endif |