diff options
Diffstat (limited to 'drivers/ata/sata_sil24.c')
-rw-r--r-- | drivers/ata/sata_sil24.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index e9250514734b..be7726d7686d 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c | |||
@@ -539,12 +539,12 @@ static void sil24_config_port(struct ata_port *ap) | |||
539 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | 539 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); |
540 | 540 | ||
541 | /* zero error counters. */ | 541 | /* zero error counters. */ |
542 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | 542 | writew(0x8000, port + PORT_DECODE_ERR_THRESH); |
543 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | 543 | writew(0x8000, port + PORT_CRC_ERR_THRESH); |
544 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | 544 | writew(0x8000, port + PORT_HSHK_ERR_THRESH); |
545 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | 545 | writew(0x0000, port + PORT_DECODE_ERR_CNT); |
546 | writel(0x0000, port + PORT_CRC_ERR_CNT); | 546 | writew(0x0000, port + PORT_CRC_ERR_CNT); |
547 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | 547 | writew(0x0000, port + PORT_HSHK_ERR_CNT); |
548 | 548 | ||
549 | /* always use 64bit activation */ | 549 | /* always use 64bit activation */ |
550 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); | 550 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); |
@@ -622,6 +622,11 @@ static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, | |||
622 | irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); | 622 | irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); |
623 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); | 623 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); |
624 | 624 | ||
625 | /* | ||
626 | * The barrier is required to ensure that writes to cmd_block reach | ||
627 | * the memory before the write to PORT_CMD_ACTIVATE. | ||
628 | */ | ||
629 | wmb(); | ||
625 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | 630 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
626 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); | 631 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); |
627 | 632 | ||
@@ -865,7 +870,7 @@ static void sil24_qc_prep(struct ata_queued_cmd *qc) | |||
865 | } else { | 870 | } else { |
866 | prb = &cb->atapi.prb; | 871 | prb = &cb->atapi.prb; |
867 | sge = cb->atapi.sge; | 872 | sge = cb->atapi.sge; |
868 | memset(cb->atapi.cdb, 0, 32); | 873 | memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb)); |
869 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); | 874 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
870 | 875 | ||
871 | if (ata_is_data(qc->tf.protocol)) { | 876 | if (ata_is_data(qc->tf.protocol)) { |
@@ -895,6 +900,11 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) | |||
895 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); | 900 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
896 | activate = port + PORT_CMD_ACTIVATE + tag * 8; | 901 | activate = port + PORT_CMD_ACTIVATE + tag * 8; |
897 | 902 | ||
903 | /* | ||
904 | * The barrier is required to ensure that writes to cmd_block reach | ||
905 | * the memory before the write to PORT_CMD_ACTIVATE. | ||
906 | */ | ||
907 | wmb(); | ||
898 | writel((u32)paddr, activate); | 908 | writel((u32)paddr, activate); |
899 | writel((u64)paddr >> 32, activate + 4); | 909 | writel((u64)paddr >> 32, activate + 4); |
900 | 910 | ||