1 files changed, 56 insertions, 64 deletions

diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index dd26bc73bd9a..01457b266f3d 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -25,7 +25,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME        "pata_hpt3x2n"
-#define DRV_VERSION     "0.3.8"
+#define DRV_VERSION     "0.3.10"
 
 enum {
         HPT_PCI_FAST    =       (1 << 31),
@@ -45,25 +45,24 @@ struct hpt_chip {
 
 /* key for bus clock timings
  * bit
- * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
- *        DMA. cycles = value + 1
- * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
- *        DMA. cycles = value + 1
- * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
+ * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
+ *        cycles = value + 1
+ * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
+ *        cycles = value + 1
+ * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  *        register access.
- * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
+ * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
  *        register access.
- * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
- *        during task file register access.
- * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
- *        xfer.
- * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
+ * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
+ * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
+ * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
+ * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  *        register access.
- * 28     UDMA enable
- * 29     DMA enable
- * 30     PIO_MST enable. if set, the chip is in bus master mode during
- *        PIO.
- * 31     FIFO enable.
+ * 28     UDMA enable.
+ * 29     DMA  enable.
+ * 30     PIO_MST enable. If set, the chip is in bus master mode during
+ *        PIO xfer.
+ * 31     FIFO enable. Only for PIO.
  */
 
 /* 66MHz DPLL clocks */
@@ -161,20 +160,12 @@ static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
         return ata_sff_prereset(link, deadline);
 }
 
-/**
- *      hpt3x2n_set_piomode             -       PIO setup
- *      @ap: ATA interface
- *      @adev: device on the interface
- *
- *      Perform PIO mode setup.
- */
-
-static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
+static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
+                             u8 mode)
 {
         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
         u32 addr1, addr2;
-        u32 reg;
-        u32 mode;
+        u32 reg, timing, mask;
         u8 fast;
 
         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
@@ -185,11 +176,32 @@ static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
         fast &= ~0x07;
         pci_write_config_byte(pdev, addr2, fast);
 
+        /* Determine timing mask and find matching mode entry */
+        if (mode < XFER_MW_DMA_0)
+                mask = 0xcfc3ffff;
+        else if (mode < XFER_UDMA_0)
+                mask = 0x31c001ff;
+        else
+                mask = 0x303c0000;
+
+        timing = hpt3x2n_find_mode(ap, mode);
+
         pci_read_config_dword(pdev, addr1, &reg);
-        mode = hpt3x2n_find_mode(ap, adev->pio_mode);
-        mode &= 0xCFC3FFFF;     /* Leave DMA bits alone */
-        reg &= ~0xCFC3FFFF;     /* Strip timing bits */
-        pci_write_config_dword(pdev, addr1, reg | mode);
+        reg = (reg & ~mask) | (timing & mask);
+        pci_write_config_dword(pdev, addr1, reg);
+}
+
+/**
+ *      hpt3x2n_set_piomode             -       PIO setup
+ *      @ap: ATA interface
+ *      @adev: device on the interface
+ *
+ *      Perform PIO mode setup.
+ */
+
+static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+        hpt3x2n_set_mode(ap, adev, adev->pio_mode);
 }
 
 /**
@@ -197,32 +209,12 @@ static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
  *      @ap: ATA interface
  *      @adev: Device being configured
  *
- *      Set up the channel for MWDMA or UDMA modes. Much the same as with
- *      PIO, load the mode number and then set MWDMA or UDMA flag.
+ *      Set up the channel for MWDMA or UDMA modes.
  */
 
 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
-        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-        u32 addr1, addr2;
-        u32 reg, mode, mask;
-        u8 fast;
-
-        addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
-        addr2 = 0x51 + 4 * ap->port_no;
-
-        /* Fast interrupt prediction disable, hold off interrupt disable */
-        pci_read_config_byte(pdev, addr2, &fast);
-        fast &= ~0x07;
-        pci_write_config_byte(pdev, addr2, fast);
-
-        mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
-
-        pci_read_config_dword(pdev, addr1, &reg);
-        mode = hpt3x2n_find_mode(ap, adev->dma_mode);
-        mode &= mask;
-        reg &= ~mask;
-        pci_write_config_dword(pdev, addr1, reg | mode);
+        hpt3x2n_set_mode(ap, adev, adev->dma_mode);
 }
 
 /**
@@ -544,19 +536,19 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
                pci_mhz);
         /* Set our private data up. We only need a few flags so we use
            it directly */
-        if (pci_mhz > 60) {
+        if (pci_mhz > 60)
                 hpriv = (void *)(PCI66 | USE_DPLL);
-                /*
-                 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
-                 * the MISC. register to stretch the UltraDMA Tss timing.
-                 * NOTE: This register is only writeable via I/O space.
-                 */
-                if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
-                        outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
-        }
+
+        /*
+         * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
+         * the MISC. register to stretch the UltraDMA Tss timing.
+         * NOTE: This register is only writeable via I/O space.
+         */
+        if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
+                outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
 
         /* Now kick off ATA set up */
-        return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
+        return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
 }
 
 static const struct pci_device_id hpt3x2n[] = {