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path: root/drivers/ata/ata_piix.c
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Diffstat (limited to 'drivers/ata/ata_piix.c')
-rw-r--r--drivers/ata/ata_piix.c312
1 files changed, 64 insertions, 248 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index fae8404254c0..b7c38eeb498f 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -100,13 +100,11 @@ enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */ 101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */ 102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_SIDPR_BAR = 5, 103 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16, 104 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0, 105 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4, 106 PIIX_SIDPR_DATA = 4,
108 107
109 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112 110
@@ -140,12 +138,11 @@ enum piix_controller_ids {
140 ich_pata_100, /* ICH up to UDMA 100 */ 138 ich_pata_100, /* ICH up to UDMA 100 */
141 ich5_sata, 139 ich5_sata,
142 ich6_sata, 140 ich6_sata,
143 ich6_sata_ahci, 141 ich6m_sata,
144 ich6m_sata_ahci, 142 ich8_sata,
145 ich8_sata_ahci,
146 ich8_2port_sata, 143 ich8_2port_sata,
147 ich8m_apple_sata_ahci, /* locks up on second port enable */ 144 ich8m_apple_sata, /* locks up on second port enable */
148 tolapai_sata_ahci, 145 tolapai_sata,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150}; 147};
151 148
@@ -162,7 +159,7 @@ struct piix_host_priv {
162 159
163static int piix_init_one(struct pci_dev *pdev, 160static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent); 161 const struct pci_device_id *ent);
165static void piix_pata_error_handler(struct ata_port *ap); 162static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
166static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 163static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
167static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 164static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
168static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 165static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
@@ -170,7 +167,6 @@ static int ich_pata_cable_detect(struct ata_port *ap);
170static u8 piix_vmw_bmdma_status(struct ata_port *ap); 167static u8 piix_vmw_bmdma_status(struct ata_port *ap);
171static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val); 168static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
172static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val); 169static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
173static void piix_sidpr_error_handler(struct ata_port *ap);
174#ifdef CONFIG_PM 170#ifdef CONFIG_PM
175static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 171static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
176static int piix_pci_device_resume(struct pci_dev *pdev); 172static int piix_pci_device_resume(struct pci_dev *pdev);
@@ -236,25 +232,27 @@ static const struct pci_device_id piix_pci_tbl[] = {
236 /* 82801FB/FW (ICH6/ICH6W) */ 232 /* 82801FB/FW (ICH6/ICH6W) */
237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 233 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* 82801FR/FRW (ICH6R/ICH6RW) */ 234 /* 82801FR/FRW (ICH6R/ICH6RW) */
239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 235 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ 236 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
241 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 237 * Attach iff the controller is in IDE mode. */
238 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
239 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
246 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 244 /* Enterprise Southbridge 2 (631xESB/632xESB) */
247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* SATA Controller 1 IDE (ICH8) */ 246 /* SATA Controller 1 IDE (ICH8) */
249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller 2 IDE (ICH8) */ 248 /* SATA Controller 2 IDE (ICH8) */
251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* Mobile SATA Controller IDE (ICH8M) */ 250 /* Mobile SATA Controller IDE (ICH8M) */
253 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 251 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
254 /* Mobile SATA Controller IDE (ICH8M), Apple */ 252 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci }, 253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
256 /* SATA Controller IDE (ICH9) */ 254 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 255 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
258 /* SATA Controller IDE (ICH9) */ 256 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 257 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260 /* SATA Controller IDE (ICH9) */ 258 /* SATA Controller IDE (ICH9) */
@@ -264,15 +262,15 @@ static const struct pci_device_id piix_pci_tbl[] = {
264 /* SATA Controller IDE (ICH9M) */ 262 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 263 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9M) */ 264 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 265 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
268 /* SATA Controller IDE (Tolapai) */ 266 /* SATA Controller IDE (Tolapai) */
269 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci }, 267 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
270 /* SATA Controller IDE (ICH10) */ 268 /* SATA Controller IDE (ICH10) */
271 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 269 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (ICH10) */ 270 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 271 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH10) */ 272 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 273 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
276 /* SATA Controller IDE (ICH10) */ 274 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 275 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 276
@@ -291,170 +289,37 @@ static struct pci_driver piix_pci_driver = {
291}; 289};
292 290
293static struct scsi_host_template piix_sht = { 291static struct scsi_host_template piix_sht = {
294 .module = THIS_MODULE, 292 ATA_BMDMA_SHT(DRV_NAME),
295 .name = DRV_NAME,
296 .ioctl = ata_scsi_ioctl,
297 .queuecommand = ata_scsi_queuecmd,
298 .can_queue = ATA_DEF_QUEUE,
299 .this_id = ATA_SHT_THIS_ID,
300 .sg_tablesize = LIBATA_MAX_PRD,
301 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
302 .emulated = ATA_SHT_EMULATED,
303 .use_clustering = ATA_SHT_USE_CLUSTERING,
304 .proc_name = DRV_NAME,
305 .dma_boundary = ATA_DMA_BOUNDARY,
306 .slave_configure = ata_scsi_slave_config,
307 .slave_destroy = ata_scsi_slave_destroy,
308 .bios_param = ata_std_bios_param,
309}; 293};
310 294
311static const struct ata_port_operations piix_pata_ops = { 295static struct ata_port_operations piix_pata_ops = {
296 .inherits = &ata_bmdma_port_ops,
297 .cable_detect = ata_cable_40wire,
312 .set_piomode = piix_set_piomode, 298 .set_piomode = piix_set_piomode,
313 .set_dmamode = piix_set_dmamode, 299 .set_dmamode = piix_set_dmamode,
314 .mode_filter = ata_pci_default_filter, 300 .prereset = piix_pata_prereset,
315 301};
316 .tf_load = ata_tf_load,
317 .tf_read = ata_tf_read,
318 .check_status = ata_check_status,
319 .exec_command = ata_exec_command,
320 .dev_select = ata_std_dev_select,
321
322 .bmdma_setup = ata_bmdma_setup,
323 .bmdma_start = ata_bmdma_start,
324 .bmdma_stop = ata_bmdma_stop,
325 .bmdma_status = ata_bmdma_status,
326 .qc_prep = ata_qc_prep,
327 .qc_issue = ata_qc_issue_prot,
328 .data_xfer = ata_data_xfer,
329
330 .freeze = ata_bmdma_freeze,
331 .thaw = ata_bmdma_thaw,
332 .error_handler = piix_pata_error_handler,
333 .post_internal_cmd = ata_bmdma_post_internal_cmd,
334 .cable_detect = ata_cable_40wire,
335
336 .irq_clear = ata_bmdma_irq_clear,
337 .irq_on = ata_irq_on,
338 302
339 .port_start = ata_port_start, 303static struct ata_port_operations piix_vmw_ops = {
304 .inherits = &piix_pata_ops,
305 .bmdma_status = piix_vmw_bmdma_status,
340}; 306};
341 307
342static const struct ata_port_operations ich_pata_ops = { 308static struct ata_port_operations ich_pata_ops = {
343 .set_piomode = piix_set_piomode, 309 .inherits = &piix_pata_ops,
344 .set_dmamode = ich_set_dmamode,
345 .mode_filter = ata_pci_default_filter,
346
347 .tf_load = ata_tf_load,
348 .tf_read = ata_tf_read,
349 .check_status = ata_check_status,
350 .exec_command = ata_exec_command,
351 .dev_select = ata_std_dev_select,
352
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357 .qc_prep = ata_qc_prep,
358 .qc_issue = ata_qc_issue_prot,
359 .data_xfer = ata_data_xfer,
360
361 .freeze = ata_bmdma_freeze,
362 .thaw = ata_bmdma_thaw,
363 .error_handler = piix_pata_error_handler,
364 .post_internal_cmd = ata_bmdma_post_internal_cmd,
365 .cable_detect = ich_pata_cable_detect, 310 .cable_detect = ich_pata_cable_detect,
366 311 .set_dmamode = ich_set_dmamode,
367 .irq_clear = ata_bmdma_irq_clear,
368 .irq_on = ata_irq_on,
369
370 .port_start = ata_port_start,
371}; 312};
372 313
373static const struct ata_port_operations piix_sata_ops = { 314static struct ata_port_operations piix_sata_ops = {
374 .tf_load = ata_tf_load, 315 .inherits = &ata_bmdma_port_ops,
375 .tf_read = ata_tf_read,
376 .check_status = ata_check_status,
377 .exec_command = ata_exec_command,
378 .dev_select = ata_std_dev_select,
379
380 .bmdma_setup = ata_bmdma_setup,
381 .bmdma_start = ata_bmdma_start,
382 .bmdma_stop = ata_bmdma_stop,
383 .bmdma_status = ata_bmdma_status,
384 .qc_prep = ata_qc_prep,
385 .qc_issue = ata_qc_issue_prot,
386 .data_xfer = ata_data_xfer,
387
388 .freeze = ata_bmdma_freeze,
389 .thaw = ata_bmdma_thaw,
390 .error_handler = ata_bmdma_error_handler,
391 .post_internal_cmd = ata_bmdma_post_internal_cmd,
392
393 .irq_clear = ata_bmdma_irq_clear,
394 .irq_on = ata_irq_on,
395
396 .port_start = ata_port_start,
397}; 316};
398 317
399static const struct ata_port_operations piix_vmw_ops = { 318static struct ata_port_operations piix_sidpr_sata_ops = {
400 .set_piomode = piix_set_piomode, 319 .inherits = &piix_sata_ops,
401 .set_dmamode = piix_set_dmamode, 320 .hardreset = sata_std_hardreset,
402 .mode_filter = ata_pci_default_filter,
403
404 .tf_load = ata_tf_load,
405 .tf_read = ata_tf_read,
406 .check_status = ata_check_status,
407 .exec_command = ata_exec_command,
408 .dev_select = ata_std_dev_select,
409
410 .bmdma_setup = ata_bmdma_setup,
411 .bmdma_start = ata_bmdma_start,
412 .bmdma_stop = ata_bmdma_stop,
413 .bmdma_status = piix_vmw_bmdma_status,
414 .qc_prep = ata_qc_prep,
415 .qc_issue = ata_qc_issue_prot,
416 .data_xfer = ata_data_xfer,
417
418 .freeze = ata_bmdma_freeze,
419 .thaw = ata_bmdma_thaw,
420 .error_handler = piix_pata_error_handler,
421 .post_internal_cmd = ata_bmdma_post_internal_cmd,
422 .cable_detect = ata_cable_40wire,
423
424 .irq_handler = ata_interrupt,
425 .irq_clear = ata_bmdma_irq_clear,
426 .irq_on = ata_irq_on,
427
428 .port_start = ata_port_start,
429};
430
431static const struct ata_port_operations piix_sidpr_sata_ops = {
432 .tf_load = ata_tf_load,
433 .tf_read = ata_tf_read,
434 .check_status = ata_check_status,
435 .exec_command = ata_exec_command,
436 .dev_select = ata_std_dev_select,
437
438 .bmdma_setup = ata_bmdma_setup,
439 .bmdma_start = ata_bmdma_start,
440 .bmdma_stop = ata_bmdma_stop,
441 .bmdma_status = ata_bmdma_status,
442 .qc_prep = ata_qc_prep,
443 .qc_issue = ata_qc_issue_prot,
444 .data_xfer = ata_data_xfer,
445
446 .scr_read = piix_sidpr_scr_read, 321 .scr_read = piix_sidpr_scr_read,
447 .scr_write = piix_sidpr_scr_write, 322 .scr_write = piix_sidpr_scr_write,
448
449 .freeze = ata_bmdma_freeze,
450 .thaw = ata_bmdma_thaw,
451 .error_handler = piix_sidpr_error_handler,
452 .post_internal_cmd = ata_bmdma_post_internal_cmd,
453
454 .irq_clear = ata_bmdma_irq_clear,
455 .irq_on = ata_irq_on,
456
457 .port_start = ata_port_start,
458}; 323};
459 324
460static const struct piix_map_db ich5_map_db = { 325static const struct piix_map_db ich5_map_db = {
@@ -553,12 +418,11 @@ static const struct piix_map_db tolapai_map_db = {
553static const struct piix_map_db *piix_map_db_table[] = { 418static const struct piix_map_db *piix_map_db_table[] = {
554 [ich5_sata] = &ich5_map_db, 419 [ich5_sata] = &ich5_map_db,
555 [ich6_sata] = &ich6_map_db, 420 [ich6_sata] = &ich6_map_db,
556 [ich6_sata_ahci] = &ich6_map_db, 421 [ich6m_sata] = &ich6m_map_db,
557 [ich6m_sata_ahci] = &ich6m_map_db, 422 [ich8_sata] = &ich8_map_db,
558 [ich8_sata_ahci] = &ich8_map_db,
559 [ich8_2port_sata] = &ich8_2port_map_db, 423 [ich8_2port_sata] = &ich8_2port_map_db,
560 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db, 424 [ich8m_apple_sata] = &ich8m_apple_map_db,
561 [tolapai_sata_ahci] = &tolapai_map_db, 425 [tolapai_sata] = &tolapai_map_db,
562}; 426};
563 427
564static struct ata_port_info piix_port_info[] = { 428static struct ata_port_info piix_port_info[] = {
@@ -624,28 +488,18 @@ static struct ata_port_info piix_port_info[] = {
624 .port_ops = &piix_sata_ops, 488 .port_ops = &piix_sata_ops,
625 }, 489 },
626 490
627 [ich6_sata_ahci] = 491 [ich6m_sata] =
628 {
629 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
630 .pio_mask = 0x1f, /* pio0-4 */
631 .mwdma_mask = 0x07, /* mwdma0-2 */
632 .udma_mask = ATA_UDMA6,
633 .port_ops = &piix_sata_ops,
634 },
635
636 [ich6m_sata_ahci] =
637 { 492 {
638 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, 493 .flags = PIIX_SATA_FLAGS,
639 .pio_mask = 0x1f, /* pio0-4 */ 494 .pio_mask = 0x1f, /* pio0-4 */
640 .mwdma_mask = 0x07, /* mwdma0-2 */ 495 .mwdma_mask = 0x07, /* mwdma0-2 */
641 .udma_mask = ATA_UDMA6, 496 .udma_mask = ATA_UDMA6,
642 .port_ops = &piix_sata_ops, 497 .port_ops = &piix_sata_ops,
643 }, 498 },
644 499
645 [ich8_sata_ahci] = 500 [ich8_sata] =
646 { 501 {
647 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI | 502 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
648 PIIX_FLAG_SIDPR,
649 .pio_mask = 0x1f, /* pio0-4 */ 503 .pio_mask = 0x1f, /* pio0-4 */
650 .mwdma_mask = 0x07, /* mwdma0-2 */ 504 .mwdma_mask = 0x07, /* mwdma0-2 */
651 .udma_mask = ATA_UDMA6, 505 .udma_mask = ATA_UDMA6,
@@ -654,27 +508,25 @@ static struct ata_port_info piix_port_info[] = {
654 508
655 [ich8_2port_sata] = 509 [ich8_2port_sata] =
656 { 510 {
657 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI | 511 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
658 PIIX_FLAG_SIDPR,
659 .pio_mask = 0x1f, /* pio0-4 */ 512 .pio_mask = 0x1f, /* pio0-4 */
660 .mwdma_mask = 0x07, /* mwdma0-2 */ 513 .mwdma_mask = 0x07, /* mwdma0-2 */
661 .udma_mask = ATA_UDMA6, 514 .udma_mask = ATA_UDMA6,
662 .port_ops = &piix_sata_ops, 515 .port_ops = &piix_sata_ops,
663 }, 516 },
664 517
665 [tolapai_sata_ahci] = 518 [tolapai_sata] =
666 { 519 {
667 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI, 520 .flags = PIIX_SATA_FLAGS,
668 .pio_mask = 0x1f, /* pio0-4 */ 521 .pio_mask = 0x1f, /* pio0-4 */
669 .mwdma_mask = 0x07, /* mwdma0-2 */ 522 .mwdma_mask = 0x07, /* mwdma0-2 */
670 .udma_mask = ATA_UDMA6, 523 .udma_mask = ATA_UDMA6,
671 .port_ops = &piix_sata_ops, 524 .port_ops = &piix_sata_ops,
672 }, 525 },
673 526
674 [ich8m_apple_sata_ahci] = 527 [ich8m_apple_sata] =
675 { 528 {
676 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI | 529 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
677 PIIX_FLAG_SIDPR,
678 .pio_mask = 0x1f, /* pio0-4 */ 530 .pio_mask = 0x1f, /* pio0-4 */
679 .mwdma_mask = 0x07, /* mwdma0-2 */ 531 .mwdma_mask = 0x07, /* mwdma0-2 */
680 .udma_mask = ATA_UDMA6, 532 .udma_mask = ATA_UDMA6,
@@ -683,7 +535,6 @@ static struct ata_port_info piix_port_info[] = {
683 535
684 [piix_pata_vmw] = 536 [piix_pata_vmw] =
685 { 537 {
686 .sht = &piix_sht,
687 .flags = PIIX_PATA_FLAGS, 538 .flags = PIIX_PATA_FLAGS,
688 .pio_mask = 0x1f, /* pio0-4 */ 539 .pio_mask = 0x1f, /* pio0-4 */
689 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 540 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
@@ -776,13 +627,7 @@ static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
776 627
777 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 628 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
778 return -ENOENT; 629 return -ENOENT;
779 return ata_std_prereset(link, deadline); 630 return ata_sff_prereset(link, deadline);
780}
781
782static void piix_pata_error_handler(struct ata_port *ap)
783{
784 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
785 ata_std_postreset);
786} 631}
787 632
788/** 633/**
@@ -1168,35 +1013,6 @@ static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1168 return 0; 1013 return 0;
1169} 1014}
1170 1015
1171static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class,
1172 unsigned long deadline)
1173{
1174 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1175 int rc;
1176
1177 /* do hardreset */
1178 rc = sata_link_hardreset(link, timing, deadline);
1179 if (rc) {
1180 ata_link_printk(link, KERN_ERR,
1181 "COMRESET failed (errno=%d)\n", rc);
1182 return rc;
1183 }
1184
1185 /* TODO: phy layer with polling, timeouts, etc. */
1186 if (ata_link_offline(link)) {
1187 *class = ATA_DEV_NONE;
1188 return 0;
1189 }
1190
1191 return -EAGAIN;
1192}
1193
1194static void piix_sidpr_error_handler(struct ata_port *ap)
1195{
1196 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1197 piix_sidpr_hardreset, ata_std_postreset);
1198}
1199
1200#ifdef CONFIG_PM 1016#ifdef CONFIG_PM
1201static int piix_broken_suspend(void) 1017static int piix_broken_suspend(void)
1202{ 1018{
@@ -1633,6 +1449,16 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
1633 if (rc) 1449 if (rc)
1634 return rc; 1450 return rc;
1635 1451
1452 /* ICH6R may be driven by either ata_piix or ahci driver
1453 * regardless of BIOS configuration. Make sure AHCI mode is
1454 * off.
1455 */
1456 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1457 int rc = piix_disable_ahci(pdev);
1458 if (rc)
1459 return rc;
1460 }
1461
1636 /* SATA map init can change port_info, do it before prepping host */ 1462 /* SATA map init can change port_info, do it before prepping host */
1637 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1463 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1638 if (!hpriv) 1464 if (!hpriv)
@@ -1642,22 +1468,12 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
1642 hpriv->map = piix_init_sata_map(pdev, port_info, 1468 hpriv->map = piix_init_sata_map(pdev, port_info,
1643 piix_map_db_table[ent->driver_data]); 1469 piix_map_db_table[ent->driver_data]);
1644 1470
1645 rc = ata_pci_prepare_sff_host(pdev, ppi, &host); 1471 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1646 if (rc) 1472 if (rc)
1647 return rc; 1473 return rc;
1648 host->private_data = hpriv; 1474 host->private_data = hpriv;
1649 1475
1650 /* initialize controller */ 1476 /* initialize controller */
1651 if (port_flags & PIIX_FLAG_AHCI) {
1652 u8 tmp;
1653 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1654 if (tmp == PIIX_AHCI_DEVICE) {
1655 rc = piix_disable_ahci(pdev);
1656 if (rc)
1657 return rc;
1658 }
1659 }
1660
1661 if (port_flags & ATA_FLAG_SATA) { 1477 if (port_flags & ATA_FLAG_SATA) {
1662 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1478 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1663 piix_init_sidpr(host); 1479 piix_init_sidpr(host);
@@ -1686,7 +1502,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
1686 } 1502 }
1687 1503
1688 pci_set_master(pdev); 1504 pci_set_master(pdev);
1689 return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht); 1505 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1690} 1506}
1691 1507
1692static int __init piix_init(void) 1508static int __init piix_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 12:22:37 -0400