1 files changed, 74 insertions, 26 deletions

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 1db93b619074..17ee6ed985d9 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -49,6 +49,10 @@
 #define DRV_NAME        "ahci"
 #define DRV_VERSION     "3.0"
 
+static int ahci_skip_host_reset;
+module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
+MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
+
 static int ahci_enable_alpm(struct ata_port *ap,
                 enum link_pm policy);
 static void ahci_disable_alpm(struct ata_port *ap);
@@ -186,6 +190,7 @@ enum {
         AHCI_HFLAG_NO_MSI               = (1 << 5), /* no PCI MSI */
         AHCI_HFLAG_NO_PMP               = (1 << 6), /* no PMP */
         AHCI_HFLAG_NO_HOTPLUG           = (1 << 7), /* ignore PxSERR.DIAG.N */
+        AHCI_HFLAG_SECT255              = (1 << 8), /* max 255 sectors */
 
         /* ap->flags bits */
 
@@ -255,6 +260,7 @@ static void ahci_vt8251_error_handler(struct ata_port *ap);
 static void ahci_p5wdh_error_handler(struct ata_port *ap);
 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
 static int ahci_port_resume(struct ata_port *ap);
+static void ahci_dev_config(struct ata_device *dev);
 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
                                u32 opts);
@@ -294,6 +300,8 @@ static const struct ata_port_operations ahci_ops = {
         .check_altstatus        = ahci_check_status,
         .dev_select             = ata_noop_dev_select,
 
+        .dev_config             = ahci_dev_config,
+
         .tf_read                = ahci_tf_read,
 
         .qc_defer               = sata_pmp_qc_defer_cmd_switch,
@@ -425,7 +433,7 @@ static const struct ata_port_info ahci_port_info[] = {
         /* board_ahci_sb600 */
         {
                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
-                                 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
+                                 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
                 .flags          = AHCI_FLAG_COMMON,
                 .link_flags     = AHCI_LFLAG_COMMON,
                 .pio_mask       = 0x1f, /* pio0-4 */
@@ -563,6 +571,18 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci },            /* MCP79 */
         { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci },            /* MCP79 */
         { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci },            /* MCP79 */
+        { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci },            /* MCP7B */
+        { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci },            /* MCP7B */
 
         /* SiS */
         { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
@@ -571,6 +591,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 
         /* Marvell */
         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
+        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 
         /* Generic, PCI class code for AHCI */
         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -645,6 +666,7 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
         void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
         u32 cap, port_map;
         int i;
+        int mv;
 
         /* make sure AHCI mode is enabled before accessing CAP */
         ahci_enable_ahci(mmio);
@@ -668,7 +690,7 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
                 cap &= ~HOST_CAP_NCQ;
         }
 
-        if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
+        if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
                 dev_printk(KERN_INFO, &pdev->dev,
                            "controller can't do PMP, turning off CAP_PMP\n");
                 cap &= ~HOST_CAP_PMP;
@@ -680,12 +702,16 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
          * presence register, as bit 4 (counting from 0)
          */
         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
+                if (pdev->device == 0x6121)
+                        mv = 0x3;
+                else
+                        mv = 0xf;
                 dev_printk(KERN_ERR, &pdev->dev,
                            "MV_AHCI HACK: port_map %x -> %x\n",
-                           hpriv->port_map,
-                           hpriv->port_map & 0xf);
+                           port_map,
+                           port_map & mv);
 
-                port_map &= 0xf;
+                port_map &= mv;
         }
 
         /* cross check port_map and cap.n_ports */
@@ -1072,29 +1098,35 @@ static int ahci_reset_controller(struct ata_host *host)
         ahci_enable_ahci(mmio);
 
         /* global controller reset */
-        tmp = readl(mmio + HOST_CTL);
-        if ((tmp & HOST_RESET) == 0) {
-                writel(tmp | HOST_RESET, mmio + HOST_CTL);
-                readl(mmio + HOST_CTL); /* flush */
-        }
+        if (!ahci_skip_host_reset) {
+                tmp = readl(mmio + HOST_CTL);
+                if ((tmp & HOST_RESET) == 0) {
+                        writel(tmp | HOST_RESET, mmio + HOST_CTL);
+                        readl(mmio + HOST_CTL); /* flush */
+                }
 
-        /* reset must complete within 1 second, or
-         * the hardware should be considered fried.
-         */
-        ssleep(1);
+                /* reset must complete within 1 second, or
+                 * the hardware should be considered fried.
+                 */
+                ssleep(1);
 
-        tmp = readl(mmio + HOST_CTL);
-        if (tmp & HOST_RESET) {
-                dev_printk(KERN_ERR, host->dev,
-                           "controller reset failed (0x%x)\n", tmp);
-                return -EIO;
-        }
+                tmp = readl(mmio + HOST_CTL);
+                if (tmp & HOST_RESET) {
+                        dev_printk(KERN_ERR, host->dev,
+                                   "controller reset failed (0x%x)\n", tmp);
+                        return -EIO;
+                }
 
-        /* turn on AHCI mode */
-        ahci_enable_ahci(mmio);
+                /* turn on AHCI mode */
+                ahci_enable_ahci(mmio);
 
-        /* some registers might be cleared on reset.  restore initial values */
-        ahci_restore_initial_config(host);
+                /* Some registers might be cleared on reset.  Restore
+                 * initial values.
+                 */
+                ahci_restore_initial_config(host);
+        } else
+                dev_printk(KERN_INFO, host->dev,
+                           "skipping global host reset\n");
 
         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
                 u16 tmp16;
@@ -1146,9 +1178,14 @@ static void ahci_init_controller(struct ata_host *host)
         int i;
         void __iomem *port_mmio;
         u32 tmp;
+        int mv;
 
         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
-                port_mmio = __ahci_port_base(host, 4);
+                if (pdev->device == 0x6121)
+                        mv = 2;
+                else
+                        mv = 4;
+                port_mmio = __ahci_port_base(host, mv);
 
                 writel(0, port_mmio + PORT_IRQ_MASK);
 
@@ -1176,6 +1213,14 @@ static void ahci_init_controller(struct ata_host *host)
         VPRINTK("HOST_CTL 0x%x\n", tmp);
 }
 
+static void ahci_dev_config(struct ata_device *dev)
+{
+        struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
+
+        if (hpriv->flags & AHCI_HFLAG_SECT255)
+                dev->max_sectors = 255;
+}
+
 static unsigned int ahci_dev_classify(struct ata_port *ap)
 {
         void __iomem *port_mmio = ahci_port_base(ap);
@@ -2217,7 +2262,10 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (rc)
                 return rc;
 
-        rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
+        /* AHCI controllers often implement SFF compatible interface.
+         * Grab all PCI BARs just in case.
+         */
+        rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
         if (rc == -EBUSY)
                 pcim_pin_device(pdev);
         if (rc)