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-rw-r--r--arch/powerpc/boot/dts/fsl/t1040si-post.dtsi430
-rw-r--r--arch/powerpc/boot/dts/fsl/t1042si-post.dtsi37
-rw-r--r--arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi104
3 files changed, 571 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000000000000..12e597eea3c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,430 @@
1/*
2 * T1040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42&pci0 {
43 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
44 device_type = "pci";
45 #size-cells = <2>;
46 #address-cells = <3>;
47 bus-range = <0x0 0xff>;
48 interrupts = <20 2 0 0>;
49 fsl,iommu-parent = <&pamu0>;
50 pcie@0 {
51 reg = <0 0 0 0 0>;
52 #interrupt-cells = <1>;
53 #size-cells = <2>;
54 #address-cells = <3>;
55 device_type = "pci";
56 interrupts = <20 2 0 0>;
57 interrupt-map-mask = <0xf800 0 0 7>;
58 interrupt-map = <
59 /* IDSEL 0x0 */
60 0000 0 0 1 &mpic 40 1 0 0
61 0000 0 0 2 &mpic 1 1 0 0
62 0000 0 0 3 &mpic 2 1 0 0
63 0000 0 0 4 &mpic 3 1 0 0
64 >;
65 };
66};
67
68&pci1 {
69 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
70 device_type = "pci";
71 #size-cells = <2>;
72 #address-cells = <3>;
73 bus-range = <0 0xff>;
74 interrupts = <21 2 0 0>;
75 fsl,iommu-parent = <&pamu0>;
76 pcie@0 {
77 reg = <0 0 0 0 0>;
78 #interrupt-cells = <1>;
79 #size-cells = <2>;
80 #address-cells = <3>;
81 device_type = "pci";
82 interrupts = <21 2 0 0>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <
85 /* IDSEL 0x0 */
86 0000 0 0 1 &mpic 41 1 0 0
87 0000 0 0 2 &mpic 5 1 0 0
88 0000 0 0 3 &mpic 6 1 0 0
89 0000 0 0 4 &mpic 7 1 0 0
90 >;
91 };
92};
93
94&pci2 {
95 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
96 device_type = "pci";
97 #size-cells = <2>;
98 #address-cells = <3>;
99 bus-range = <0x0 0xff>;
100 interrupts = <22 2 0 0>;
101 fsl,iommu-parent = <&pamu0>;
102 pcie@0 {
103 reg = <0 0 0 0 0>;
104 #interrupt-cells = <1>;
105 #size-cells = <2>;
106 #address-cells = <3>;
107 device_type = "pci";
108 interrupts = <22 2 0 0>;
109 interrupt-map-mask = <0xf800 0 0 7>;
110 interrupt-map = <
111 /* IDSEL 0x0 */
112 0000 0 0 1 &mpic 42 1 0 0
113 0000 0 0 2 &mpic 9 1 0 0
114 0000 0 0 3 &mpic 10 1 0 0
115 0000 0 0 4 &mpic 11 1 0 0
116 >;
117 };
118};
119
120&pci3 {
121 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
122 device_type = "pci";
123 #size-cells = <2>;
124 #address-cells = <3>;
125 bus-range = <0x0 0xff>;
126 interrupts = <23 2 0 0>;
127 fsl,iommu-parent = <&pamu0>;
128 pcie@0 {
129 reg = <0 0 0 0 0>;
130 #interrupt-cells = <1>;
131 #size-cells = <2>;
132 #address-cells = <3>;
133 device_type = "pci";
134 interrupts = <23 2 0 0>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 interrupt-map = <
137 /* IDSEL 0x0 */
138 0000 0 0 1 &mpic 43 1 0 0
139 0000 0 0 2 &mpic 0 1 0 0
140 0000 0 0 3 &mpic 4 1 0 0
141 0000 0 0 4 &mpic 8 1 0 0
142 >;
143 };
144};
145
146&dcsr {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "fsl,dcsr", "simple-bus";
150
151 dcsr-epu@0 {
152 compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
153 interrupts = <52 2 0 0
154 84 2 0 0
155 85 2 0 0>;
156 reg = <0x0 0x1000>;
157 };
158 dcsr-npc {
159 compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
160 reg = <0x1000 0x1000 0x1002000 0x10000>;
161 };
162 dcsr-nxc@2000 {
163 compatible = "fsl,dcsr-nxc";
164 reg = <0x2000 0x1000>;
165 };
166 dcsr-corenet {
167 compatible = "fsl,dcsr-corenet";
168 reg = <0x8000 0x1000 0x1A000 0x1000>;
169 };
170 dcsr-dpaa@9000 {
171 compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
172 reg = <0x9000 0x1000>;
173 };
174 dcsr-ocn@11000 {
175 compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
176 reg = <0x11000 0x1000>;
177 };
178 dcsr-ddr@12000 {
179 compatible = "fsl,dcsr-ddr";
180 dev-handle = <&ddr1>;
181 reg = <0x12000 0x1000>;
182 };
183 dcsr-nal@18000 {